Changeset 1f4db180 in rtems


Ignore:
Timestamp:
Mar 25, 2010, 8:26:51 PM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 5, master
Children:
956531b
Parents:
2f5435a4
Message:

fix timer support, some reworks

Location:
c/src/lib
Files:
9 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen5200/ChangeLog

    r2f5435a4 r1f4db180  
     12010-03-25      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * configure.ac, include/bsp.h, console/console.c, start/start.S:
     4        move more configuration constants to configure.ac
     5
    162010-03-16      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
    27
  • c/src/lib/libbsp/powerpc/gen5200/configure.ac

    r2f5435a4 r1f4db180  
    2626 is turned on.])
    2727
     28RTEMS_BSPOPTS_SET([HAS_UBOOT],[icecube],[1])
     29RTEMS_BSPOPTS_SET([HAS_UBOOT],[pm520_*],[1])
     30RTEMS_BSPOPTS_HELP([HAS_UBOOT],
     31[If defined, board boots via U-Boot])
     32
    2833RTEMS_BSPOPTS_SET([BENCHMARK_IRQ_PROCESSING],[*],[0])
    2934RTEMS_BSPOPTS_HELP([BENCHMARK_IRQ_PROCESSING],
    30 [If defined, enable code to benchmark IRQ processing.])
     35[If set to !0, enable code to benchmark IRQ processing.])
    3136
    3237RTEMS_BSPOPTS_SET([ALLOW_IRQ_NESTING],[icecube],[0])
    3338RTEMS_BSPOPTS_SET([ALLOW_IRQ_NESTING],[*],[1])
    3439RTEMS_BSPOPTS_HELP([ALLOW_IRQ_NESTING],
    35 [If defined, allow nested IRQ processing.])
     40[If set to !0, allow nested IRQ processing.])
    3641
    3742RTEMS_BSPOPTS_SET([BSP_PRESS_KEY_FOR_RESET],[icecube],[1])
     43RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[pm520_cr825],[1])
    3844RTEMS_BSPOPTS_SET([BSP_PRESS_KEY_FOR_RESET],[*],[0])
    3945RTEMS_BSPOPTS_HELP([BSP_PRESS_KEY_FOR_RESET],
    40 [If defined, print a message and wait until pressed before resetting
     46[If set to !0, print a message and wait until pressed before resetting
    4147 board when application exits.])
    4248
    4349RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[icecube],[1])
     50RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[pm520_*],[1])
     51RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[brs5l],[1])
    4452RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[*],[0])
    4553RTEMS_BSPOPTS_HELP([BSP_RESET_BOARD_AT_EXIT],
    46 [If defined, reset the board when the application exits.])
     54[If set to !0, reset the board when the application exits.])
     55
     56RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_ze30],[0x337F3F77])
     57RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_ze30],[0x01552114])
     58
     59RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[pm520_cr825],[0x330F0F77])
     60RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_cr825],[0x01050444])
     61
     62RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[brs5l],[0xb30F0F77])
     63RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[brs5l],[0x91050444])
     64
     65RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[icecube],[0x330F0F77])
     66RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[icecube],[0x01050444])
     67
     68RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[*],[0x330F0F77])
     69RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[*],[0x01050444])
     70
     71RTEMS_BSPOPTS_HELP([BSP_GPIOPCR_INITMASK],
     72[defines the bits modified in the MPC5200 GPIOPCR register during init.
     73 Must match the hardware requirements])
     74RTEMS_BSPOPTS_HELP([BSP_GPIOPCR_INITVAL],
     75[defines the bit values written in the MPC5200 GPIOPCR register during init.
     76 Must match the hardware requirements])
     77
     78## on ze30, we have PSC1/4/5/6 ...
     79RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_ze30],[0x39])
     80## on cr825, we have PSC1/2/3
     81RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_cr825],[0x07])
     82## on brs5l, we have PSC1/2/3
     83RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[brs5l],[0x07])
     84## on icecube, we only have PSC1
     85RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[icecube],[0x01])
     86RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[*],[0x01])
     87RTEMS_BSPOPTS_HELP([BSP_UART_AVAIL_MASK],
     88[bit mask to specify the UARTS (PSCs), which should be enabled on this board.
     89 Must match the hardware requirements. PSC1 corresponds to the LSB])
    4790
    4891RTEMS_BSPOPTS_SET([PM520_ZE30],[pm520_ze30],[1])
  • c/src/lib/libbsp/powerpc/gen5200/console/console.c

    r2f5435a4 r1f4db180  
    116116#define PSC6_MINOR      5
    117117
    118 uint32_t mpc5200_uart_avail_mask = GEN5200_UART_AVAIL_MASK;
     118uint32_t mpc5200_uart_avail_mask = BSP_UART_AVAIL_MASK;
    119119
    120120#if defined(UARTS_USE_TERMIOS_INT)
  • c/src/lib/libbsp/powerpc/gen5200/include/bsp.h

    r2f5435a4 r1f4db180  
    7272#if defined(PM520_ZE30)
    7373#define PM520
    74 #define GPIOPCR_INITMASK 0x337F3F77
    75 #define GPIOPCR_INITVAL  0x01552114
    76 /* we have PSC1/4/5/6 */
    77 /* #define GEN5200_UART_AVAIL_MASK 0x39 */
    78 #define GEN5200_UART_AVAIL_MASK 0x39
    7974#endif
    8075/*
     
    8378#if defined(PM520_CR825)
    8479#define PM520
    85 #define GPIOPCR_INITMASK 0x330F0F77
    86 #define GPIOPCR_INITVAL  0x01050444
    87 /* we have PSC1/2/3*/
    88 #define GEN5200_UART_AVAIL_MASK 0x07
    8980#endif
    9081
     
    9384 * IMD Custom Board BRS5L
    9485 */
    95 #define GPIOPCR_INITMASK 0xb30F0F77
    96 #define GPIOPCR_INITVAL  0x91050444
    97 /* we have PSC1/2/3 */
    98 #define GEN5200_UART_AVAIL_MASK 0x07
    99 
    100 /* we need the low level initialization in start.S*/
    101 #define NEED_LOW_LEVEL_INIT
    10286
    10387#define HAS_NVRAM_93CXX
     88
    10489#elif defined (PM520)
    105 
    106 #define HAS_UBOOT
    10790
    10891#elif defined (icecube)
     
    11396 *     Embedded Planet EP5200
    11497 */
    115 
    116 #define HAS_UBOOT
    117 
    118 /* These are copied from PM520 but seem to work so OK */
    119 #define GPIOPCR_INITMASK 0x330F0F77
    120 #define GPIOPCR_INITVAL  0x01050444
    121 
    122 /* we only have PSC1 */
    123 #define GEN5200_UART_AVAIL_MASK 0x01
    12498
    12599#else
     
    148122
    149123extern bd_t bsp_uboot_board_info;
     124#else
     125
     126/* we need the low level initialization in start.S*/
     127#define NEED_LOW_LEVEL_INIT
     128
     129
    150130#endif
    151131
  • c/src/lib/libbsp/powerpc/gen5200/start/start.S

    r2f5435a4 r1f4db180  
    183183        /* init GPIOPCR */
    184184        lwz     r29,GPIOPCR(r31)
    185         LWI     r30, GPIOPCR_INITMASK
     185        LWI     r30, BSP_GPIOPCR_INITMASK
    186186        not     r30,r30
    187187        and     r29,r29,r30
    188         LWI     r30, GPIOPCR_INITVAL
     188        LWI     r30, BSP_GPIOPCR_INITVAL
    189189        or      r29,r29,r30
    190190        stw     r29, GPIOPCR(r31)
     
    238238
    239239
    240 #endif
     240#endif /* BRS5L */
    241241
    242242
     
    398398        bl      clr_mem                         /* Clear onchip SRAM */
    399399
    400 #endif /* defined(BRS5L) */
     400#endif /* defined(NEED_LOW_LEVEL_INIT) */
    401401/* clear .bss section (unique for ROM startup) */
    402402        LWI     r30, bsp_section_bss_start      /* get start address of bss section */
     
    426426        bl      SYM (boot_card)                 /* Call the first C routine */
    427427
    428 #if defined(BRS5L)
    429428twiddle:
    430429        b       twiddle                         /* We don't expect to return from boot_card but if we do */
    431430                                                /* wait here for watchdog to kick us into hard reset     */
    432431
     432#if defined(NEED_LOW_LEVEL_INIT)
    433433SDRAM_init:
    434 #if defined (BRS5L)
     434#if defined(BRS5L)
    435435      /* set GPIO_WKUP7 pin low for 66MHz buffering */
    436436      /* or high for 133MHz registered buffering    */
     
    459459
    460460#endif
    461 #if 0
    462         LWI     r30, 0xC2222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
    463         stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
    464                                                 /* Refr.2No-Read delay=0x06, Write latency=0x0 */
    465 #else
    466461        /* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf:       */
    467462        /* set 5 delays to their maximum to support two banks           */
     
    469464        stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
    470465                                                /* Refr.2No-Read delay=0x06, Write latency=0x0 */
    471 #endif
    472466
    473467        LWI     r30, 0xCCC70004                 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
     
    560554copy_image_end:
    561555        blr
    562 #endif /* defined(BRS5L) */
     556#endif /* defined(NEED_LOW_LEVEL_INIT) */
    563557
    564558FID_DCache:
     
    643637        SETBITS r30, r29, MSR_FP
    644638        mtmsr   r30                             /* enable FPU and FPU exceptions */
    645 
    646 #if 0
    647         LA      r29, bsp_ram_start
    648         stw     r29, 0x0(r29)
    649 #endif
    650639
    651640        lfd     f0, 0(r29)
  • c/src/lib/libcpu/powerpc/ChangeLog

    r2f5435a4 r1f4db180  
     12010-03-25      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * Makefile.am, mpc55xx/include/siu.h, mpc55xx/siu/siu.c:
     4        add generic SIU support
     5        add timer support, on timebase
     6        * mpc55xx/edma/edma.c: fix init call to be prototype
     7        * mpc55xx/esci/esci.c: adapted to new prototype for *_write function
     8        * mpc55xx/include/reg-defs.h, mpc55xx/include/regs.h,
     9        mpc55xx/misc/fmpll.S:
     10        add support for mpc551x registers
     11        * mpc6xx/timer/timer.c: fix typo
     12
    1132009-12-17      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
    214
  • c/src/lib/libcpu/powerpc/Makefile.am

    r2f5435a4 r1f4db180  
    417417        mpc55xx/include/mpc55xx.h \
    418418        mpc55xx/include/esci.h \
     419        mpc55xx/include/siu.h \
    419420        mpc55xx/include/watchdog.h
    420421
     
    426427mpc55xx_irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    427428
     429# mpc6xx/timer
     430noinst_PROGRAMS += mpc55xx/timer.rel
     431mpc55xx_timer_rel_SOURCES = mpc6xx/timer/timer.c
     432mpc55xx_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
     433mpc55xx_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     434
    428435# FEC
    429436noinst_PROGRAMS += mpc55xx/fec.rel
     
    440447mpc55xx_emios_rel_SOURCES = mpc55xx/emios/emios.c
    441448mpc55xx_emios_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     449
     450# SIU
     451noinst_PROGRAMS += mpc55xx/siu.rel
     452mpc55xx_siu_rel_SOURCES = mpc55xx/siu/siu.c
     453mpc55xx_siu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    442454
    443455# eSCI
  • c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c

    r2f5435a4 r1f4db180  
    11/*  timer.c
    22 *
    3  *  This file implements a benchmark timer using the General Purpose Timer.
     3 *  This file implements a benchmark timer using the PPC Timebase
    44 *
    55 *  Notes: NONE
  • c/src/lib/libcpu/powerpc/preinstall.am

    r2f5435a4 r1f4db180  
    275275PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/esci.h
    276276
     277$(PROJECT_INCLUDE)/mpc55xx/siu.h: mpc55xx/include/siu.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
     278        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/siu.h
     279PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/siu.h
     280
    277281$(PROJECT_INCLUDE)/mpc55xx/watchdog.h: mpc55xx/include/watchdog.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
    278282        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/watchdog.h
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