Index: c/src/lib/libcpu/arm/mc9328mxl/ChangeLog
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/ChangeLog	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/ChangeLog	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,7 @@
+2004-07-15	Jay Monkman
+
+	* ChangeLog, Makefile.am, clock/.cvsignore, clock/clockdrv.c,
+	include/mc9328mxl.h, irq/.cvsignore, irq/bsp_irq_asm.S,
+	irq/bsp_irq_init.c, irq/irq.c, irq/irq.h, timer/.cvsignore,
+	timer/timer.c: New files.
+
Index: c/src/lib/libcpu/arm/mc9328mxl/Makefile.am
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/Makefile.am	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/Makefile.am	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,104 @@
+##
+## $Id$
+##
+
+CLEANFILES =
+EXTRA_DIST =
+EXTRA_PROGRAMS =
+noinst_DATA =
+
+include $(top_srcdir)/../../../automake/compile.am
+
+if mc9328mxl
+include_mc9328mxldir = $(includedir)/mc9328mxl
+include_libcpudir = $(includedir)/libcpu
+include_HEADERS = include/mc9328mxl.h 
+
+## clock
+EXTRA_PROGRAMS += clock.rel
+CLEANFILES += clock.rel
+clock_rel_SOURCES = clock/clockdrv.c
+clock_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += clock_g.rel
+CLEANFILES += clock_g.rel
+clock_g_rel_SOURCES = $(clock_rel_SOURCES)
+clock_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+clock_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += clock$(LIB_VARIANT).rel
+
+## timer
+EXTRA_PROGRAMS += timer.rel
+CLEANFILES += timer.rel
+timer_rel_SOURCES = timer/timer.c
+timer_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += timer_g.rel
+CLEANFILES += timer_g.rel
+timer_g_rel_SOURCES = $(timer_rel_SOURCES)
+timer_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+timer_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += timer$(LIB_VARIANT).rel
+
+## interrupt
+include_HEADERS += irq/irq.h
+
+EXTRA_PROGRAMS += irq.rel
+CLEANFILES += irq.rel
+irq_rel_SOURCES = irq/irq.c irq/bsp_irq_init.c \
+    ../../../libbsp/arm/shared/irq/irq_init.c irq/bsp_irq_asm.S \
+    ../../../libbsp/arm/shared/irq/irq_asm.S irq/irq.h
+irq_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += irq_g.rel
+CLEANFILES += irq_g.rel
+irq_g_rel_SOURCES = $(irq_rel_SOURCES)
+irq_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+irq_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += irq$(LIB_VARIANT).rel
+
+
+endif
+
+## --
+all-local: $(PREINSTALL_FILES)
+
+PREINSTALL_DIRS =
+PREINSTALL_FILES =
+
+$(PROJECT_INCLUDE)/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)
+	@: > $(PROJECT_INCLUDE)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
+
+if mc9328mxl
+$(PROJECT_INCLUDE)/mc9328mxl/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)/mc9328mxl
+	@: > $(PROJECT_INCLUDE)/mc9328mxl/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/mc9328mxl/$(dirstamp)
+
+$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)/libcpu
+	@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+
+$(PROJECT_INCLUDE)/mc9328mxl.h: include/mc9328mxl.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mc9328mxl.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/mc9328mxl.h
+
+$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
+
+endif
+
+CLEANFILES += $(PREINSTALL_FILES)
+DISTCLEANFILES = $(PREINSTALL_DIRS)
+
+include $(top_srcdir)/../../../automake/local.am
Index: c/src/lib/libcpu/arm/mc9328mxl/clock/.cvsignore
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/clock/.cvsignore	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/clock/.cvsignore	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,14 @@
+Makefile
+Makefile.in
+aclocal.m4
+autom4te.cache
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
Index: c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,145 @@
+/*
+ *  MC9328MXL clock specific using the System Timer
+ *
+ *  This is hardware specific part of the clock driver. At the end of this
+ *  file, the generic part of the driver is #included.
+ *
+ *  Copyright (c) 2004 by Cogent Computer Systems
+ *  Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ *  clockdrv.c,v 1.1 2002/11/13 17:55:04 joel Exp
+*/
+#include <rtems.h>
+#include <bsp.h>
+#include <irq.h>
+#include <mc9328mxl.h>
+
+/* this is defined in ../../../shared/clockdrv_shell.c */
+rtems_isr Clock_isr(rtems_vector_number vector);
+static void clock_isr_on(const rtems_irq_connect_data *unused);
+static void clock_isr_off(const rtems_irq_connect_data *unused);
+static int clock_isr_is_on(const rtems_irq_connect_data *irq);
+
+/* Replace the first value with the clock's interrupt name. */
+rtems_irq_connect_data clock_isr_data = {BSP_INT_TIMER1,
+                                         (rtems_irq_hdl)Clock_isr,
+                                         clock_isr_on,
+                                         clock_isr_off,
+                                         clock_isr_is_on,
+                                         3,     /* unused for ARM cpus */
+                                         0 };   /* unused for ARM cpus */
+
+/* If you follow the code, this is never used, so any value 
+ * should work
+ */
+#define CLOCK_VECTOR 0
+
+    
+/**
+ * When we get the clock interrupt
+ *    - clear the interrupt bit?
+ *    - restart the timer?
+ */
+#define Clock_driver_support_at_tick()                \
+  do {                                                \
+        uint32_t reg;                                 \
+        reg = MC9328MXL_TMR1_TSTAT;                   \
+        MC9328MXL_TMR1_TSTAT = 0;                     \
+  } while(0)
+
+
+/**
+ * Installs the clock ISR. You shouldn't need to change this.
+ */
+#define Clock_driver_support_install_isr( _new, _old )                      \
+  do {                                                                      \
+      BSP_install_rtems_irq_handler(&clock_isr_data);                       \
+     } while(0)
+
+
+/**
+ * Initialize the hardware for the clock
+ *   - Set the frequency
+ *   - enable it
+ *   - clear any pending interrupts
+ *
+ * Since you may want the clock always running, you can 
+ * enable interrupts here. If you do so, the clock_isr_on(),
+ * clock_isr_off(), and clock_isr_is_on() functions can be 
+ * NOPs.
+ */
+#define Clock_driver_support_initialize_hardware() \
+  do { \
+        int freq; \
+        int cnt; \
+        freq = get_perclk1_freq(); \
+        printk("perclk1 freq is %d\n", freq); \
+        cnt = ((freq / 1000) * BSP_Configuration.microseconds_per_tick) / 1000;\
+        printk("cnt freq is %d\n", cnt); \
+        MC9328MXL_TMR1_TCMP = cnt; \
+        /* use PERCLK1 as input, enable timer */ \
+        MC9328MXL_TMR1_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 | \
+                               MC9328MXL_TMR_TCTL_TEN | \
+                               MC9328MXL_TMR_TCTL_IRQEN); \
+        /* set prescaler to 1 (register value + 1) */ \
+        MC9328MXL_TMR1_TPRER = 0; \
+     } while (0)
+
+/**
+ * Do whatever you need to shut the clock down and remove the 
+ * interrupt handler. Since this normally only gets called on
+ * RTEMS shutdown, you may not need to do anything other than
+ * remove the ISR.
+ */
+#define Clock_driver_support_shutdown_hardware()                        \
+  do {                                                                  \
+        /* Disable timer */ \
+        MC9328MXL_TMR1_TCTL = 0; \
+	BSP_remove_rtems_irq_handler(&clock_isr_data);                  \
+     } while (0)
+
+/**
+ * Enables clock interrupt.
+ *
+ * If the interrupt is always on, this can be a NOP.
+ */
+static void clock_isr_on(const rtems_irq_connect_data *unused)
+{
+    MC9328MXL_TMR1_TCTL |= MC9328MXL_TMR_TCTL_IRQEN;
+    MC9328MXL_AITC_INTENNUM = MC9328MXL_INT_TIMER1;
+
+    return;
+}
+
+/**
+ * Disables clock interrupts
+ *
+ * If the interrupt is always on, this can be a NOP.
+ */
+static void clock_isr_off(const rtems_irq_connect_data *unused)
+{
+    MC9328MXL_TMR1_TCTL &= ~MC9328MXL_TMR_TCTL_IRQEN;
+    MC9328MXL_AITC_INTDISNUM = MC9328MXL_INT_TIMER1;
+    return;
+}
+
+/**
+ * Tests to see if clock interrupt is enabled, and returns 1 if so.
+ * If interrupt is not enabled, returns 0.
+ *
+ * If the interrupt is always on, this always returns 1.
+ */
+static int clock_isr_is_on(const rtems_irq_connect_data *irq)
+{
+    return MC9328MXL_TMR1_TCTL & MC9328MXL_TMR_TCTL_IRQEN;
+}
+
+
+/* Make sure to include this, and only at the end of the file */
+#include "../../../../libbsp/shared/clockdrv_shell.c"
Index: c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,451 @@
+/*
+ * Motorola MC9328MXL Register definitions
+ *
+ * Copyright (c) 2003 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *	
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#ifndef __MC9328MXL_H__
+#define __MC9328MXL_H__
+
+#include <rtems/stdint.h>
+
+#define bit(_x_) (1 << (_x_))
+
+/* Define some constants relating to the CPU */
+#define MC9328MXL_NUM_INTS  64        /* CPU supports 64 interrupts */
+
+/* Define the base addresses of the internal registers */
+#define MC9328MXL_AIPI1_BASE    0x00200000
+#define MC9328MXL_AIPI2_BASE    0x00210000
+#define MC9328MXL_WDOG_BASE     0x00201000
+#define MC9328MXL_TMR1_BASE     0x00202000
+#define MC9328MXL_TMR2_BASE     0x00203000
+#define MC9328MXL_RTC_BASE      0x00204000
+#define MC9328MXL_LCDC_BASE     0x00205000
+#define MC9328MXL_UART1_BASE    0x00206000
+#define MC9328MXL_UART2_BASE    0x00207000
+#define MC9328MXL_PWM_BASE      0x00208000
+#define MC9328MXL_DMAC_BASE     0x00209000
+#define MC9328MXL_USBD_BASE     0x00212000
+#define MC9328MXL_SPI1_BASE     0x00213000
+#define MC9328MXL_SPI2_BASE     0x00219000
+#define MC9328MXL_MMC_BASE      0x00214000
+#define MC9328MXL_I2C_BASE      0x00217000
+#define MC9328MXL_SSI_BASE      0x00218000
+#define MC9328MXL_MSHC_BASE     0x0021a000
+#define MC9328MXL_PLL_BASE      0x0021b000
+#define MC9328MXL_RESET_BASE    0x0021b800
+#define MC9328MXL_SYSCTRL_BASE  0x0021b804
+#define MC9328MXL_GPIOA_BASE    0x0021c000
+#define MC9328MXL_GPIOB_BASE    0x0021c100
+#define MC9328MXL_GPIOC_BASE    0x0021c200
+#define MC9328MXL_GPIOD_BASE    0x0021c300
+#define MC9328MXL_EIM_BASE      0x00220000
+#define MC9328MXL_SDRAM_BASE    0x00221000
+#define MC9328MXL_MMA_BASE      0x00222000
+#define MC9328MXL_AITC_BASE     0x00223000
+#define MC9328MXL_CSI_BASE      0x00224000
+
+
+#define MC9328MXL_TMR1_TCTL   (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x00)))
+#define MC9328MXL_TMR1_TPRER  (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x04)))
+#define MC9328MXL_TMR1_TCMP   (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x08)))
+#define MC9328MXL_TMR1_TCR    (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x0c)))
+#define MC9328MXL_TMR1_TCN    (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x10)))
+#define MC9328MXL_TMR1_TSTAT  (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x14)))
+
+#define MC9328MXL_TMR2_TCTL   (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x00)))
+#define MC9328MXL_TMR2_TPRER  (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x04)))
+#define MC9328MXL_TMR2_TCMP   (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x08)))
+#define MC9328MXL_TMR2_TCR    (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x0c)))
+#define MC9328MXL_TMR2_TCN    (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x10)))
+#define MC9328MXL_TMR2_TSTAT  (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x14)))
+
+#define MC9328MXL_TMR_TCTL_SWR                (bit(15))
+#define MC9328MXL_TMR_TCTL_FRR                (bit(8))
+#define MC9328MXL_TMR_TCTL_CAP_DIS            (0 << 6)
+#define MC9328MXL_TMR_TCTL_CAP_RISE           (1 << 6)
+#define MC9328MXL_TMR_TCTL_CAP_FALL           (2 << 6)
+#define MC9328MXL_TMR_TCTL_CAP_ANY            (3 << 6)
+#define MC9328MXL_TMR_TCTL_OM                 (bit(5))
+#define MC9328MXL_TMR_TCTL_IRQEN              (bit(4))               
+#define MC9328MXL_TMR_TCTL_CLKSRC_STOP        (0 << 1)
+#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1       (1 << 1)
+#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16  (2 << 1)
+#define MC9328MXL_TMR_TCTL_CLKSRC_TIN         (3 << 1)
+#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX       (4 << 1) 
+#define MC9328MXL_TMR_TCTL_TEN                (bit(0))
+
+#define MC9328MXL_UART1_RXD   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x00)))
+#define MC9328MXL_UART1_TXD   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x40)))
+#define MC9328MXL_UART1_CR1   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x80)))
+#define MC9328MXL_UART1_CR2   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x84)))
+#define MC9328MXL_UART1_CR3   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x88)))
+#define MC9328MXL_UART1_CR4   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x8c)))
+#define MC9328MXL_UART1_FCR   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x90)))
+#define MC9328MXL_UART1_SR1   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x94)))
+#define MC9328MXL_UART1_SR2   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x98)))
+#define MC9328MXL_UART1_ESC   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x9c)))
+#define MC9328MXL_UART1_TIM   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa0)))
+#define MC9328MXL_UART1_BIR   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa4)))
+#define MC9328MXL_UART1_BMR   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa8)))
+#define MC9328MXL_UART1_BRC   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xac)))
+#define MC9328MXL_UART1_IPR1  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb0)))
+#define MC9328MXL_UART1_IPR2  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb4)))
+#define MC9328MXL_UART1_IPR3  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb8)))
+#define MC9328MXL_UART1_IPR4  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xbc)))
+#define MC9328MXL_UART1_MPR1  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc0)))
+#define MC9328MXL_UART1_MPR2  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc4)))
+#define MC9328MXL_UART1_MPR3  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc8)))
+#define MC9328MXL_UART1_MPR4  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xcc)))
+#define MC9328MXL_UART1_TS    (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xd0)))
+
+#define MC9328MXL_UART2_RXD   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x00)))
+#define MC9328MXL_UART2_TXD   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x40)))
+#define MC9328MXL_UART2_CR1   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x80)))
+#define MC9328MXL_UART2_CR2   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x84)))
+#define MC9328MXL_UART2_CR3   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x88)))
+#define MC9328MXL_UART2_CR4   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x8c)))
+#define MC9328MXL_UART2_FCR   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x90)))
+#define MC9328MXL_UART2_SR1   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x94)))
+#define MC9328MXL_UART2_SR2   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x98)))
+#define MC9328MXL_UART2_ESC   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x9c)))
+#define MC9328MXL_UART2_TIM   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa0)))
+#define MC9328MXL_UART2_BIR   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa4)))
+#define MC9328MXL_UART2_BMR   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa8)))
+#define MC9328MXL_UART2_BRC   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xac)))
+#define MC9328MXL_UART2_IPR1  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb0)))
+#define MC9328MXL_UART2_IPR2  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb4)))
+#define MC9328MXL_UART2_IPR3  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb8)))
+#define MC9328MXL_UART2_IPR4  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xbc)))
+#define MC9328MXL_UART2_MPR1  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc0)))
+#define MC9328MXL_UART2_MPR2  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc4)))
+#define MC9328MXL_UART2_MPR3  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc8)))
+#define MC9328MXL_UART2_MPR4  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xcc)))
+#define MC9328MXL_UART2_TS    (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xd0)))
+
+
+#define MC9328MXL_UART_RXD_CHARRDY    (bit(15))
+#define MC9328MXL_UART_RXD_ERR        (bit(14))
+#define MC9328MXL_UART_RXD_OVRRUN     (bit(13))
+#define MC9328MXL_UART_RXD_FRMERR     (bit(12))
+#define MC9328MXL_UART_RXD_BRK        (bit(11))
+#define MC9328MXL_UART_RXD_PRERR      (bit(10))
+#define MC9328MXL_UART_RXD_CHARMASK   (0xff)
+
+#define MC9328MXL_UART_CR1_ADEN       (bit(15))
+#define MC9328MXL_UART_CR1_ADBR       (bit(14))
+#define MC9328MXL_UART_CR1_TRDYEN     (bit(13))
+#define MC9328MXL_UART_CR1_IDEN       (bit(12))
+#define MC9328MXL_UART_CR1_ICD4       (0x0 << 10)
+#define MC9328MXL_UART_CR1_ICD8       (0x1 << 10)
+#define MC9328MXL_UART_CR1_ICD16      (0x2 << 10)
+#define MC9328MXL_UART_CR1_ICD32      (0x3 << 10)
+#define MC9328MXL_UART_CR1_RRDYEN     (bit(9))
+#define MC9328MXL_UART_CR1_RDMAEN     (bit(8))
+#define MC9328MXL_UART_CR1_IREN       (bit(7))
+#define MC9328MXL_UART_CR1_TXMPTYEN   (bit(6))
+#define MC9328MXL_UART_CR1_RTSDEN     (bit(5))
+#define MC9328MXL_UART_CR1_SNDBRK     (bit(4))
+#define MC9328MXL_UART_CR1_TDMAEN     (bit(3))
+#define MC9328MXL_UART_CR1_UARTCLKEN  (bit(2))
+#define MC9328MXL_UART_CR1_DOZE       (bit(1))
+#define MC9328MXL_UART_CR1_UARTEN     (bit(0))
+
+
+#define MC9328MXL_UART_CR2_ESCI       (bit(15))
+#define MC9328MXL_UART_CR2_IRTS       (bit(14))
+#define MC9328MXL_UART_CR2_CTSC       (bit(13))
+#define MC9328MXL_UART_CR2_CTS        (bit(12))
+#define MC9328MXL_UART_CR2_ESCEN      (bit(11))
+#define MC9328MXL_UART_CR2_RTEC_RE    (0 << 9)
+#define MC9328MXL_UART_CR2_RTEC_FE    (1 << 9)
+#define MC9328MXL_UART_CR2_RTEC_ANY   (2 << 9)
+#define MC9328MXL_UART_CR2_PREN       (bit(8))
+#define MC9328MXL_UART_CR2_PROE       (bit(7))
+#define MC9328MXL_UART_CR2_STPB       (bit(6))
+#define MC9328MXL_UART_CR2_WS         (bit(5))
+#define MC9328MXL_UART_CR2_RTSEN      (bit(4))
+#define MC9328MXL_UART_CR2_TXEN       (bit(2))
+#define MC9328MXL_UART_CR2_RXEN       (bit(1))
+#define MC9328MXL_UART_CR2_SRST       (bit(0))
+
+#define MC9328MXL_UART_CR3_DPEC_RE    (0 << 14)  /* UART2 only */
+#define MC9328MXL_UART_CR3_DPEC_FE    (1 << 14)  /* UART2 only */
+#define MC9328MXL_UART_CR3_DPEC_ANY   (2 << 14)  /* UART2 only */
+#define MC9328MXL_UART_CR3_DTREN      (bit(13))  /* UART2 only */
+#define MC9328MXL_UART_CR3_PARERREN   (bit(12))
+#define MC9328MXL_UART_CR3_FRAERREN   (bit(11))
+#define MC9328MXL_UART_CR3_DSR        (bit(10))  /* UART2 only */
+#define MC9328MXL_UART_CR3_DCD        (bit(9))   /* UART2 only */
+#define MC9328MXL_UART_CR3_RI         (bit(8))   /* UART2 only */
+#define MC9328MXL_UART_CR3_RXDSEN     (bit(6))
+#define MC9328MXL_UART_CR3_AIRINTEN   (bit(5))
+#define MC9328MXL_UART_CR3_AWAKEN     (bit(4))
+#define MC9328MXL_UART_CR3_REF25      (bit(3))
+#define MC9328MXL_UART_CR3_REF30      (bit(2))
+#define MC9328MXL_UART_CR3_INVT       (bit(1))
+#define MC9328MXL_UART_CR3_BPEN       (bit(0))
+
+#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)      
+#define MC9328MXL_UART_CR4_INVR       (bit(9))
+#define MC9328MXL_UART_CR4_ENIRI      (bit(8))
+#define MC9328MXL_UART_CR4_WKEN       (bit(7))
+#define MC9328MXL_UART_CR4_REF16      (bit(6))
+#define MC9328MXL_UART_CR4_IRSC       (bit(5))
+#define MC9328MXL_UART_CR4_TCEN       (bit(3))
+#define MC9328MXL_UART_CR4_BKEN       (bit(2))
+#define MC9328MXL_UART_CR4_OREN       (bit(1))
+#define MC9328MXL_UART_CR4_DREN       (bit(0))
+
+#define MC9328MXL_UART_SR1_PARERR     (bit(15))
+#define MC9328MXL_UART_SR1_RTSS       (bit(14))
+#define MC9328MXL_UART_SR1_TRDY       (bit(13))
+#define MC9328MXL_UART_SR1_RTSD       (bit(12))
+#define MC9328MXL_UART_SR1_ESCF       (bit(11))
+#define MC9328MXL_UART_SR1_FRMERR     (bit(10))
+#define MC9328MXL_UART_SR1_RRDY       (bit(9))
+#define MC9328MXL_UART_SR1_RXDS       (bit(6))
+#define MC9328MXL_UART_SR1_AIRINT     (bit(5))
+#define MC9328MXL_UART_SR1_AWAKE      (bit(4))
+
+#define MC9328MXL_UART_SR2_ADET       (bit(15))
+#define MC9328MXL_UART_SR2_TXFE       (bit(14))
+#define MC9328MXL_UART_SR2_DTRF       (bit(13))
+#define MC9328MXL_UART_SR2_IDLE       (bit(12))
+#define MC9328MXL_UART_SR2_IRINT      (bit(8))
+#define MC9328MXL_UART_SR2_WAKE       (bit(7))
+#define MC9328MXL_UART_SR2_RTSF       (bit(4))
+#define MC9328MXL_UART_SR2_TXDC       (bit(3))
+#define MC9328MXL_UART_SR2_BRCD       (bit(2))
+#define MC9328MXL_UART_SR2_ORE        (bit(1))
+#define MC9328MXL_UART_SR2_RDR        (bit(0))
+
+
+#define MC9328MXL_PLL_CSCR   (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x00)))
+#define MC9328MXL_PLL_MPCTL0 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x04)))
+#define MC9328MXL_PLL_MPCTL1 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x08)))
+#define MC9328MXL_PLL_SPCTL0 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x0c)))
+#define MC9328MXL_PLL_SPCTL1 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x10)))
+#define MC9328MXL_PLL_PCDR   (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x20)))
+
+#define MC9328MXL_PLL_CSCR_CLKOSEL_PERCLK1 (0 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_HCLK    (1 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_CLK48M  (2 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_CLK16M  (3 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_PREMCLK (4 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_FCLK    (5 << 29)
+
+#define MC9328MXL_PLL_CSCR_USBDIV(_x_)     (((_x_) & 0x7) << 26)
+#define MC9328MXL_PLL_CSCR_SDCNT_1         (0 << 24)
+#define MC9328MXL_PLL_CSCR_SDCNT_2         (1 << 24)
+#define MC9328MXL_PLL_CSCR_SDCNT_3         (2 << 24)
+#define MC9328MXL_PLL_CSCR_SDCNT_4         (3 << 24)
+
+#define MC9328MXL_PLL_CSCR_SPLLRSTRT       (bit(22))
+#define MC9328MXL_PLL_CSCR_MPLLRSTRT       (bit(21))
+#define MC9328MXL_PLL_CSCR_CLK16SEL        (bit(18))
+#define MC9328MXL_PLL_CSCR_OSCEN           (bit(17))
+#define MC9328MXL_PLL_CSCR_SYSSEL          (bit(16))
+#define MC9328MXL_PLL_CSCR_PRESC           (bit(15))
+#define MC9328MXL_PLL_CSCR_BLKDIV(_x_)     (((_x_) & 0xf) << 10)
+#define MC9328MXL_PLL_CSCR_SPEN            (bit(1))
+#define MC9328MXL_PLL_CSCR_MPEN            (bit(0))
+
+#define MC9328MXL_PLL_PCDR_PCLK1_MASK      (0x0000000f)
+#define MC9328MXL_PLL_PCDR_PCLK1_SHIFT     (0)
+#define MC9328MXL_PLL_PCDR_PCLK2_MASK      (0x000000f0)
+#define MC9328MXL_PLL_PCDR_PCLK2_SHIFT     (4)
+#define MC9328MXL_PLL_PCDR_PCLK3_MASK      (0x007f0000)
+#define MC9328MXL_PLL_PCDR_PCLK3_SHIFT     (16)
+
+
+#define MC9328MXL_PLL_SPCTL_PD_MASK        (0x3c000000)
+#define MC9328MXL_PLL_SPCTL_PD_SHIFT       (26)
+#define MC9328MXL_PLL_SPCTL_MFD_MASK       (0x03ff0000)
+#define MC9328MXL_PLL_SPCTL_MFD_SHIFT      (16)
+#define MC9328MXL_PLL_SPCTL_MFI_MASK       (0x00003c00)
+#define MC9328MXL_PLL_SPCTL_MFI_SHIFT      (10)
+#define MC9328MXL_PLL_SPCTL_MFN_MASK       (0x000003ff)
+#define MC9328MXL_PLL_SPCTL_MFN_SHIFT      (0)
+    
+
+#define MC9328MXL_GPIOA_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00)))
+#define MC9328MXL_GPIOA_OCR1    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x04)))
+#define MC9328MXL_GPIOA_OCR2    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x08)))
+#define MC9328MXL_GPIOA_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x0c)))
+#define MC9328MXL_GPIOA_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x10)))
+#define MC9328MXL_GPIOA_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x14)))
+#define MC9328MXL_GPIOA_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x18)))
+#define MC9328MXL_GPIOA_DR      (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x1c)))
+#define MC9328MXL_GPIOA_GIUS    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x20)))
+#define MC9328MXL_GPIOA_SSR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x24)))
+#define MC9328MXL_GPIOA_ICR1    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x28)))
+#define MC9328MXL_GPIOA_ICR2    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x2c)))
+#define MC9328MXL_GPIOA_IMR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x30)))
+#define MC9328MXL_GPIOA_ISR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x34)))
+#define MC9328MXL_GPIOA_GPR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x38)))
+#define MC9328MXL_GPIOA_SWR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x3c)))
+#define MC9328MXL_GPIOA_PUEN    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x40)))
+
+#define MC9328MXL_GPIOB_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x00)))
+#define MC9328MXL_GPIOB_OCR1    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x04)))
+#define MC9328MXL_GPIOB_OCR2    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x08)))
+#define MC9328MXL_GPIOB_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x0c)))
+#define MC9328MXL_GPIOB_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x10)))
+#define MC9328MXL_GPIOB_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x14)))
+#define MC9328MXL_GPIOB_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x18)))
+#define MC9328MXL_GPIOB_DR      (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x1c)))
+#define MC9328MXL_GPIOB_GIUS    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x20)))
+#define MC9328MXL_GPIOB_SSR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x24)))
+#define MC9328MXL_GPIOB_ICR1    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x28)))
+#define MC9328MXL_GPIOB_ICR2    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x2c)))
+#define MC9328MXL_GPIOB_IMR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x30)))
+#define MC9328MXL_GPIOB_ISR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x34)))
+#define MC9328MXL_GPIOB_GPR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x38)))
+#define MC9328MXL_GPIOB_SWR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x3c)))
+#define MC9328MXL_GPIOB_PUEN    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x40)))
+
+#define MC9328MXL_GPIOC_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x00)))
+#define MC9328MXL_GPIOC_OCR1    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x04)))
+#define MC9328MXL_GPIOC_OCR2    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x08)))
+#define MC9328MXL_GPIOC_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x0c)))
+#define MC9328MXL_GPIOC_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x10)))
+#define MC9328MXL_GPIOC_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x14)))
+#define MC9328MXL_GPIOC_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x18)))
+#define MC9328MXL_GPIOC_DR      (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x1c)))
+#define MC9328MXL_GPIOC_GIUS    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x20)))
+#define MC9328MXL_GPIOC_SSR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x24)))
+#define MC9328MXL_GPIOC_ICR1    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x28)))
+#define MC9328MXL_GPIOC_ICR2    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x2c)))
+#define MC9328MXL_GPIOC_IMR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x30)))
+#define MC9328MXL_GPIOC_ISR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x34)))
+#define MC9328MXL_GPIOC_GPR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x38)))
+#define MC9328MXL_GPIOC_SWR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x3c)))
+#define MC9328MXL_GPIOC_PUEN    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x40)))
+
+#define MC9328MXL_GPIOD_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x00)))
+#define MC9328MXL_GPIOD_OCR1    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x04)))
+#define MC9328MXL_GPIOD_OCR2    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x08)))
+#define MC9328MXL_GPIOD_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x0c)))
+#define MC9328MXL_GPIOD_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x10)))
+#define MC9328MXL_GPIOD_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x14)))
+#define MC9328MXL_GPIOD_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x18)))
+#define MC9328MXL_GPIOD_DR      (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x1c)))
+#define MC9328MXL_GPIOD_GIUS    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x20)))
+#define MC9328MXL_GPIOD_SSR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x24)))
+#define MC9328MXL_GPIOD_ICR1    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x28)))
+#define MC9328MXL_GPIOD_ICR2    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x2c)))
+#define MC9328MXL_GPIOD_IMR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x30)))
+#define MC9328MXL_GPIOD_ISR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x34)))
+#define MC9328MXL_GPIOD_GPR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x38)))
+#define MC9328MXL_GPIOD_SWR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x3c)))
+#define MC9328MXL_GPIOD_PUEN    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x40)))
+
+#define MC9328MXL_AITC_INTCNTL    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE) + 0x00)))
+#define MC9328MXL_AITC_NIMASK     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE) + 0x04)))
+#define MC9328MXL_AITC_INTENNUM   (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x08)))
+#define MC9328MXL_AITC_INTDISNUM  (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x0c)))
+#define MC9328MXL_AITC_INTENABLEH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x10)))
+#define MC9328MXL_AITC_INTENABLEL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x14)))
+#define MC9328MXL_AITC_INTTYPEH   (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x18)))
+#define MC9328MXL_AITC_INTTYPEL   (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x1c)))
+#define MC9328MXL_AITC_NIPIR7     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x20)))
+#define MC9328MXL_AITC_NIPRI6     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x24)))
+#define MC9328MXL_AITC_NIPRI5     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x28)))
+#define MC9328MXL_AITC_NIPRI4     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x2c)))
+#define MC9328MXL_AITC_NIPRI3     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x30)))
+#define MC9328MXL_AITC_NIPRI2     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x34)))
+#define MC9328MXL_AITC_NIPRI1     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x38)))
+#define MC9328MXL_AITC_NIPRI0     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x3c)))
+#define MC9328MXL_AITC_NIVECSR    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x40)))
+#define MC9328MXL_AITC_FIVECSR    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x44)))
+#define MC9328MXL_AITC_INTSRCH    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x48)))
+#define MC9328MXL_AITC_INTSRCL    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x4c)))
+#define MC9328MXL_AITC_INTFRCH    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x50)))
+#define MC9328MXL_AITC_INTFRCL    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x54)))
+#define MC9328MXL_AITC_NIPNDH     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x58)))
+#define MC9328MXL_AITC_NIPNDL     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x5c)))
+#define MC9328MXL_AITC_FIPNDH     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x60)))
+#define MC9328MXL_AITC_FIPNDL     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x64)))
+
+#define MC9328MXL_INT_UART3_PFERR          (0)
+#define MC9328MXL_INT_UART3_RTS            (1)
+#define MC9328MXL_INT_UART3_DTR            (2)
+#define MC9328MXL_INT_UART3_UARTC          (3)
+#define MC9328MXL_INT_UART3_TX             (4)
+#define MC9328MXL_INT_PEN_UP               (5)
+#define MC9328MXL_INT_CSI                  (6)
+#define MC9328MXL_INT_MMA_MAC              (7)
+#define MC9328MXL_INT_MMA                  (8)
+#define MC9328MXL_INT_COMP                 (9)
+#define MC9328MXL_INT_MSIRQ                (10)
+#define MC9328MXL_INT_GPIO_PORTA           (11)
+#define MC9328MXL_INT_GPIO_PORTB           (12)
+#define MC9328MXL_INT_GPIO_PORTC           (13)
+#define MC9328MXL_INT_LCDC                 (14)
+#define MC9328MXL_INT_SIM_IRQ              (15)
+#define MC9328MXL_INT_SIM_DATA             (16)
+#define MC9328MXL_INT_RTC                  (17)
+#define MC9328MXL_INT_RTC_SAM              (18)
+#define MC9328MXL_INT_UART2_PFERR          (19)
+#define MC9328MXL_INT_UART2_RTS            (20)
+#define MC9328MXL_INT_UART2_DTR            (21)
+#define MC9328MXL_INT_UART2_UARTC          (22)
+#define MC9328MXL_INT_UART2_TX             (23)
+#define MC9328MXL_INT_UART2_RX             (24)
+#define MC9328MXL_INT_UART1_PFERR          (25)
+#define MC9328MXL_INT_UART1_RTS            (26)
+#define MC9328MXL_INT_UART1_DTR            (27)
+#define MC9328MXL_INT_UART1_UARTC          (28)
+#define MC9328MXL_INT_UART1_TX             (29)
+#define MC9328MXL_INT_UART1_RX             (30)
+#define MC9328MXL_INT_PEN_DATA             (33)
+#define MC9328MXL_INT_PWM                  (34)
+#define MC9328MXL_INT_MMC_IRQ              (35)
+#define MC9328MXL_INT_SSI2_TX              (36)
+#define MC9328MXL_INT_SSI2_RX              (37)
+#define MC9328MXL_INT_SSI2_ERR             (38)
+#define MC9328MXL_INT_I2C                  (39)
+#define MC9328MXL_INT_SPI2                 (40)
+#define MC9328MXL_INT_SPI1                 (41)
+#define MC9328MXL_INT_SSI_TX               (42)
+#define MC9328MXL_INT_SSI_TX_ERR           (43)
+#define MC9328MXL_INT_SSI_RX               (44)
+#define MC9328MXL_INT_SSI_RX_ERR           (45)
+#define MC9328MXL_INT_TOUCH                (46)
+#define MC9328MXL_INT_USBD0                (47)
+#define MC9328MXL_INT_USBD1                (48)
+#define MC9328MXL_INT_USBD2                (49)
+#define MC9328MXL_INT_USBD3                (50)
+#define MC9328MXL_INT_USBD4                (51)
+#define MC9328MXL_INT_USBD5                (52)
+#define MC9328MXL_INT_USBD6                (53)
+#define MC9328MXL_INT_UART3_RX             (54)
+#define MC9328MXL_INT_BTSYS                (55)
+#define MC9328MXL_INT_BTTIM                (56)
+#define MC9328MXL_INT_BTWUI                (57)
+#define MC9328MXL_INT_TIMER2               (58)
+#define MC9328MXL_INT_TIMER1               (59)
+#define MC9328MXL_INT_DMA_ERR              (60)
+#define MC9328MXL_INT_DMA                  (61)
+#define MC9328MXL_INT_GPIO_PORTD           (62)
+#define MC9328MXL_INT_WDT                  (63)
+
+#define MC9328MXL_AITC_INTCTL_NIAD    BIT(20)
+#define MC9328MXL_AITC_INTCTL_FIAD    BIT(19)
+#define MC9328MXL_AITC_NIMASK_MASK (0X1F)
+#define MC9328MXL_AITC_INTENNUM_MASK  (0X3F)
+#define MC9328MXL_AITC_INTDISNUM_MASK (0X3F)
+#define MC9328MXL_AITC_NIPRIORITY(_int_, _pri_) \
+           (((_pri_) & 0xf) << ((_int_) & 0x7) * 4)
+
+
+#endif /* __MC9328MXL_H__ */
Index: c/src/lib/libcpu/arm/mc9328mxl/irq/.cvsignore
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/irq/.cvsignore	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/irq/.cvsignore	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,14 @@
+Makefile
+Makefile.in
+aclocal.m4
+autom4te.cache
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
Index: c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,45 @@
+/*
+ * MC9328MXL Intererrupt handler
+ *
+ * Copyright (c) 2002 by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ *  bsp_irq_asm.S,v 1.1 2002/11/13 17:55:06 joel Exp
+ */
+#define __asm__
+	
+/* 
+ * BSP specific interrupt handler for INT or FIQ. In here
+ * you do determine which interrupt happened and call its
+ * handler.
+ */
+	.globl ExecuteITHandler
+ExecuteITHandler :
+/*
+ * Look at interrupt status register to determine source.
+ * From source, determine offset into expanded vector table
+ * and load handler address into r0.
+ */
+  ldr 	r0, =0x00223040  /* Read the vector number */
+  ldr	r1, [r0]
+  mov   r1, r1, LSR #16         /* get the NIVECTOR into 16 LSbits */
+
+  /* find the ISR's address based on the vector */	
+  ldr   r0, =bsp_vector_table
+  ldr	r0, [r0, r1, LSL #2]	/* Read the address */
+
+
+  stmdb	  sp!,{lr}
+  ldr     lr, =IRQ_return         /* prepare the return from handler  */
+
+  mov     pc, r0		/* EXECUTE INT HANDLER */
+
+IRQ_return:
+  ldmia sp!,{lr}
+
+  mov pc, lr
Index: c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,32 @@
+/*
+ * Motorola MC9328MXL Interrupt handler
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ *  $Id$
+ */
+#include <irq.h>
+#include <bsp.h>
+#include <mc9328mxl.h>
+
+extern void default_int_handler();
+
+/* 
+ * Interrupt system initialization. Disable interrupts, clear 
+ * any that are pending.
+ */
+void BSP_rtems_irq_mngt_init()
+{
+#if 0
+    /* disable all interrupts */
+    AIC_CTL_REG(AIC_IDCR) = 0xffffffff;
+#endif
+
+}
+
Index: c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,117 @@
+/*
+ * Motorola MC9328MXL Interrupt handler
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#include <bsp.h>
+#include <irq.h>
+#include <rtems/score/thread.h>
+#include <rtems/score/apiext.h>
+#include <mc9328mxl.h>
+
+/*
+ * This function check that the value given for the irq line
+ * is valid.
+ */
+static int isValidInterrupt(int irq)
+{
+  if ( (irq < 0) || (irq >= BSP_MAX_INT))
+    return 0;
+  return 1;
+}
+
+/*
+ * Installs the interrupt handler.
+ *
+ * You should only have to add the code to unmask the interrupt.
+ *
+ */
+int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    rtems_interrupt_level level;
+    uint32_t *bsp_tbl;
+
+    bsp_tbl = (uint32_t*)&bsp_vector_table;
+    
+    if (!isValidInterrupt(irq->name)) {
+      return 0;
+    }
+
+    /*
+     * Check if default handler is actually connected. If not issue an error.
+     */
+    if (bsp_tbl[irq->name] != default_int_handler) {
+      return 0;
+    }
+
+    _CPU_ISR_Disable(level);
+
+    /*
+     * store the new handler
+     */
+    bsp_tbl[irq->name] = irq->hdl;
+
+    /*
+     * Enable interrupt on device
+     */
+    if(irq->on)
+    {
+    	irq->on(irq);
+    }
+    
+    _CPU_ISR_Enable(level);
+    
+    return 1;
+}
+
+/* 
+ * Remove and interrupt handler
+ *
+ * You should only have to add the code to mask the interrupt.
+ *
+ */
+int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    rtems_interrupt_level level;
+    uint32_t *bsp_tbl;
+
+    bsp_tbl = (uint32_t*)&bsp_vector_table;
+  
+    if (!isValidInterrupt(irq->name)) {
+      return 0;
+    }
+    /*
+     * Check if the handler is actually connected. If not issue an error.
+     */
+    if (bsp_tbl[irq->name] != irq->hdl) {
+      return 0;
+    }
+
+    _CPU_ISR_Disable(level);
+
+
+    /*
+     * Disable interrupt on device
+     */
+    if(irq->off) {
+        irq->off(irq);
+    }
+    /*
+     * restore the default irq value
+     */
+    bsp_tbl[irq->name] = default_int_handler;
+    
+
+    _CPU_ISR_Enable(level);
+
+    return 1;
+}
+
+
Index: c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,170 @@
+/*
+ * Interrupt handler Header file
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *	
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ *  $Id$
+ */
+
+#ifndef __IRQ_H__
+#define __IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+  /* define that can be useful (the values are just examples) */
+#ifndef __asm__
+
+/*
+ * Include some preprocessor value also used by assember code
+ */
+  
+#include <rtems.h>
+#include <mc9328mxl.h>
+
+extern void default_int_handler();
+/***********************************************************************
+ * Constants
+ **********************************************************************/
+
+/* enum of the possible interrupt sources on the AT91RM9200 */
+typedef enum {
+    BSP_INT_UART3_PFERR = 0,
+    BSP_INT_UART3_RTS,
+    BSP_INT_UART3_DTR,
+    BSP_INT_UART3_UARTC,
+    BSP_INT_UART3_TX,
+    BSP_INT_PEN_UP,
+    BSP_INT_CSI,
+    BSP_INT_MMA_MAC,
+    BSP_INT_MMA,
+    BSP_INT_COMP,
+    BSP_INT_MSIRQ,
+    BSP_INT_GPIO_PORTA,
+    BSP_INT_GPIO_PORTB,
+    BSP_INT_GPIO_PORTC,
+    BSP_INT_LCDC,
+    BSP_INT_SIM_IRQ,
+    BSP_INT_SIM_DATA,
+    BSP_INT_RTC,
+    BSP_INT_RTC_SAM,
+    BSP_INT_UART2_PFERR,
+    BSP_INT_UART2_RTS,
+    BSP_INT_UART2_DTR,
+    BSP_INT_UART2_UARTC,
+    BSP_INT_UART2_TX,
+    BSP_INT_UART2_RX,
+    BSP_INT_UART1_PFERR,
+    BSP_INT_UART1_RTS,
+    BSP_INT_UART1_DTR,
+    BSP_INT_UART1_UARTC,
+    BSP_INT_UART1_TX,
+    BSP_INT_UART1_RX,
+    BSP_INT_RES31,
+    BSP_INT_RES32,
+    BSP_INT_PEN_DATA,
+    BSP_INT_PWM,
+    BSP_INT_MMC_IRQ,
+    BSP_INT_SSI2_TX,
+    BSP_INT_SSI2_RX,
+    BSP_INT_SSI2_ERR,
+    BSP_INT_I2C,
+    BSP_INT_SPI2,
+    BSP_INT_SPI1,
+    BSP_INT_SSI_TX,
+    BSP_INT_SSI_TX_ERR,
+    BSP_INT_SSI_RX,
+    BSP_INT_SSI_RX_ERR,
+    BSP_INT_TOUCH,
+    BSP_INT_USBD0,
+    BSP_INT_USBD1,
+    BSP_INT_USBD2,
+    BSP_INT_USBD3,
+    BSP_INT_USBD4,
+    BSP_INT_USBD5,
+    BSP_INT_USBD6,
+    BSP_INT_UART3_RX,
+    BSP_INT_BTSYS,
+    BSP_INT_BTTIM,
+    BSP_INT_BTWUI,
+    BSP_INT_TIMER2,
+    BSP_INT_TIMER1,
+    BSP_INT_DMA_ERR,
+    BSP_INT_DMA,
+    BSP_INT_GPIO_PORTD,
+    BSP_INT_WDT,
+
+    BSP_MAX_INT
+} rtems_irq_symbolic_name;
+
+extern void *bsp_vector_table;
+#define VECTOR_TABLE &bsp_vector_table;
+  											   
+typedef unsigned char  rtems_irq_level;
+typedef unsigned char  rtems_irq_trigger;
+
+struct  __rtems_irq_connect_data__;     /* forward declaratiuon */
+
+typedef void (*rtems_irq_hdl)       (void);
+typedef void (*rtems_irq_enable)    (const struct __rtems_irq_connect_data__*);
+typedef void (*rtems_irq_disable)   (const struct __rtems_irq_connect_data__*);
+typedef int  (*rtems_irq_is_enabled)(const struct __rtems_irq_connect_data__*);
+
+typedef struct __rtems_irq_connect_data__ {
+    /* IRQ line */
+    rtems_irq_symbolic_name       name;
+
+    /* Handler */
+    rtems_irq_hdl                 hdl;
+
+    /* function for enabling interrupts at device level. */
+    rtems_irq_enable              on;
+
+    /* function for disabling interrupts at device level. */
+    rtems_irq_disable             off;
+
+    /* Function to test if interrupt is enabled */
+    rtems_irq_is_enabled        isOn;
+
+    /* priority level of interrupt */
+    rtems_irq_level               irqLevel;
+
+    /* Trigger method (rising/falling edge or high/low level) */
+    rtems_irq_trigger             irqTrigger;
+} rtems_irq_connect_data;
+
+/*
+ * function to initialize the interrupt for a specific BSP
+ */
+void BSP_rtems_irq_mngt_init();
+
+
+/*
+ * function to connect a particular irq handler.
+ */
+int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
+
+/*
+ * function to get the current RTEMS irq handler for ptr->name. 
+ */
+int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
+
+/*
+ * function to disconnect the RTEMS irq handler for ptr->name.
+ */
+int BSP_remove_rtems_irq_handler        (const rtems_irq_connect_data*);
+
+#endif /* __asm__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H__ */
Index: c/src/lib/libcpu/arm/mc9328mxl/timer/.cvsignore
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/timer/.cvsignore	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/timer/.cvsignore	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,14 @@
+Makefile
+Makefile.in
+aclocal.m4
+autom4te.cache
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
Index: c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c
===================================================================
--- c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
+++ c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c	(revision 1cfcfd3cfbf65c0d3171e8939134329db4539f08)
@@ -0,0 +1,113 @@
+/*
+ * Cogent CSB336 Timer driver
+ *
+ * This uses timer 2 for timing measurments.
+ *
+ * Copyright (c) 2004 Cogent Computer Systems
+ *        Written by Jay Monkman <jtm@lopingdog.com>
+ *	
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ * Notes:
+ *  This file manages the benchmark timer used by the RTEMS Timing Test
+ *  Suite.  Each measured time period is demarcated by calls to
+ *  Timer_initialize() and Read_timer().  Read_timer() usually returns
+ *  the number of microseconds since Timer_initialize() exitted.
+ *
+ *  It is important that the timer start/stop overhead be determined 
+ *  when porting or modifying this code.
+ *
+ *  timer.c,v 1.1 2002/11/13 17:55:09 joel Exp
+*/
+
+#include <rtems.h>
+#include <bsp.h>
+#include <mc9328mxl.h>
+
+uint32_t g_start;
+uint32_t g_freq;
+
+rtems_boolean Timer_driver_Find_average_overhead;
+
+    
+/*
+ * Set up Timer 1
+ */
+void Timer_initialize( void )
+{
+    MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 | 
+                            MC9328MXL_TMR_TCTL_FRR |
+                            MC9328MXL_TMR_TCTL_TEN);
+    /* set prescaler to 1 (register value + 1) */ \
+    MC9328MXL_TMR2_TPRER = 0;
+
+    /* get freq of counter in KHz */
+    g_freq = get_perclk1_freq() / 1000;
+
+    g_start =  MC9328MXL_TMR2_TCN;
+}
+
+/*
+ *  The following controls the behavior of Read_timer().
+ *
+ *  AVG_OVEREHAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      0  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in microseconds. */
+#define LEAST_VALID       1  /* Don't trust a clicks value lower than this */
+
+int Read_timer( void )
+{
+  rtems_unsigned32 t;
+  unsigned long long total;
+
+  t =  MC9328MXL_TMR2_TCN;
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+
+  total = (t - g_start);
+
+  /* convert to nanoseconds */
+  total = (total * 1000)/ g_freq; 
+
+  if ( Timer_driver_Find_average_overhead == 1 ) {
+    return (int) total; 
+  } else if ( total < LEAST_VALID ) {
+      return 0;       
+  }
+  /*
+   *  Somehow convert total into microseconds
+   */
+
+  return (total - AVG_OVERHEAD);
+}
+
+/*
+ *  Empty function call used in loops to measure basic cost of looping
+ *  in Timing Test Suite.
+ */
+
+rtems_status_code Empty_function( void )
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+void Set_find_average_overhead(
+  rtems_boolean find_flag
+)
+{
+  Timer_driver_Find_average_overhead = find_flag;
+}
+
