Changeset 1c62f74d in rtems


Ignore:
Timestamp:
Apr 17, 2014, 9:11:58 AM (6 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
62fa1ea
Parents:
bebcfa57
git-author:
Ralf Kirchner <ralf.kirchner@…> (04/17/14 09:11:58)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/17/14 11:25:12)
Message:

bsp/arm: Add L2 cache locking

This level 2 cache is a shared data and instruction cache and thus needs locking.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    rbebcfa57 r1c62f74d  
    6060#include <bsp.h>
    6161#include <libcpu/arm-cp15.h>
     62#include <rtems/rtems/intr.h>
    6263#include <bsp/arm-release-id.h>
    6364#include <bsp/arm-errata.h>
     
    8384#define CACHE_MIN( a, b ) \
    8485  ((a < b) ? (a) : (b))
     86
     87#define CACHE_MAX_LOCKING_BYTES (4 * 1024)
    8588
    8689
     
    458461} L2CC;
    459462
     463rtems_interrupt_lock l2c_310_cache_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER(
     464  "cache"
     465);
     466
    460467/* Errata table for the LC2 310 Level 2 cache from ARM.
    461468* Information taken from ARMs
     
    10611068cache_l2c_310_flush_range( const void* d_addr, const size_t n_bytes )
    10621069{
     1070  rtems_interrupt_lock_context lock_context;
    10631071  /* Back starting address up to start of a line and invalidate until ADDR_LAST */
    10641072  uint32_t       adx               = (uint32_t)d_addr
     
    10701078  bool is_errata_588369_applicable =
    10711079    l2c_310_cache_errata_is_applicable_588369();
     1080
     1081  rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    10721082
    10731083  for (;
     
    10841094  }
    10851095  cache_l2c_310_sync();
     1096  rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    10861097}
    10871098
     
    10891100cache_l2c_310_flush_entire( void )
    10901101{
    1091   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1102  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1103  rtems_interrupt_lock_context lock_context;
    10921104
    10931105  /* Only flush if level 2 cache is active */
     
    10971109    _ARM_Data_memory_barrier();
    10981110
     1111    rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    10991112    l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
    11001113
     
    11061119    /* Wait for the flush to complete */
    11071120    cache_l2c_310_sync();
     1121
     1122    rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    11081123  }
    11091124}
     
    11231138cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST )
    11241139{
    1125     volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
    1126 
    1127     /* Back starting address up to start of a line and invalidate until end */
     1140  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1141  rtems_interrupt_lock_context lock_context;
     1142
     1143  rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    11281144  for (;
    11291145       adx <= ADDR_LAST;
     
    11321148    l2cc->inv_pa = adx;
    11331149  }
    1134     cache_l2c_310_sync();
    1135   }
     1150  cache_l2c_310_sync();
     1151  rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    11361152}
    11371153
     
    11571173cache_l2c_310_clean_and_invalidate_entire( void )
    11581174{
    1159   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
    1160 
     1175  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1176  rtems_interrupt_lock_context lock_context;
    11611177
    11621178  if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) {
     
    11661182    _ARM_Data_memory_barrier();
    11671183
     1184    rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    11681185    l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
    11691186
     
    11721189    /* Wait for the invalidate to complete */
    11731190    cache_l2c_310_sync();
     1191
     1192    rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    11741193  }
    11751194}
     
    13121331cache_l2c_310_disable( void )
    13131332{
    1314   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
    1315 
     1333  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1334  rtems_interrupt_lock_context lock_context;
    13161335
    13171336  if ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) {
    13181337    /* Clean and Invalidate L2 Cache */
    13191338    cache_l2c_310_flush_entire();
     1339    rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    13201340
    13211341    /* Level 2 configuration and control registers must not get written while
     
    13291349    /* Disable the L2 cache */
    13301350    l2cc->ctrl &= ~CACHE_L2C_310_L2CC_ENABLE_MASK;
     1351    rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    13311352  }
    13321353}
     
    14961517_CPU_cache_invalidate_entire_instruction( void )
    14971518{
     1519  rtems_interrupt_lock_context lock_context;
     1520
     1521  rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    14981522  cache_l2c_310_invalidate_entire();
     1523  rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    14991524  arm_cache_l1_invalidate_entire_instruction();
    15001525}
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