Changeset 1be1e913 in rtems
- Timestamp:
- 03/31/04 05:17:45 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- bd97803
- Parents:
- cdf41b07
- Location:
- c/src/lib/libbsp/sparc/erc32
- Files:
-
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/sparc/erc32/ChangeLog
rcdf41b07 r1be1e913 1 2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * clock/ckinit.c, console/console.c, console/debugputs.c, 4 erc32sonic/erc32sonic.c, include/bsp.h, include/erc32.h, 5 startup/setvec.c, startup/spurious.c, timer/timer.c: Convert to 6 using c99 fixed size types. 7 1 8 2004-02-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 9 -
c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
rcdf41b07 r1be1e913 40 40 */ 41 41 42 volatile rtems_unsigned32Clock_driver_ticks;42 volatile uint32_t Clock_driver_ticks; 43 43 44 44 /* … … 49 49 */ 50 50 51 extern rtems_unsigned32CPU_SPARC_CLICKS_PER_TICK;51 extern uint32_t CPU_SPARC_CLICKS_PER_TICK; 52 52 53 53 rtems_isr_entry Old_ticker; … … 230 230 ) 231 231 { 232 rtems_unsigned32isrlevel;232 uint32_t isrlevel; 233 233 rtems_libio_ioctl_args_t *args = pargp; 234 234 -
c/src/lib/libbsp/sparc/erc32/console/console.c
rcdf41b07 r1be1e913 109 109 if ( !Ring_buffer_Is_empty( &TX_Buffer[ 0 ] ) ) { 110 110 Ring_buffer_Remove_character( &TX_Buffer[ 0 ], ch ); 111 ERC32_MEC.UART_Channel_A = (u nsigned32) ch;111 ERC32_MEC.UART_Channel_A = (uint32_t) ch; 112 112 } else 113 113 Is_TX_active[ 0 ] = FALSE; … … 150 150 if ( !Ring_buffer_Is_empty( &TX_Buffer[ 1 ] ) ) { 151 151 Ring_buffer_Remove_character( &TX_Buffer[ 1 ], ch ); 152 ERC32_MEC.UART_Channel_B = (u nsigned32) ch;152 ERC32_MEC.UART_Channel_B = (uint32_t) ch; 153 153 } else 154 154 Is_TX_active[ 1 ] = FALSE; … … 173 173 void console_exit() 174 174 { 175 rtems_unsigned32port;176 rtems_unsigned32ch;175 uint32_t port; 176 uint32_t ch; 177 177 178 178 /* … … 221 221 222 222 #ifdef RDB_BREAK_IN 223 extern u nsigned32trap_table[];223 extern uint32_t trap_table[]; 224 224 #endif 225 225 -
c/src/lib/libbsp/sparc/erc32/console/debugputs.c
rcdf41b07 r1be1e913 102 102 { 103 103 char *s; 104 u nsigned32old_level;104 uint32_t old_level; 105 105 106 106 ERC32_Disable_interrupt( ERC32_INTERRUPT_UART_A_RX_TX, old_level ); -
c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
rcdf41b07 r1be1e913 18 18 void erc32_sonic_write_register( 19 19 void *base, 20 u nsigned32regno,21 u nsigned32value20 uint32_t regno, 21 uint32_t value 22 22 ) 23 23 { 24 volatile u nsigned32*p = base;24 volatile uint32_t *p = base; 25 25 26 26 #if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) … … 32 32 } 33 33 34 u nsigned32erc32_sonic_read_register(34 uint32_t erc32_sonic_read_register( 35 35 void *base, 36 u nsigned32regno36 uint32_t regno 37 37 ) 38 38 { 39 volatile u nsigned32*p = base;40 u nsigned32value;39 volatile uint32_t *p = base; 40 uint32_t value; 41 41 42 42 value = p[regno]; -
c/src/lib/libbsp/sparc/erc32/include/bsp.h
rcdf41b07 r1be1e913 132 132 */ 133 133 134 extern void Clock_delay( rtems_unsigned32microseconds);134 extern void Clock_delay(uint32_t microseconds); 135 135 136 136 #define delay( microseconds ) Clock_delay(microseconds) -
c/src/lib/libbsp/sparc/erc32/include/erc32.h
rcdf41b07 r1be1e913 99 99 100 100 typedef struct { 101 volatile u nsigned32Control; /* offset 0x00 */102 volatile u nsigned32Software_Reset; /* offset 0x04 */103 volatile u nsigned32Power_Down; /* offset 0x08 */104 volatile u nsigned32Unimplemented_0; /* offset 0x0c */105 volatile u nsigned32Memory_Configuration; /* offset 0x10 */106 volatile u nsigned32IO_Configuration; /* offset 0x14 */107 volatile u nsigned32Wait_State_Configuration; /* offset 0x18 */108 volatile u nsigned32Unimplemented_1; /* offset 0x1c */109 volatile u nsigned32Memory_Access_0; /* offset 0x20 */110 volatile u nsigned32Memory_Access_1; /* offset 0x24 */111 volatile u nsigned32Unimplemented_2[ 7 ]; /* offset 0x28 */112 volatile u nsigned32Interrupt_Shape; /* offset 0x44 */113 volatile u nsigned32Interrupt_Pending; /* offset 0x48 */114 volatile u nsigned32Interrupt_Mask; /* offset 0x4c */115 volatile u nsigned32Interrupt_Clear; /* offset 0x50 */116 volatile u nsigned32Interrupt_Force; /* offset 0x54 */117 volatile u nsigned32Unimplemented_3[ 2 ]; /* offset 0x58 */101 volatile uint32_t Control; /* offset 0x00 */ 102 volatile uint32_t Software_Reset; /* offset 0x04 */ 103 volatile uint32_t Power_Down; /* offset 0x08 */ 104 volatile uint32_t Unimplemented_0; /* offset 0x0c */ 105 volatile uint32_t Memory_Configuration; /* offset 0x10 */ 106 volatile uint32_t IO_Configuration; /* offset 0x14 */ 107 volatile uint32_t Wait_State_Configuration; /* offset 0x18 */ 108 volatile uint32_t Unimplemented_1; /* offset 0x1c */ 109 volatile uint32_t Memory_Access_0; /* offset 0x20 */ 110 volatile uint32_t Memory_Access_1; /* offset 0x24 */ 111 volatile uint32_t Unimplemented_2[ 7 ]; /* offset 0x28 */ 112 volatile uint32_t Interrupt_Shape; /* offset 0x44 */ 113 volatile uint32_t Interrupt_Pending; /* offset 0x48 */ 114 volatile uint32_t Interrupt_Mask; /* offset 0x4c */ 115 volatile uint32_t Interrupt_Clear; /* offset 0x50 */ 116 volatile uint32_t Interrupt_Force; /* offset 0x54 */ 117 volatile uint32_t Unimplemented_3[ 2 ]; /* offset 0x58 */ 118 118 /* offset 0x60 */ 119 volatile u nsigned32Watchdog_Program_and_Timeout_Acknowledge;120 volatile u nsigned32Watchdog_Trap_Door_Set; /* offset 0x64 */121 volatile u nsigned32Unimplemented_4[ 6 ]; /* offset 0x68 */122 volatile u nsigned32Real_Time_Clock_Counter; /* offset 0x80 */123 volatile u nsigned32Real_Time_Clock_Scalar; /* offset 0x84 */124 volatile u nsigned32General_Purpose_Timer_Counter; /* offset 0x88 */125 volatile u nsigned32General_Purpose_Timer_Scalar; /* offset 0x8c */126 volatile u nsigned32Unimplemented_5[ 2 ]; /* offset 0x90 */127 volatile u nsigned32Timer_Control; /* offset 0x98 */128 volatile u nsigned32Unimplemented_6; /* offset 0x9c */129 volatile u nsigned32System_Fault_Status; /* offset 0xa0 */130 volatile u nsigned32First_Failing_Address; /* offset 0xa4 */131 volatile u nsigned32First_Failing_Data; /* offset 0xa8 */132 volatile u nsigned32First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */133 volatile u nsigned32Error_and_Reset_Status; /* offset 0xb0 */134 volatile u nsigned32Error_Mask; /* offset 0xb4 */135 volatile u nsigned32Unimplemented_7[ 2 ]; /* offset 0xb8 */136 volatile u nsigned32Debug_Control; /* offset 0xc0 */137 volatile u nsigned32Breakpoint; /* offset 0xc4 */138 volatile u nsigned32Watchpoint; /* offset 0xc8 */139 volatile u nsigned32Unimplemented_8; /* offset 0xcc */140 volatile u nsigned32Test_Control; /* offset 0xd0 */141 volatile u nsigned32Test_Data; /* offset 0xd4 */142 volatile u nsigned32Unimplemented_9[ 2 ]; /* offset 0xd8 */143 volatile u nsigned32UART_Channel_A; /* offset 0xe0 */144 volatile u nsigned32UART_Channel_B; /* offset 0xe4 */145 volatile u nsigned32UART_Status; /* offset 0xe8 */119 volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge; 120 volatile uint32_t Watchdog_Trap_Door_Set; /* offset 0x64 */ 121 volatile uint32_t Unimplemented_4[ 6 ]; /* offset 0x68 */ 122 volatile uint32_t Real_Time_Clock_Counter; /* offset 0x80 */ 123 volatile uint32_t Real_Time_Clock_Scalar; /* offset 0x84 */ 124 volatile uint32_t General_Purpose_Timer_Counter; /* offset 0x88 */ 125 volatile uint32_t General_Purpose_Timer_Scalar; /* offset 0x8c */ 126 volatile uint32_t Unimplemented_5[ 2 ]; /* offset 0x90 */ 127 volatile uint32_t Timer_Control; /* offset 0x98 */ 128 volatile uint32_t Unimplemented_6; /* offset 0x9c */ 129 volatile uint32_t System_Fault_Status; /* offset 0xa0 */ 130 volatile uint32_t First_Failing_Address; /* offset 0xa4 */ 131 volatile uint32_t First_Failing_Data; /* offset 0xa8 */ 132 volatile uint32_t First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */ 133 volatile uint32_t Error_and_Reset_Status; /* offset 0xb0 */ 134 volatile uint32_t Error_Mask; /* offset 0xb4 */ 135 volatile uint32_t Unimplemented_7[ 2 ]; /* offset 0xb8 */ 136 volatile uint32_t Debug_Control; /* offset 0xc0 */ 137 volatile uint32_t Breakpoint; /* offset 0xc4 */ 138 volatile uint32_t Watchpoint; /* offset 0xc8 */ 139 volatile uint32_t Unimplemented_8; /* offset 0xcc */ 140 volatile uint32_t Test_Control; /* offset 0xd0 */ 141 volatile uint32_t Test_Data; /* offset 0xd4 */ 142 volatile uint32_t Unimplemented_9[ 2 ]; /* offset 0xd8 */ 143 volatile uint32_t UART_Channel_A; /* offset 0xe0 */ 144 volatile uint32_t UART_Channel_B; /* offset 0xe4 */ 145 volatile uint32_t UART_Status; /* offset 0xe8 */ 146 146 } ERC32_Register_Map; 147 147 … … 343 343 #define ERC32_Force_interrupt( _source ) \ 344 344 do { \ 345 u nsigned32_level; \345 uint32_t _level; \ 346 346 \ 347 347 _level = sparc_disable_interrupts(); \ … … 359 359 #define ERC32_Mask_interrupt( _source ) \ 360 360 do { \ 361 u nsigned32_level; \361 uint32_t _level; \ 362 362 \ 363 363 _level = sparc_disable_interrupts(); \ … … 368 368 #define ERC32_Unmask_interrupt( _source ) \ 369 369 do { \ 370 u nsigned32_level; \370 uint32_t _level; \ 371 371 \ 372 372 _level = sparc_disable_interrupts(); \ … … 377 377 #define ERC32_Disable_interrupt( _source, _previous ) \ 378 378 do { \ 379 u nsigned32_level; \380 u nsigned32_mask = 1 << (_source); \379 uint32_t _level; \ 380 uint32_t _mask = 1 << (_source); \ 381 381 \ 382 382 _level = sparc_disable_interrupts(); \ … … 389 389 #define ERC32_Restore_interrupt( _source, _previous ) \ 390 390 do { \ 391 u nsigned32_level; \392 u nsigned32_mask = 1 << (_source); \391 uint32_t _level; \ 392 uint32_t _mask = 1 << (_source); \ 393 393 \ 394 394 _level = sparc_disable_interrupts(); \ … … 449 449 #define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005 450 450 451 extern u nsigned32_ERC32_MEC_Timer_Control_Mirror;451 extern uint32_t _ERC32_MEC_Timer_Control_Mirror; 452 452 453 453 /* … … 459 459 #define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \ 460 460 do { \ 461 u nsigned32_level; \462 u nsigned32_control; \463 u nsigned32__value; \461 uint32_t _level; \ 462 uint32_t _control; \ 463 uint32_t __value; \ 464 464 \ 465 465 __value = ((_value) & 0x0f); \ … … 488 488 #define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \ 489 489 do { \ 490 u nsigned32_level; \491 u nsigned32_control; \492 u nsigned32__value; \490 uint32_t _level; \ 491 uint32_t _control; \ 492 uint32_t __value; \ 493 493 \ 494 494 __value = ((_value) & 0x0f) << 8; \ -
c/src/lib/libbsp/sparc/erc32/startup/setvec.c
rcdf41b07 r1be1e913 40 40 { 41 41 rtems_isr_entry previous_isr; 42 u nsigned32real_trap;43 u nsigned32source;42 uint32_t real_trap; 43 uint32_t source; 44 44 45 45 if ( type ) -
c/src/lib/libbsp/sparc/erc32/startup/spurious.c
rcdf41b07 r1be1e913 24 24 /* Simple integer-to-string conversion */ 25 25 26 void itos(u nsigned32u, char *s)26 void itos(uint32_t u, char *s) 27 27 { 28 28 int i; … … 45 45 { 46 46 char line[ 80 ]; 47 rtems_unsigned32real_trap;47 uint32_t real_trap; 48 48 49 49 real_trap = SPARC_REAL_TRAP_NUMBER(trap); … … 162 162 void bsp_spurious_initialize() 163 163 { 164 rtems_unsigned32trap;165 u nsigned32level = 15;166 u nsigned32mask;164 uint32_t trap; 165 uint32_t level = 15; 166 uint32_t mask; 167 167 168 168 sparc_disable_interrupts(level); -
c/src/lib/libbsp/sparc/erc32/timer/timer.c
rcdf41b07 r1be1e913 61 61 int Read_timer() 62 62 { 63 rtems_unsigned32total;63 uint32_t total; 64 64 65 65 total = ERC32_MEC.General_Purpose_Timer_Counter;
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