Changeset 18e1e5b in rtems

Timestamp:

May 23, 2013, 7:04:19 AM (8 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

4.11, 5, master

Children:

d9bd5cd6

Parents:

e67025e

git-author:

Sebastian Huber <sebastian.huber@…> (05/23/13 07:04:19)

git-committer:

Sebastian Huber <sebastian.huber@…> (05/27/13 10:49:13)

Message:

arm: Fix CPSR and SPSR access

The GNU assembler translates for example a

msr spsr, rN

into

msr SPSR_fc, rN

This would update only a subset of the register and leads to an
incomplete exceptions restore sequence resulting in system corruption.
Correct is this:

msr SPSR_fsxc, rN

Location:

cpukit/score/cpu/arm

Files:

• arm_exc_interrupt.S (modified) (3 diffs)
• cpu_asm.S (modified) (2 diffs)

cpukit/score/cpu/arm/arm_exc_interrupt.S

@@ -64 +64 @@
         /* Set exchange registers */
         mov     EXCHANGE_LR, lr
-        mrs     EXCHANGE_SPSR, spsr
-        mrs     EXCHANGE_CPSR, cpsr
+        mrs     EXCHANGE_SPSR, SPSR
+        mrs     EXCHANGE_CPSR, CPSR
         sub     EXCHANGE_INT_SP, sp, #EXCHANGE_SIZE
 
         /* Switch to SVC mode */
         orr     EXCHANGE_CPSR, EXCHANGE_CPSR, #0x1
-        msr     cpsr, EXCHANGE_CPSR
+        msr     CPSR_c, EXCHANGE_CPSR
 
         /*
@@ -184 +184 @@
 
         /* Get INT mode program status register */
-        mrs     r1, cpsr
+        mrs     r1, CPSR
         bic     r1, r1, #0x1
 
         /* Switch to INT mode */
-        msr     cpsr, r1
+        msr     CPSR_c, r1
 
         /* Save EXCHANGE_LR and EXCHANGE_SPSR registers to exchange area */
@@ -198 +198 @@
         /* Set return address and program status */
         mov     lr, EXCHANGE_LR
-        msr     spsr, EXCHANGE_SPSR
+        msr     SPSR_fsxc, EXCHANGE_SPSR
 
         /* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */

cpukit/score/cpu/arm/cpu_asm.S

@@ -55 +55 @@
 DEFINE_FUNCTION_ARM(_CPU_Context_switch)
 /* Start saving context */
-        mrs     r2, cpsr
+        mrs     r2, CPSR
         stmia   r0,  {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
 
@@ -72 +72 @@
 
         ldmia   r1,  {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
-        msr     cpsr, r2
+        msr     CPSR_fsxc, r2
 #ifdef __thumb__
         bx      lr