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Changeset 18b1a591 in rtems
- Timestamp:
- 10/27/22 18:47:03 (7 months ago)
- Branches:
- master
- Children:
- b4ffaa7c
- Parents:
- d64e10e
- git-author:
- Chris Johns <chrisj@…> (10/27/22 18:47:03)
- git-committer:
- Chris Johns <chrisj@…> (10/30/22 21:04:00)
- File:
-
- 1 edited
-
cpukit/libdebugger/rtems-debugger-arm.c (modified) (35 diffs)
Legend:
- Unmodified
- Added
- Removed
-
cpukit/libdebugger/rtems-debugger-arm.c
rd64e10e r18b1a591 1 1 /* 2 * Copyright (c) 2016-20 19Chris Johns <chrisj@rtems.org>.2 * Copyright (c) 2016-2022 Chris Johns <chrisj@rtems.org>. 3 3 * All rights reserved. 4 4 * … … 87 87 #define ARM_SWITCH_REG_ASM [arm_switch_reg] "=&r" (arm_switch_reg) 88 88 #define ARM_SWITCH_REG_ASM_L ARM_SWITCH_REG_ASM, 89 #define ASM_ARM_ASM ".align 2\n.arm\n" 89 90 #define ASM_ARM_MODE ".align 2\nbx pc\n.arm\n" 90 91 #define ASM_THUMB_MODE "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" 92 #define ARM_THUMB_MODE() __asm__ volatile(ASM_THUMB_MODE : ARM_SWITCH_REG_ASM : :); 93 #define ARM_ARM_MODE() __asm__ volatile(ASM_ARM_MODE : : :); 91 94 #else 92 95 #define ARM_SWITCH_REG 93 96 #define ARM_SWITCH_REG_ASM 94 97 #define ARM_SWITCH_REG_ASM_L 98 #define ASM_ARM_ASM 95 99 #define ASM_ARM_MODE 96 100 #define ASM_THUMB_MODE 101 #define ARM_THUMB_MODE() 102 #define ARM_ARM_MODE() 103 #endif 104 105 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS 106 #define ARM_SYNC_INST "isb\n" 107 #else 108 #define ARM_SYNC_INST 97 109 #endif 98 110 … … 288 300 289 301 /* 290 * ARM debug hardware. 302 * ARM debug hardware. These variables are directly access 303 * from assembler so do not change types. 291 304 */ 292 305 static int debug_version; 293 306 static void* debug_registers; 294 307 static int debug_revision; 295 static booldebug_disable_ints;308 static int debug_disable_ints; 296 309 static int hw_breakpoints; 297 310 static int hw_watchpoints; … … 300 313 * Hardware break and watch points. 301 314 */ 302 typedef struct303 {304 bool enabled;305 bool loaded;306 void* address;307 size_t length;308 CPU_Exception_frame* frame;309 uint32_t control;310 uint32_t value;311 } arm_debug_hwbreak;312 313 315 #define ARM_HW_BREAKPOINT_MAX (16) 314 316 #define ARM_HW_WATCHPOINT_MAX (16) … … 328 330 #define ARM_HW_BP_PRIV_ALL_MODES (0x03) 329 331 330 static arm_debug_hwbreak hw_breaks[ARM_HW_BREAKPOINT_MAX]; 331 //static arm_debug_hwbreak hw_watches[ARM_HW_WATCHPOINT_MAX]; 332 /* 333 * A hw breakpoint has DBGBCR and DBGBVR registers. Allocate memory 334 * for each. 335 * 336 * Maintian the values ready to load into the hardware. The loader is 337 * a load of the value and then control for enabled BPs. 338 */ 339 static uint32_t hw_breaks[ARM_HW_BREAKPOINT_MAX * 2]; 340 341 /* 342 * The order in the array is important 343 */ 344 #define ARM_HWB_BCR(_bp) (hw_breaks[((_bp) * 2) + 1]) 345 #define ARM_HWB_VCR(_bp) (hw_breaks[(_bp) * 2]) 346 #define ARM_HWB_ENALBED(_bp) ((ARM_HWB_BCR(_bp) & 1) != 0) 347 #define ARM_HWB_CLEAR(_bp) ARM_HWB_BCR(_bp) = 0; ARM_HWB_VCR(_bp) = 0 348 #define ARM_HWB_CLEAR_ALL() memset(&hw_breaks[0], 0, sizeof(hw_breaks)) 332 349 333 350 /* … … 440 457 ASM_ARM_MODE \ 441 458 ARM_CP_INSTR(mcr, _cp, _op1, val, _CRn, _CRm, _op2) \ 459 ARM_SYNC_INST \ 442 460 ASM_THUMB_MODE \ 443 461 : ARM_SWITCH_REG_ASM \ … … 450 468 asm volatile( \ 451 469 ASM_ARM_MODE \ 470 ARM_SYNC_INST \ 452 471 ARM_CP_INSTR(mrc, _cp, _op1, val, _CRn, _CRm, _op2) \ 453 472 ASM_THUMB_MODE \ … … 492 511 * offset from the base address. 493 512 */ 494 #define ARM_MMAP_ADDR(reg) (((volatile uint32_t*) debug_registers) + (reg)) 495 #define ARM_MMAP_WRITE(reg, val) *ARM_MMAP_ADDR(reg) = (val); _ARM_Data_synchronization_barrier() 496 #define ARM_MMAP_READ(reg) *ARM_MMAP_ADDR(reg) 513 #define ARM_MMAP_ADDR(reg) \ 514 (((volatile uint32_t*) debug_registers) + (reg)) 515 #define ARM_MMAP_WRITE(reg, val) *ARM_MMAP_ADDR(reg) = (val) 516 #define ARM_MMAP_READ(reg) *ARM_MMAP_ADDR(reg) 517 #define ARM_MMAP_WRITE_SYNC(reg, val) \ 518 ARM_MMAP_WRITE(reg, val); \ 519 _ARM_Data_synchronization_barrier(); \ 520 _ARM_Instruction_synchronization_barrier() 521 522 /* 523 * Debug hardware breakpoint registers. 524 */ 525 #define ARM_MMAP_DBGDSCR 34 526 #define ARM_MMAP_DBGBCR 80 527 #define ARM_MMAP_DBGBVR 64 497 528 498 529 static bool … … 903 934 */ 904 935 if (ARM_MMAP_READ(1005) == 3) { 905 ARM_MMAP_WRITE (1004, 0xC5ACCE55);936 ARM_MMAP_WRITE_SYNC(1004, 0xC5ACCE55); 906 937 } 907 938 /* 908 939 * Are we already in debug mode? 909 940 */ 910 val = ARM_MMAP_READ( 34);941 val = ARM_MMAP_READ(ARM_MMAP_DBGDSCR); 911 942 if ((val & (1 << 15)) == 0) { 912 943 rtems_debugger_printf("rtems-db: arm debug: enable debug mode\n"); 913 val = ARM_MMAP_READ(34); 914 ARM_MMAP_WRITE(34, ARM_MMAP_READ(34) | (1 << 15)); 944 val = ARM_MMAP_READ(ARM_MMAP_DBGDSCR); 945 ARM_MMAP_WRITE_SYNC(ARM_MMAP_DBGDSCR, 946 ARM_MMAP_READ(ARM_MMAP_DBGDSCR) | (1 << 15)); 915 947 arm_debug_retries = 0; 916 948 } … … 1003 1035 1004 1036 static inline void 1005 arm_debug_break_setup( arm_debug_hwbreak*bp,1006 uint32_t 1007 uint32_t 1008 uint32_t 1009 uint32_t 1010 { 1011 bp->control= (((type & 0xf) << 20) |1012 ((byte_address_select & 0xf) << 5) |1013 ((privilege & 0x3) << 1) | 1);1014 bp->value = (intptr_t) address;1037 arm_debug_break_setup(int bp, 1038 uint32_t address, 1039 uint32_t type, 1040 uint32_t byte_address_select, 1041 uint32_t privilege) 1042 { 1043 ARM_HWB_BCR(bp) = (((type & 0xf) << 20) | 1044 ((byte_address_select & 0xf) << 5) | 1045 ((privilege & 0x3) << 1) | 1); 1046 ARM_HWB_VCR(bp) = (intptr_t) (address & (~3)); 1015 1047 } 1016 1048 1017 1049 static void 1018 arm_debug_break_write_control(int bp, uint32_t control) 1019 { 1020 if (bp < 15) { 1021 if (debug_registers != NULL) { 1022 ARM_MMAP_WRITE(80 + bp, control); 1050 arm_debug_break_c14_write_control(int bp, uint32_t control) 1051 { 1052 switch (bp) { 1053 case 0: 1054 ARM_CP14_WRITE(control, 0, 0, 5); 1055 break; 1056 case 1: 1057 ARM_CP14_WRITE(control, 0, 1, 5); 1058 break; 1059 case 2: 1060 ARM_CP14_WRITE(control, 0, 2, 5); 1061 break; 1062 case 3: 1063 ARM_CP14_WRITE(control, 0, 3, 5); 1064 break; 1065 case 4: 1066 ARM_CP14_WRITE(control, 0, 4, 5); 1067 break; 1068 case 5: 1069 ARM_CP14_WRITE(control, 0, 5, 5); 1070 break; 1071 case 6: 1072 ARM_CP14_WRITE(control, 0, 6, 5); 1073 break; 1074 case 7: 1075 ARM_CP14_WRITE(control, 0, 7, 5); 1076 break; 1077 case 8: 1078 ARM_CP14_WRITE(control, 0, 8, 5); 1079 break; 1080 case 9: 1081 ARM_CP14_WRITE(control, 0, 9, 5); 1082 break; 1083 case 10: 1084 ARM_CP14_WRITE(control, 0, 10, 5); 1085 break; 1086 case 11: 1087 ARM_CP14_WRITE(control, 0, 11, 5); 1088 break; 1089 case 12: 1090 ARM_CP14_WRITE(control, 0, 12, 5); 1091 break; 1092 case 13: 1093 ARM_CP14_WRITE(control, 0, 13, 5); 1094 break; 1095 case 14: 1096 ARM_CP14_WRITE(control, 0, 14, 5); 1097 break; 1098 case 15: 1099 ARM_CP14_WRITE(control, 0, 15, 5); 1100 break; 1101 } 1102 } 1103 1104 static void 1105 arm_debug_break_c14_write_value(int bp, uint32_t value) 1106 { 1107 switch (bp) { 1108 case 0: 1109 ARM_CP14_WRITE(value, 0, 0, 4); 1110 break; 1111 case 1: 1112 ARM_CP14_WRITE(value, 0, 1, 4); 1113 break; 1114 case 2: 1115 ARM_CP14_WRITE(value, 0, 2, 4); 1116 break; 1117 case 3: 1118 ARM_CP14_WRITE(value, 0, 3, 4); 1119 break; 1120 case 4: 1121 ARM_CP14_WRITE(value, 0, 4, 4); 1122 break; 1123 case 5: 1124 ARM_CP14_WRITE(value, 0, 5, 4); 1125 break; 1126 case 6: 1127 ARM_CP14_WRITE(value, 0, 6, 4); 1128 break; 1129 case 7: 1130 ARM_CP14_WRITE(value, 0, 7, 4); 1131 break; 1132 case 8: 1133 ARM_CP14_WRITE(value, 0, 8, 4); 1134 break; 1135 case 9: 1136 ARM_CP14_WRITE(value, 0, 9, 4); 1137 break; 1138 case 10: 1139 ARM_CP14_WRITE(value, 0, 10, 4); 1140 break; 1141 case 11: 1142 ARM_CP14_WRITE(value, 0, 11, 4); 1143 break; 1144 case 12: 1145 ARM_CP14_WRITE(value, 0, 12, 4); 1146 break; 1147 case 13: 1148 ARM_CP14_WRITE(value, 0, 13, 4); 1149 break; 1150 case 14: 1151 ARM_CP14_WRITE(value, 0, 14, 4); 1152 break; 1153 case 15: 1154 ARM_CP14_WRITE(value, 0, 15, 4); 1155 break; 1156 } 1157 } 1158 1159 static uint32_t 1160 arm_debug_dbgdscr_read(void) 1161 { 1162 uint32_t val; 1163 if (debug_registers != NULL) { 1164 val = ARM_MMAP_READ(ARM_MMAP_DBGDSCR); 1165 } 1166 else { 1167 ARM_CP14_READ(val, 0, 1, 0); 1168 } 1169 return val; 1170 } 1171 1172 static void 1173 arm_debug_dbgdscr_write(uint32_t val) 1174 { 1175 if (debug_registers != NULL) { 1176 ARM_MMAP_WRITE_SYNC(ARM_MMAP_DBGDSCR, val); 1177 } 1178 else { 1179 ARM_CP14_WRITE(val, 0, 1, 0); 1180 } 1181 } 1182 1183 static uint32_t 1184 arm_debug_method_of_entry(void) 1185 { 1186 return (arm_debug_dbgdscr_read() >> 2) & 0xf; 1187 } 1188 1189 static void 1190 arm_debug_disable_interrupts(void) 1191 { 1192 debug_disable_ints = 1; 1193 } 1194 1195 static void 1196 arm_debug_enable_interrupts(void) 1197 { 1198 arm_debug_dbgdscr_write(arm_debug_dbgdscr_read() & ~(1 << 11)); 1199 } 1200 1201 static void 1202 arm_debug_break_clear(int bp) 1203 { 1204 rtems_interrupt_lock_context lock_context; 1205 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 1206 ARM_HWB_CLEAR(bp); 1207 rtems_interrupt_lock_release(&target_lock, &lock_context); 1208 } 1209 1210 static void 1211 arm_debug_break_clear_all(void) 1212 { 1213 rtems_interrupt_lock_context lock_context; 1214 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 1215 ARM_HWB_CLEAR_ALL(); 1216 rtems_interrupt_lock_release(&target_lock, &lock_context); 1217 } 1218 1219 static inline void 1220 arm_debug_set_context_id(const uint32_t id) 1221 { 1222 #if ARM_CP15 1223 ARM_CP15_WRITE(id, 0, 13, 0, 1); 1224 #endif 1225 } 1226 1227 static void 1228 arm_debug_break_unload(void) 1229 { 1230 rtems_interrupt_lock_context lock_context; 1231 int i; 1232 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 1233 if (debug_registers != NULL) { 1234 for (i = 0; i < hw_breakpoints; ++i) { 1235 ARM_MMAP_WRITE(ARM_MMAP_DBGBCR + i, 0); 1236 ARM_MMAP_WRITE(ARM_MMAP_DBGBVR + i, 0); 1237 } 1238 } else { 1239 for (i = 0; i < hw_breakpoints; ++i) { 1240 arm_debug_break_c14_write_control(i, 0); 1241 arm_debug_break_c14_write_value(i, 0); 1242 } 1243 } 1244 rtems_interrupt_lock_release(&target_lock, &lock_context); 1245 } 1246 1247 static void 1248 arm_debug_break_exec_enable(int bp, uintptr_t addr, bool thumb, bool step) { 1249 uint32_t bas; 1250 1251 /* 1252 * See table C3-2 Effect of byte address selection on Breakpoint 1253 * generation and "Instruction address comparision programming 1254 * examples. 1255 */ 1256 if (thumb) { 1257 /* 1258 * Thumb 1259 */ 1260 if ((addr & (1 << 1)) == 0) { 1261 /* 1262 * Instruction address: DBGBVR[31:2]:00 BAS: 0bxx11 Mismatch: Miss 1263 */ 1264 bas = 0x3; /* bxx11 */ 1023 1265 } 1024 1266 else { 1025 switch (bp) { 1026 case 0: 1027 ARM_CP14_WRITE(control, 0, 0, 5); 1028 break; 1029 case 1: 1030 ARM_CP14_WRITE(control, 0, 1, 5); 1031 break; 1032 case 2: 1033 ARM_CP14_WRITE(control, 0, 2, 5); 1034 break; 1035 case 3: 1036 ARM_CP14_WRITE(control, 0, 3, 5); 1037 break; 1038 case 4: 1039 ARM_CP14_WRITE(control, 0, 4, 5); 1040 break; 1041 case 5: 1042 ARM_CP14_WRITE(control, 0, 5, 5); 1043 break; 1044 case 6: 1045 ARM_CP14_WRITE(control, 0, 6, 5); 1046 break; 1047 case 7: 1048 ARM_CP14_WRITE(control, 0, 7, 5); 1049 break; 1050 case 8: 1051 ARM_CP14_WRITE(control, 0, 8, 5); 1052 break; 1053 case 9: 1054 ARM_CP14_WRITE(control, 0, 9, 5); 1055 break; 1056 case 10: 1057 ARM_CP14_WRITE(control, 0, 10, 5); 1058 break; 1059 case 11: 1060 ARM_CP14_WRITE(control, 0, 11, 5); 1061 break; 1062 case 12: 1063 ARM_CP14_WRITE(control, 0, 12, 5); 1064 break; 1065 case 13: 1066 ARM_CP14_WRITE(control, 0, 13, 5); 1067 break; 1068 case 14: 1069 ARM_CP14_WRITE(control, 0, 14, 5); 1070 break; 1071 case 15: 1072 ARM_CP14_WRITE(control, 0, 15, 5); 1073 break; 1074 } 1267 /* 1268 * Instruction address: DBGBVR[31:2]:10 BAS: 0b11xx Mismatch: Miss 1269 */ 1270 bas = 0xc; /* b11xx */ 1075 1271 } 1076 1272 } 1077 }1078 1079 static void1080 arm_debug_break_write_value(int bp, uint32_t value)1081 {1082 if (bp < 15) {1083 if (debug_registers != NULL) {1084 ARM_MMAP_WRITE(64 + bp, value);1085 }1086 else {1087 switch (bp) {1088 case 0:1089 ARM_CP14_WRITE(value, 0, 0, 4);1090 break;1091 case 1:1092 ARM_CP14_WRITE(value, 0, 1, 4);1093 break;1094 case 2:1095 ARM_CP14_WRITE(value, 0, 2, 4);1096 break;1097 case 3:1098 ARM_CP14_WRITE(value, 0, 3, 4);1099 break;1100 case 4:1101 ARM_CP14_WRITE(value, 0, 4, 4);1102 break;1103 case 5:1104 ARM_CP14_WRITE(value, 0, 5, 4);1105 break;1106 case 6:1107 ARM_CP14_WRITE(value, 0, 6, 4);1108 break;1109 case 7:1110 ARM_CP14_WRITE(value, 0, 7, 4);1111 break;1112 case 8:1113 ARM_CP14_WRITE(value, 0, 8, 4);1114 break;1115 case 9:1116 ARM_CP14_WRITE(value, 0, 9, 4);1117 break;1118 case 10:1119 ARM_CP14_WRITE(value, 0, 10, 4);1120 break;1121 case 11:1122 ARM_CP14_WRITE(value, 0, 11, 4);1123 break;1124 case 12:1125 ARM_CP14_WRITE(value, 0, 12, 4);1126 break;1127 case 13:1128 ARM_CP14_WRITE(value, 0, 13, 4);1129 break;1130 case 14:1131 ARM_CP14_WRITE(value, 0, 14, 4);1132 break;1133 case 15:1134 ARM_CP14_WRITE(value, 0, 15, 4);1135 break;1136 }1137 }1138 }1139 }1140 1141 static uint32_t1142 arm_debug_dbgdscr_read(void)1143 {1144 uint32_t val;1145 if (debug_registers != NULL) {1146 val = ARM_MMAP_READ(34);1147 }1148 1273 else { 1149 ARM_CP14_READ(val, 0, 1, 0); 1150 } 1151 return val; 1152 } 1153 1154 static void 1155 arm_debug_dbgdscr_write(uint32_t val) 1156 { 1157 if (debug_registers != NULL) { 1158 ARM_MMAP_WRITE(34, val); 1159 } 1160 else { 1161 ARM_CP14_WRITE(val, 0, 1, 0); 1162 } 1163 } 1164 1165 static uint32_t 1166 arm_debug_method_of_entry(void) 1167 { 1168 return (arm_debug_dbgdscr_read() >> 2) & 0xf; 1169 } 1170 1171 static void 1172 arm_debug_disable_interrupts(void) 1173 { 1174 debug_disable_ints = true; 1175 } 1176 1177 static void 1178 arm_debug_commit_interrupt_disable(void) 1179 { 1180 if (debug_disable_ints) { 1181 arm_debug_dbgdscr_write(arm_debug_dbgdscr_read() | (1 << 11)); 1182 debug_disable_ints = false; 1183 } 1184 } 1185 1186 static void 1187 arm_debug_enable_interrupts(void) 1188 { 1189 arm_debug_dbgdscr_write(arm_debug_dbgdscr_read() & ~(1 << 11)); 1190 } 1191 1192 static void 1193 arm_debug_break_clear(void) 1194 { 1195 rtems_interrupt_lock_context lock_context; 1196 arm_debug_hwbreak* bp = &hw_breaks[0]; 1197 int i; 1198 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 1199 for (i = 0; i < hw_breakpoints; ++i, ++bp) { 1200 bp->enabled = false; 1201 bp->loaded = false; 1202 } 1203 rtems_interrupt_lock_release(&target_lock, &lock_context); 1204 } 1205 1206 static inline void 1207 arm_debug_set_context_id(const uint32_t id) 1208 { 1209 #if ARM_CP15 1210 ARM_CP15_WRITE(id, 0, 13, 0, 1); 1211 #endif 1212 } 1213 1214 /* 1215 * You can only load the hardware breaks points when in the SVC mode or the 1216 * single step inverted break point will trigger. 1217 */ 1218 static void 1219 arm_debug_break_load(void) 1220 { 1221 rtems_interrupt_lock_context lock_context; 1222 arm_debug_hwbreak* bp = &hw_breaks[0]; 1223 int i; 1224 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 1225 if (bp->enabled && !bp->loaded) { 1226 arm_debug_set_context_id(0xdead1111); 1227 arm_debug_break_write_value(0, bp->value); 1228 arm_debug_break_write_control(0, bp->control); 1229 } 1230 ++bp; 1231 for (i = 1; i < hw_breakpoints; ++i, ++bp) { 1232 if (bp->enabled && !bp->loaded) { 1233 bp->loaded = true; 1234 arm_debug_break_write_value(i, bp->value); 1235 arm_debug_break_write_control(i, bp->control); 1236 } 1237 } 1238 rtems_interrupt_lock_release(&target_lock, &lock_context); 1239 } 1240 1241 static void 1242 arm_debug_break_unload(void) 1243 { 1244 rtems_interrupt_lock_context lock_context; 1245 arm_debug_hwbreak* bp = &hw_breaks[0]; 1246 int i; 1247 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 1248 arm_debug_set_context_id(0); 1249 for (i = 0; i < hw_breakpoints; ++i, ++bp) { 1250 bp->loaded = false; 1251 arm_debug_break_write_control(i, 0); 1252 } 1253 rtems_interrupt_lock_release(&target_lock, &lock_context); 1274 /* 1275 * ARM 1276 * 1277 * Instruction address: DBGBVR[31:2]:00 BAS: 0b1111 Mismatch: Miss 1278 */ 1279 bas = 0xf; /* b1111 */ 1280 } 1281 1282 target_printk("[} break: addr:%08x bas:%x thumb:%s\n", 1283 addr, bas, thumb ? "yes" : "no"); 1284 1285 arm_debug_break_setup( 1286 bp, 1287 addr, 1288 step ? ARM_HW_BP_UNLINKED_INSTR_MISMATCH : ARM_HW_BP_UNLINKED_INSTR_MATCH, 1289 bas, 1290 ARM_HW_BP_PRIV_PL0_SUP_SYS); 1254 1291 } 1255 1292 … … 1258 1295 { 1259 1296 #if TARGET_DEBUG 1260 arm_debug_hwbreak* bp = &hw_breaks[0];1261 1297 int i; 1262 for (i = 0; i < hw_breakpoints; ++i , ++bp) {1263 if ( bp->enabled) {1298 for (i = 0; i < hw_breakpoints; ++i) { 1299 if (ARM_HWB_ENALBED(i)) { 1264 1300 target_printk("[} bp: %d: control: %08x addr: %08x\n", 1265 i, bp->control, bp->value);1301 i, ARM_HWB_BCR(i), ARM_HWB_VCR(i)); 1266 1302 } 1267 1303 } … … 1315 1351 #if ARM_CP15 1316 1352 const uint32_t ifsr = arm_cp15_get_instruction_fault_status(); 1353 const uint32_t dfsr = arm_cp15_get_data_fault_status(); 1354 const void* far = arm_cp15_get_fault_address(); 1317 1355 #else 1318 1356 const uint32_t ifsr = 0; … … 1342 1380 target_printk("[} > frame = %08" PRIx32 \ 1343 1381 " sig=%d vector=%u (%u) dbgdscr=%08" PRIx32 " moe=%s" \ 1344 " ifsr=%08" PRIx32 " pra=%08x\n",1345 (uint32_t) frame,1382 " far=%p ifsr=%08" PRIx32 " dfsr=%08" PRIx32 1383 " exc-ret-pc=%08x\n", (uint32_t) frame, 1346 1384 rtems_debugger_target_exception_to_signal(frame), 1347 1385 frame->vector, mvector, dbgdscr, arm_moe_label(moe), 1348 ifsr, (intptr_t) frame->register_pc); 1386 far, ifsr, dfsr, (intptr_t) frame->register_pc); 1387 1388 arm_debug_break_dump(); 1349 1389 1350 1390 frame->register_pc = (void*) ((intptr_t) frame->register_pc - exc_offset); … … 1352 1392 target_print_frame(frame); 1353 1393 1394 arm_debug_break_clear(0); 1354 1395 arm_debug_enable_interrupts(); 1355 arm_debug_break_clear();1356 1396 1357 1397 if (!debug_session_active) … … 1374 1414 (uint32_t) frame, (intptr_t) frame->register_pc, FRAME_SR(frame)); 1375 1415 target_print_frame(frame); 1376 arm_debug_break_dump(); 1377 } 1416 } 1417 1418 /** 1419 * Exception Handlers 1420 * 1421 * The entry and exit is all assembler and ARM code. This avoids any 1422 * compiler related optimisations effecting the various pieces. 1423 */ 1378 1424 1379 1425 /** … … 1409 1455 #define EXCEPTION_ENTRY_EXC() \ 1410 1456 __asm__ volatile( \ 1411 ASM_ARM_MODE 1457 ASM_ARM_MODE /* force ARM mode for thumb systems */ \ 1412 1458 "sub sp, %[frame_size]\n" /* alloc the frame and CPSR */ \ 1413 1459 "stm sp, {r0-r12}\n" /* store r0-r12 */ \ 1414 "sub sp, #4\n" \ 1415 "str lr, [sp]\n" /* save the link reg */ \ 1416 ASM_THUMB_MODE \ 1417 : ARM_SWITCH_REG_ASM \ 1460 : \ 1418 1461 : [frame_size] "i" (EXCEPTION_FRAME_SIZE) \ 1419 : "memory") 1462 : "cc", "memory") 1463 1464 /** 1465 * Debugger entry 1466 * 1467 * Check if using debug registers else use CP14. 1468 * 1469 * Set all the break point registers to 0. Enable interrupts. 1470 */ 1471 #if ARM_CP15 1472 #define ARM_HW_BP_UNLOAD(_bp) \ 1473 "cmp r0, #" #_bp "\n" \ 1474 "ble 3f\n" \ 1475 "mcr p14, 0, r1, c0, c" #_bp ", 5\n" \ 1476 "mcr p14, 0, r1, c0, c" #_bp ", 4\n" 1477 #define ARM_DGB_ENABLE_INTS \ 1478 "mrc p14, 0, r1, c0, c1, 0\n" /* Get the DBGDSCR */ \ 1479 "bic r1, r1, #(1 << 11)\n" /* enable interrupts */ \ 1480 "mcr p14, 0, r1, c0, c1, 0\n" /* Set the DBGDSCR */ 1481 #else 1482 #define ARM_HW_BP_UNLOAD(_bp) 1483 #define ARM_DGB_ENABLE_INTS 1484 #endif 1485 1486 #define EXCEPTION_ENTRY_DEBUGGER() \ 1487 __asm__ volatile( \ 1488 /* Set up r0 and r1 */ \ 1489 "movw r0, #:lower16:hw_breakpoints\n" /* get the num hw breaks */ \ 1490 "movt r0, #:upper16:hw_breakpoints\n" \ 1491 "ldr r0, [r0]\n" /* r0 = hw_breakpoints */ \ 1492 "mov r1, #0\n" /* write zero */ \ 1493 /* Check if debug registers are being used */ \ 1494 "movw r2, #:lower16:debug_registers\n" /* get the debug regs */ \ 1495 "movt r2, #:upper16:debug_registers\n" \ 1496 "ldr r2, [r2]\n" /* r2 = debug_registers */ \ 1497 "cmp r2, #0\n" /* NULL? */ \ 1498 "beq 2f\n" /* if NULL use cp14 */ \ 1499 /* Debug registers */ \ 1500 "add r3, r2, %[dbgbvr] - 4\n" /* a3 = DBGBCR0, adjusted */ \ 1501 "add r2, r2, %[dbgbcr] - 4\n" /* a2 = DBGBVR0, adjusted */ \ 1502 "1:\n" \ 1503 "str r1, [r3, #4]!\n" /* Store DBGBVR, pre-indexed, modified */ \ 1504 "str r1, [r2, #4]!\n" /* Store DBGBCR, pre-indexed, modified */ \ 1505 "sub r0, r0, #1\n" /* one less */ \ 1506 "cmp r0, #0\n" /* all done? */ \ 1507 "bne 1b\n" \ 1508 "ldr r1, [r2, %[dbgdscr]]\n" /* Get the DBGDSCR */ \ 1509 "bic r1, r1, #(1 << 11)\n" /* enable interrupts */ \ 1510 "str r1, [r2, %[dbgdscr]]\n" /* Set the DBGDSCR */ \ 1511 "b 4f\n" \ 1512 /* CP14 */ \ 1513 "2:\n" \ 1514 ARM_HW_BP_UNLOAD(0) \ 1515 ARM_HW_BP_UNLOAD(1) \ 1516 ARM_HW_BP_UNLOAD(2) \ 1517 ARM_HW_BP_UNLOAD(3) \ 1518 ARM_HW_BP_UNLOAD(4) \ 1519 ARM_HW_BP_UNLOAD(5) \ 1520 ARM_HW_BP_UNLOAD(6) \ 1521 ARM_HW_BP_UNLOAD(7) \ 1522 ARM_HW_BP_UNLOAD(8) \ 1523 ARM_HW_BP_UNLOAD(9) \ 1524 ARM_HW_BP_UNLOAD(10) \ 1525 ARM_HW_BP_UNLOAD(11) \ 1526 ARM_HW_BP_UNLOAD(12) \ 1527 ARM_HW_BP_UNLOAD(12) \ 1528 ARM_HW_BP_UNLOAD(13) \ 1529 ARM_HW_BP_UNLOAD(14) \ 1530 ARM_HW_BP_UNLOAD(15) \ 1531 "3:\n" \ 1532 ARM_DGB_ENABLE_INTS \ 1533 "4:\n" \ 1534 ARM_SYNC_INST \ 1535 : \ 1536 : [dbgdscr] "i" (ARM_MMAP_DBGDSCR * sizeof(uint32_t)), \ 1537 [dbgbcr] "i" (ARM_MMAP_DBGBCR * sizeof(uint32_t)), \ 1538 [dbgbvr] "i" (ARM_MMAP_DBGBVR * sizeof(uint32_t)) \ 1539 : "cc", "r0", "r1", "r2", "r3", "memory") 1420 1540 1421 1541 /* … … 1431 1551 "mov r4, #0\n" \ 1432 1552 "adds r6, r5, #128\n" \ 1433 " 3:\n" \1553 "1:\n" \ 1434 1554 "stmia r5!, {r3-r4}\n" \ 1435 1555 "cmp r5, r6\n" \ 1436 "bne 3b\n"1556 "bne 1b\n" 1437 1557 #endif /* ARM_MULTILIB_VFP_D32 */ 1438 1558 #define EXCEPTION_ENTRY_FPU(frame_fpu_size) \ … … 1454 1574 #define EXCEPTION_ENTRY_THREAD(_frame) \ 1455 1575 __asm__ volatile( \ 1456 ASM_ARM_MODE \1457 "ldr lr, [sp]\n" /* recover the link reg */ \1458 "add sp, #4\n" \1459 1576 "add r0, sp, %[r0_r12_size]\n" /* get the sp in the frame */ \ 1460 1577 "mrs r1, spsr\n" /* get the saved sr */ \ … … 1469 1586 "msr cpsr, r2\n" /* back to exc mode */ \ 1470 1587 "mov r5, lr\n" /* get the PRA */ \ 1471 "stm r0, {r3-r6}\n" /* save into the frame*/ \1588 "stm r0, {r3-r6}\n" /* save into the frame: sp,lr,pc,cpsr */ \ 1472 1589 "sub r4, r3, %[frame_size]\n" /* destination address */ \ 1473 1590 "mov r6, r4\n" /* save the frame */ \ … … 1492 1609 "bic r1, r1, %[psr_i]\n" /* clear irq mask, debug checks */ \ 1493 1610 "msr cpsr, r1\n" /* restore the state with irq mask clear */ \ 1494 ASM_THUMB_MODE \ 1495 : ARM_SWITCH_REG_ASM_L \ 1611 : \ 1496 1612 [o_frame] "=r" (_frame) \ 1497 1613 : [psr_t] "i" (ARM_PSR_T), \ … … 1502 1618 [o_frame_fpu] "i" (EXCEPTION_FRAME_FPU_OFFSET), \ 1503 1619 [frame_fpu_size] "i" (EXCEPTION_FRAME_FPU_SIZE + 4) \ 1504 : " r0", "r1", "r2", "r3", "r4", "r5", "r6", "memory")1620 : "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "memory") 1505 1621 1506 1622 /* … … 1538 1654 #define EXCEPTION_EXIT_THREAD(_frame) \ 1539 1655 __asm__ volatile( \ 1540 ASM_ARM_MODE \1541 1656 "mov r0, %[i_frame]\n" /* get the frame */ \ 1542 "ldr r0, [r0, %[frame_fpu]]\n" /* recover FPU frame pointer */ \1657 "ldr r0, [r0, %[frame_fpu]]\n" /* recover aligned FPU frame ptr */ \ 1543 1658 EXCEPTION_EXIT_FPU(frame_fpu_size) \ 1544 1659 "ldr r2, [sp, %[frame_cpsr]]\n" /* recover exc CPSR from thread */ \ … … 1563 1678 "msr cpsr, r2\n" /* switch back to the exc's context */ \ 1564 1679 "msr spsr, r6\n" /* set the thread's CPSR */ \ 1565 "sub sp, #4\n" \1566 1680 "mov lr, r5\n" /* get the PC */ \ 1567 "str lr, [sp]\n" /* save the link reg */ \ 1568 ASM_THUMB_MODE \ 1569 : ARM_SWITCH_REG_ASM \ 1681 : \ 1570 1682 : [psr_i] "i" (ARM_PSR_I), \ 1571 1683 [r0_r12_size] "i" (13 * sizeof(uint32_t)), \ … … 1575 1687 [frame_fpu_size] "i" (EXCEPTION_FRAME_FPU_SIZE + 4), \ 1576 1688 [i_frame] "r" (_frame) \ 1577 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "memory") 1689 : "cc", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "memory") 1690 1691 /* 1692 * Debugger exit 1693 * 1694 * Check if using debug registers else use CP14. 1695 * 1696 * Set all the break point registers to settgins. Disable interrupts 1697 * if debug_disable_ints is true. Clear debug_disable_ints. 1698 */ 1699 #if ARM_CP15 1700 #define ARM_HW_BP_LOAD(_bp) \ 1701 "cmp r0, #" #_bp "\n" \ 1702 "ble 5f\n" \ 1703 "ldm r1!, {r2-r3}\n" \ 1704 "mcr p14, 0, r2, c0, c" #_bp ", 4\n" /* value */ \ 1705 "mcr p14, 0, r3, c0, c" #_bp ", 5\n" /* control */ 1706 #define ARM_DGB_DISABLE_INTS \ 1707 "mrc p14, 0, r4, c0, c1, 0\n" /* Get the DBGDSCR */ \ 1708 "orr r4, r4, #(1 << 11)\n" /* disable interrupts */ \ 1709 "mcr p14, 0, r4, c0, c1, 0\n" /* Set the DBGDSCR */ 1710 #else 1711 #define ARM_HW_BP_LOAD(_bp) 1712 #define ARM_DGB_DISABLE_INTS 1713 #endif 1714 1715 #define EXCEPTION_EXIT_DEBUGGER() \ 1716 __asm__ volatile( \ 1717 /* Set up r0, r1, r4 and r5 */ \ 1718 "movw r0, #:lower16:hw_breakpoints\n" /* get the num hw breaks */ \ 1719 "movt r0, #:upper16:hw_breakpoints\n" \ 1720 "ldr r0, [r0]\n" /* r0 = hw_breakpoints */ \ 1721 "movw r1, #:lower16:hw_breaks\n" /* get the hw_breaks pointer */ \ 1722 "movt r1, #:upper16:hw_breaks\n" \ 1723 "movw r4, #:lower16:debug_disable_ints\n" /* get disable ints */ \ 1724 "movt r4, #:upper16:debug_disable_ints\n" \ 1725 "ldr r5, [r4]\n" \ 1726 "mov r3, #0\n" /* clear debug ints */ \ 1727 "str r3, [r4]\n" \ 1728 /* Check if debug registers are being used */ \ 1729 "movw r2, #:lower16:debug_registers\n" /* get the debug regs */ \ 1730 "movt r2, #:upper16:debug_registers\n" \ 1731 "ldr r2, [r2]\n" /* r2 = debug_registers */ \ 1732 "cmp r2, #0\n" /* NULL? */ \ 1733 "beq 3f\n" /* if NULL use cp14 */ \ 1734 /* Debug registers */ \ 1735 "cmp r5, #0\n" /* false? */ \ 1736 "beq 1f\n" /* if false do not set ints disable */ \ 1737 "ldr r4, [r2, %[dbgdscr]]\n" /* Get the DBGDSCR */ \ 1738 "orr r4, r4, #(1 << 11)\n" /* disable interrupts */ \ 1739 "str r4, [r2, %[dbgdscr]]\n" /* Set the DBGDSCR */ \ 1740 "1:\n" \ 1741 "add r3, r2, %[dbgbvr] - 4\n" /* a3 = DBGBCR0, adjusted */ \ 1742 "add r2, r2, %[dbgbcr] - 4\n" /* a2 = DBGBVR0, adjusted */ \ 1743 "2:\n" \ 1744 "ldm r1!, {r4-r5}\n" /* load vr and cr */ \ 1745 "str r4, [r3, #4]!\n" /* Store DBGBVR, pre-indexed, modified */ \ 1746 "str r5, [r2, #4]!\n" /* Store DBGBCR, pre-indexed, modified */ \ 1747 "sub r0, r0, #1\n" /* one less? */ \ 1748 "cmp r0, #1\n" /* all done? */ \ 1749 "bne 2b\n" \ 1750 "b 5f\n" \ 1751 /* CP14 */ \ 1752 "3:\n" \ 1753 "cmp r5, #0\n" /* false? */ \ 1754 "beq 4f\n" /* if false do not set ints disable */ \ 1755 ARM_DGB_DISABLE_INTS \ 1756 "4:\n" \ 1757 ARM_HW_BP_LOAD(0) \ 1758 ARM_HW_BP_LOAD(1) \ 1759 ARM_HW_BP_LOAD(2) \ 1760 ARM_HW_BP_LOAD(3) \ 1761 ARM_HW_BP_LOAD(4) \ 1762 ARM_HW_BP_LOAD(5) \ 1763 ARM_HW_BP_LOAD(6) \ 1764 ARM_HW_BP_LOAD(7) \ 1765 ARM_HW_BP_LOAD(8) \ 1766 ARM_HW_BP_LOAD(9) \ 1767 ARM_HW_BP_LOAD(10) \ 1768 ARM_HW_BP_LOAD(11) \ 1769 ARM_HW_BP_LOAD(12) \ 1770 ARM_HW_BP_LOAD(13) \ 1771 ARM_HW_BP_LOAD(14) \ 1772 ARM_HW_BP_LOAD(15) \ 1773 "5:\n" \ 1774 ARM_SYNC_INST \ 1775 : \ 1776 : [disints] "X" (debug_disable_ints), /* make the sym available */ \ 1777 [dbgdscr] "i" (ARM_MMAP_DBGDSCR * sizeof(uint32_t)), \ 1778 [dbgbcr] "i" (ARM_MMAP_DBGBCR * sizeof(uint32_t)), \ 1779 [dbgbvr] "i" (ARM_MMAP_DBGBVR * sizeof(uint32_t)) \ 1780 : "cc", "r0", "r1", "r2", "r3", "r4", "r5", "memory") 1578 1781 1579 1782 #define EXCEPTION_EXIT_EXC() \ 1580 1783 __asm__ volatile( \ 1581 ASM_ARM_MODE \1582 "ldr lr, [sp]\n" /* recover the link reg */ \1583 "add sp, #4\n" \1584 1784 "ldm sp, {r0-r12}\n" /* restore the thread's context */ \ 1585 1785 "add sp, %[frame_size]\n" /* free the frame */ \ 1586 1786 "subs pc, lr, #0\n" /* return from the exc */ \ 1787 ARM_SYNC_INST \ 1587 1788 : \ 1588 1789 : [frame_size] "i" (EXCEPTION_FRAME_SIZE) \ 1589 : "memory") 1790 : "cc", "memory") 1791 1792 #define ARM_PUSH_LR() \ 1793 __asm__ volatile( \ 1794 "push {lr}\n" \ 1795 : : : ) 1796 1797 #define ARM_POP_LR() \ 1798 __asm__ volatile( \ 1799 "pop {lr}\n" \ 1800 : : : ) 1801 1802 /* 1803 * Entry and exit stacks 1804 */ 1805 #define EXCEPTION_ENTRY(_frame) \ 1806 EXCEPTION_ENTRY_EXC(); \ 1807 EXCEPTION_ENTRY_DEBUGGER(); \ 1808 EXCEPTION_ENTRY_THREAD(_frame); \ 1809 ARM_THUMB_MODE() \ 1810 ARM_PUSH_LR() 1811 1812 #define EXCEPTION_EXIT(_frame) \ 1813 ARM_POP_LR(); \ 1814 ARM_ARM_MODE(); \ 1815 EXCEPTION_EXIT_THREAD(_frame); \ 1816 EXCEPTION_EXIT_DEBUGGER(); \ 1817 EXCEPTION_EXIT_EXC() 1590 1818 1591 1819 /* … … 1597 1825 { 1598 1826 CPU_Exception_frame* frame; 1599 ARM_SWITCH_REG ;1827 ARM_SWITCH_REGISTERS; 1600 1828 EXCEPTION_ENTRY_EXC(); 1601 1829 EXCEPTION_ENTRY_THREAD(frame); 1830 ARM_SWITCH_BACK; 1602 1831 longjmp(unlock_abort_jmpbuf, -1); 1603 1832 } … … 1609 1838 CPU_Exception_frame* frame; 1610 1839 ARM_SWITCH_REG; 1611 EXCEPTION_ENTRY_EXC(); 1612 arm_debug_break_unload(); 1613 arm_debug_enable_interrupts(); 1614 EXCEPTION_ENTRY_THREAD(frame); 1840 EXCEPTION_ENTRY(frame); 1615 1841 frame->vector = 1; 1616 1842 target_exception(frame); 1617 EXCEPTION_EXIT_THREAD(frame); 1618 arm_debug_commit_interrupt_disable(); 1619 arm_debug_break_load(); 1620 EXCEPTION_EXIT_EXC(); 1843 EXCEPTION_EXIT(frame); 1621 1844 } 1622 1845 … … 1632 1855 * handler to signal a TRAP. 1633 1856 */ 1634 EXCEPTION_ENTRY_EXC(); 1635 arm_debug_break_unload(); 1636 arm_debug_enable_interrupts(); 1637 EXCEPTION_ENTRY_THREAD(frame); 1857 EXCEPTION_ENTRY(frame); 1638 1858 frame->vector = 2; 1639 1859 target_exception(frame); 1640 EXCEPTION_EXIT_THREAD(frame); 1641 arm_debug_commit_interrupt_disable(); 1642 arm_debug_break_load(); 1643 EXCEPTION_EXIT_EXC(); 1860 EXCEPTION_EXIT(frame); 1644 1861 } 1645 1862 … … 1649 1866 CPU_Exception_frame* frame; 1650 1867 ARM_SWITCH_REG; 1651 EXCEPTION_ENTRY_EXC(); 1652 arm_debug_break_unload(); 1653 arm_debug_enable_interrupts(); 1654 EXCEPTION_ENTRY_THREAD(frame); 1868 EXCEPTION_ENTRY(frame); 1655 1869 frame->vector = 3; 1656 1870 target_exception(frame); 1657 EXCEPTION_EXIT_THREAD(frame); 1658 arm_debug_commit_interrupt_disable(); 1659 arm_debug_break_load(); 1660 EXCEPTION_EXIT_EXC(); 1871 EXCEPTION_EXIT(frame); 1661 1872 } 1662 1873 … … 1666 1877 CPU_Exception_frame* frame; 1667 1878 ARM_SWITCH_REG; 1668 EXCEPTION_ENTRY_EXC(); 1669 arm_debug_break_unload(); 1670 arm_debug_enable_interrupts(); 1671 EXCEPTION_ENTRY_THREAD(frame); 1879 EXCEPTION_ENTRY(frame); 1672 1880 frame->vector = 4; 1673 1881 target_exception(frame); 1674 EXCEPTION_EXIT_THREAD(frame); 1675 arm_debug_commit_interrupt_disable(); 1676 arm_debug_break_load(); 1677 EXCEPTION_EXIT_EXC(); 1882 EXCEPTION_EXIT(frame); 1678 1883 } 1679 1884 … … 1777 1982 { 1778 1983 rtems_interrupt_lock_context lock_context; 1779 debug_session_active = true;1780 1984 arm_debug_break_unload(); 1781 arm_debug_break_clear ();1985 arm_debug_break_clear_all(); 1782 1986 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 1783 1987 rtems_debugger_target_set_mmu(); 1784 1988 rtems_debugger_target_set_vectors(); 1785 1989 rtems_interrupt_lock_release(&target_lock, &lock_context); 1990 debug_session_active = true; 1786 1991 return 0; 1787 1992 } … … 1796 2001 #endif 1797 2002 arm_debug_break_unload(); 1798 arm_debug_break_clear ();2003 arm_debug_break_clear_all(); 1799 2004 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 2005 debug_disable_ints = 0; 1800 2006 debug_session_active = false; 1801 2007 #if DOES_NOT_WORK … … 1980 2186 */ 1981 2187 CPU_Exception_frame* frame = thread->frame; 1982 arm_debug_hwbreak* bp = &hw_breaks[0]; 1983 1984 target_printk("[} stepping: %s\n", bp->enabled ? "yes" : "no"); 1985 1986 if (!bp->enabled) { 2188 2189 target_printk("[} stepping: hbp[0] enabled: %s\n", ARM_HWB_ENALBED(0) ? "yes" : "no"); 2190 2191 if (!ARM_HWB_ENALBED(0)) { 1987 2192 const uint32_t addr = (intptr_t) frame->register_pc; 1988 2193 const bool thumb = (FRAME_SR(frame) & (1 << 5)) != 0 ? true : false; 1989 uint32_t bas; 1990 1991 bp->enabled = true; 1992 bp->loaded = false; 1993 bp->address = frame->register_pc; 1994 bp->frame = frame; 1995 bp->length = sizeof(uint32_t); 1996 1997 if (thumb) { 1998 uint16_t instr = *((uint16_t*) frame->register_pc); 1999 switch (instr & 0xf800) { 2000 case 0xe800: 2001 case 0xf000: 2002 case 0xf800: 2003 break; 2004 default: 2005 bp->length = sizeof(uint16_t); 2006 break; 2007 } 2008 } 2009 2010 /* 2011 * See table C3-2 Effect of byte address selection on Breakpoint 2012 * generation and "Instruction address comparision programming 2013 * examples. 2014 */ 2015 if (thumb) { 2016 if ((addr & (1 << 1)) == 0) { 2017 bas = 0x3; /* b0011 */ 2018 } 2019 else { 2020 bas = 0xc; /* b1100 */ 2021 } 2022 } 2023 else { 2024 bas = 0xf; /* b1111 */ 2025 } 2026 2027 arm_debug_break_setup(bp, 2028 addr & ~0x3, 2029 ARM_HW_BP_UNLINKED_INSTR_MISMATCH, 2030 bas, 2031 ARM_HW_BP_PRIV_PL0_SUP_SYS); 2032 2194 arm_debug_break_exec_enable(0, addr, thumb, true); 2033 2195 arm_debug_disable_interrupts(); 2034 2196 } … … 2086 2248 rtems_debugger_target_hwbreak_remove(void) 2087 2249 { 2250 target_printk("[} hbreak: remove: unload\n"); 2088 2251 arm_debug_break_unload(); 2089 2252 return 0; … … 2096 2259 DB_UINT kind) 2097 2260 { 2098 /* 2099 * To do. 2100 */ 2261 rtems_interrupt_lock_context lock_context; 2262 int i; 2263 if (wp != rtems_debugger_target_hw_execute) { 2264 errno = EIO; 2265 return -1; 2266 } 2267 rtems_interrupt_lock_acquire(&target_lock, &lock_context); 2268 for (i = 1; i < hw_breakpoints; ++i) { 2269 if (insert && !ARM_HWB_ENALBED(i)) { 2270 arm_debug_break_exec_enable(i, addr, kind == 1, false); 2271 break; 2272 } else if (!insert && ARM_HWB_ENALBED(i) && ARM_HWB_VCR(i) == (addr & ~3)) { 2273 arm_debug_break_clear(i); 2274 break; 2275 } 2276 } 2277 rtems_interrupt_lock_release(&target_lock, &lock_context); 2278 if (!insert && i == hw_breakpoints) { 2279 errno = EIO; 2280 return -1; 2281 } 2101 2282 return 0; 2102 2283 } … … 2105 2286 rtems_debugger_target_cache_sync(rtems_debugger_target_swbreak* swbreak) 2106 2287 { 2288 target_printk("[} cache: sync: %p\n", swbreak->address); 2107 2289 /* 2108 2290 * Flush the data cache and invalidate the instruction cache.
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