Changeset 18a5db2 in rtems


Ignore:
Timestamp:
Feb 3, 2016, 10:48:31 AM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
c6009340
Parents:
d638aca
git-author:
Sebastian Huber <sebastian.huber@…> (02/03/16 10:48:31)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/17/16 08:15:01)
Message:

m68k: Avoid SCORE_EXTERN

Update #2559.

Location:
cpukit/score/cpu/m68k
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/m68k/cpu.c

    rd638aca r18a5db2  
    2121#include <rtems/score/percpu.h>
    2222#include <rtems/score/tls.h>
     23
     24#if ( M68K_HAS_VBR == 0 )
     25
     26/*
     27 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
     28 * pushed onto the stack. This is not is the same order as VBR processors.
     29 * The ISR handler takes the format and uses it for dispatching the user
     30 * handler.
     31 */
     32
     33typedef struct {
     34  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
     35  uint16_t   format_id;
     36  uint16_t   jmp;                /* jmp  _ISR_Handlers */
     37  uint32_t   isr_handler;
     38} _CPU_ISR_handler_entry;
     39
     40#define M68K_MOVE_A7 0x3F3C
     41#define M68K_JMP     0x4EF9
     42
     43/* points to jsr-exception-table in targets wo/ VBR register */
     44static _CPU_ISR_handler_entry
     45_CPU_ISR_jump_table[ CPU_INTERRUPT_NUMBER_OF_VECTORS ];
     46
     47#endif /* M68K_HAS_VBR */
     48
     49#if (M68K_HAS_FPSP_PACKAGE == 1)
     50int (*_FPSP_install_raw_handler)(
     51  uint32_t   vector,
     52  proc_ptr new_handler,
     53  proc_ptr *old_handler
     54);
     55#endif
    2356
    2457#if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
  • cpukit/score/cpu/m68k/rtems/score/cpu.h

    rd638aca r18a5db2  
    313313
    314314extern void*                     _VBR;
    315 
    316 #if ( M68K_HAS_VBR == 0 )
    317 
    318 /*
    319  * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
    320  * pushed onto the stack. This is not is the same order as VBR processors.
    321  * The ISR handler takes the format and uses it for dispatching the user
    322  * handler.
    323  *
    324  * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
    325  *
    326  */
    327 
    328 typedef struct {
    329   uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
    330   uint16_t   format_id;
    331   uint16_t   jmp;                /* jmp  _ISR_Handlers */
    332   uint32_t   isr_handler;
    333 } _CPU_ISR_handler_entry;
    334 
    335 #define M68K_MOVE_A7 0x3F3C
    336 #define M68K_JMP     0x4EF9
    337 
    338       /* points to jsr-exception-table in targets wo/ VBR register */
    339 SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
    340 
    341 #endif /* M68K_HAS_VBR */
    342315
    343316#endif /* ASM */
     
    765738void M68KFPSPInstallExceptionHandlers (void);
    766739
    767 SCORE_EXTERN int (*_FPSP_install_raw_handler)(
     740extern int (*_FPSP_install_raw_handler)(
    768741  uint32_t   vector,
    769742  proc_ptr new_handler,
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