Changeset 176e1ed8 in rtems for cpukit/score/cpu/mips/cpu_asm.S

Timestamp:

04/20/01 13:07:34 (22 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, 5, master

Children:

831aba1

Parents:

4ff04390

Message:

2001-04-20 Joel Sherrill <joel@…>

• cpu_asm.S: Added code to save and restore SR and EPC to properly support nested interrupts. Note that the ISR (not RTEMS) enables interrupts allowing the nesting to occur.

File:

• cpukit/score/cpu/mips/cpu_asm.S (modified) (3 diffs)

cpukit/score/cpu/mips/cpu_asm.S

@@ -427 +427 @@
         ADDIU    sp,sp,-40
         STREG    ra,32(sp)                /* store ra on the stack */
+        MFC0     t0, C0_EPC               /* XXX */
+        STREG    t0,16(sp)                /* XXX store EPC on the stack */
+        mfc0     t0,C0_SR
+        STREG    t0,24(sp)                /* XXX store SR on the stack */
 
 /* determine if an interrupt generated this exception */
@@ -530 +534 @@
 _ISR_Handler_exit:
         LDREG    ra,32(sp)
+        LDREG    t0,16(sp)                /* XXX restore EPC on the stack */
+        MTC0     t0, C0_EPC               /* XXX */
+        LDREG    t0,24(sp)                /* XXX restore SR on the stack */
+        mtc0     t0,C0_SR
         ADDIU    sp,sp,40    /* Q: Again with the 40...Is this needed? */
 
@@ -564 +572 @@
 
         MFC0      k0, C0_EPC
+        nop
         
         rfe  /* Might not need to do RFE here... */