Ignore:
Timestamp:
Apr 20, 2001, 1:07:34 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
831aba1
Parents:
4ff04390
Message:

2001-04-20 Joel Sherrill <joel@…>

  • cpu_asm.S: Added code to save and restore SR and EPC to properly support nested interrupts. Note that the ISR (not RTEMS) enables interrupts allowing the nesting to occur.
File:
1 edited

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  • c/src/exec/score/cpu/mips/ChangeLog

    r4ff04390 r176e1ed8  
     12001-04-20      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu_asm.S: Added code to save and restore SR and EPC to
     4        properly support nested interrupts.  Note that the ISR
     5        (not RTEMS) enables interrupts allowing the nesting to occur.
     6
    172001-03-14      Joel Sherrill <joel@OARcorp.com>
    28
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