Changeset 176e1ed8 in rtems


Ignore:
Timestamp:
Apr 20, 2001, 1:07:34 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
831aba1
Parents:
4ff04390
Message:

2001-04-20 Joel Sherrill <joel@…>

  • cpu_asm.S: Added code to save and restore SR and EPC to properly support nested interrupts. Note that the ISR (not RTEMS) enables interrupts allowing the nesting to occur.
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/mips/ChangeLog

    r4ff04390 r176e1ed8  
     12001-04-20      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu_asm.S: Added code to save and restore SR and EPC to
     4        properly support nested interrupts.  Note that the ISR
     5        (not RTEMS) enables interrupts allowing the nesting to occur.
     6
    172001-03-14      Joel Sherrill <joel@OARcorp.com>
    28
  • c/src/exec/score/cpu/mips/cpu_asm.S

    r4ff04390 r176e1ed8  
    427427        ADDIU    sp,sp,-40
    428428        STREG    ra,32(sp)                /* store ra on the stack */
     429        MFC0     t0, C0_EPC               /* XXX */
     430        STREG    t0,16(sp)                /* XXX store EPC on the stack */
     431        mfc0     t0,C0_SR
     432        STREG    t0,24(sp)                /* XXX store SR on the stack */
    429433
    430434/* determine if an interrupt generated this exception */
     
    530534_ISR_Handler_exit:
    531535        LDREG    ra,32(sp)
     536        LDREG    t0,16(sp)                /* XXX restore EPC on the stack */
     537        MTC0     t0, C0_EPC               /* XXX */
     538        LDREG    t0,24(sp)                /* XXX restore SR on the stack */
     539        mtc0     t0,C0_SR
    532540        ADDIU    sp,sp,40    /* Q: Again with the 40...Is this needed? */
    533541
     
    564572
    565573        MFC0      k0, C0_EPC
     574        nop
    566575       
    567576        rfe  /* Might not need to do RFE here... */
  • cpukit/score/cpu/mips/ChangeLog

    r4ff04390 r176e1ed8  
     12001-04-20      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu_asm.S: Added code to save and restore SR and EPC to
     4        properly support nested interrupts.  Note that the ISR
     5        (not RTEMS) enables interrupts allowing the nesting to occur.
     6
    172001-03-14      Joel Sherrill <joel@OARcorp.com>
    28
  • cpukit/score/cpu/mips/cpu_asm.S

    r4ff04390 r176e1ed8  
    427427        ADDIU    sp,sp,-40
    428428        STREG    ra,32(sp)                /* store ra on the stack */
     429        MFC0     t0, C0_EPC               /* XXX */
     430        STREG    t0,16(sp)                /* XXX store EPC on the stack */
     431        mfc0     t0,C0_SR
     432        STREG    t0,24(sp)                /* XXX store SR on the stack */
    429433
    430434/* determine if an interrupt generated this exception */
     
    530534_ISR_Handler_exit:
    531535        LDREG    ra,32(sp)
     536        LDREG    t0,16(sp)                /* XXX restore EPC on the stack */
     537        MTC0     t0, C0_EPC               /* XXX */
     538        LDREG    t0,24(sp)                /* XXX restore SR on the stack */
     539        mtc0     t0,C0_SR
    532540        ADDIU    sp,sp,40    /* Q: Again with the 40...Is this needed? */
    533541
     
    564572
    565573        MFC0      k0, C0_EPC
     574        nop
    566575       
    567576        rfe  /* Might not need to do RFE here... */
Note: See TracChangeset for help on using the changeset viewer.