Changeset 173c59c8 in rtems
- Timestamp:
- 01/23/98 16:57:29 (25 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- bd620fe
- Parents:
- 1d012410
- Location:
- doc
- Files:
-
- 20 edited
Legend:
- Unmodified
- Added
- Removed
-
doc/Make.config
r1d012410 r173c59c8 12 12 GHOSTVIEW=ghostview -magstep -1 13 13 14 DOC_INSTALL_BASE=/usr1/tmp/rtemsdoc-970 80414 DOC_INSTALL_BASE=/usr1/tmp/rtemsdoc-970904 15 15 16 16 WWW_INSTALL=$(DOC_INSTALL_BASE)/html -
doc/ada_user/ada_user.texi
r1d012410 r173c59c8 54 54 @c 55 55 56 @set edition 4.2.0-beta1 57 @set update-date 1 June 1997 58 @set update-month June 1997 56 @set edition 970904 57 @set version 970904 58 @set update-date 4 September 1997 59 @set update-month September 1997 59 60 60 61 @c … … 69 70 70 71 @title RTEMS Applications Ada User's Guide 71 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease72 @subtitle Edition @value{edition}, for RTEMS @value{version} 72 73 @sp 1 73 74 @subtitle @value{update-month} -
doc/develenv/develenv.texi
r1d012410 r173c59c8 49 49 @c 50 50 51 @set edition 4.2.0-beta1 52 @set update-date 1 June 1997 53 @set update-month June 1997 51 @set edition 970904 52 @set version 970904 53 @set update-date 4 September 1997 54 @set update-month September 1997 54 55 55 56 @c … … 64 65 65 66 @title RTEMS Development Environment Guide 66 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease67 @subtitle Edition @value{edition}, for RTEMS @value{version} 67 68 @sp 1 68 69 @subtitle @value{update-month} -
doc/new_chapters/clock.texi
r1d012410 r173c59c8 245 245 @subsection nanosleep 246 246 247 @subheading timeSEQUENCE:247 @subheading CALLING SEQUENCE: 248 248 249 249 @example -
doc/new_chapters/posix_test_plan.texi
r1d012410 r173c59c8 49 49 @c 50 50 51 @set edition 4.2.0-beta152 @set update-date 1 June 199753 @set update- month June199754 51 @set edition 970904 52 @set version 970904 53 @set update-date 4 September 1997 54 @set update-month September 1997 55 55 @c 56 56 @c I don't really like having a short title page. --joel … … 64 64 65 65 @title RTEMS POSIX API Test Plan 66 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease66 @subtitle Edition @value{edition}, for RTEMS @value{version} 67 67 @sp 1 68 68 @subtitle @value{update-month} -
doc/posix_users/clock.texi
r1d012410 r173c59c8 245 245 @subsection nanosleep 246 246 247 @subheading timeSEQUENCE:247 @subheading CALLING SEQUENCE: 248 248 249 249 @example -
doc/posix_users/posix_test_plan.texi
r1d012410 r173c59c8 49 49 @c 50 50 51 @set edition 4.2.0-beta152 @set update-date 1 June 199753 @set update- month June199754 51 @set edition 970904 52 @set version 970904 53 @set update-date 4 September 1997 54 @set update-month September 1997 55 55 @c 56 56 @c I don't really like having a short title page. --joel … … 64 64 65 65 @title RTEMS POSIX API Test Plan 66 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease66 @subtitle Edition @value{edition}, for RTEMS @value{version} 67 67 @sp 1 68 68 @subtitle @value{update-month} -
doc/relnotes/relnotes.texi
r1d012410 r173c59c8 49 49 @c 50 50 51 @set edition 4.2.0-beta1 52 @set update-date 1 June 1997 53 @set update-month June 1997 51 @set edition 970904 52 @set version 970904 53 @set update-date 4 September 1997 54 @set update-month September 1997 54 55 55 56 @c … … 64 65 65 66 @title RTEMS Release Notes 66 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease67 @subtitle Edition @value{edition}, for RTEMS @value{version} 67 68 @sp 1 68 69 @subtitle @value{update-month} -
doc/supplements/hppa1_1/hppa1_1.texi
r1d012410 r173c59c8 36 36 @c 37 37 38 @set edition 4.2.0-beta1 39 @set update-date 1 June 1997 40 @set update-month June 1997 38 @set edition 970904 39 @set version 970904 40 @set update-date 4 September 1997 41 @set update-month September 1997 41 42 42 43 @c … … 51 52 52 53 @title RTEMS Hewlett Packard PA-RISC Applications Supplement 53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease54 @subtitle Edition @value{edition}, for RTEMS @value{version} 54 55 @sp 1 55 56 @subtitle @value{update-month} -
doc/supplements/i386/i386.texi
r1d012410 r173c59c8 1 @c2 @c COPYRIGHT (c) 1988-1997.3 @c On-Line Applications Research Corporation (OAR).4 @c All rights reserved.5 @c6 @c $Id$7 @c8 9 1 \input ../texinfo/texinfo @c -*-texinfo-*- 10 2 @c %**start of header … … 44 36 @c 45 37 46 @set edition 4.2.0-beta1 47 @set update-date 1 June 1997 48 @set update-month June 1997 38 @set edition 970904 39 @set version 970904 40 @set update-date 4 September 1997 41 @set update-month September 1997 49 42 50 43 @c … … 59 52 60 53 @title RTEMS Intel i386 Applications Supplement 61 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease54 @subtitle Edition @value{edition}, for RTEMS @value{version} 62 55 @sp 1 63 56 @subtitle @value{update-month} -
doc/supplements/i960/i960.texi
r1d012410 r173c59c8 36 36 @c 37 37 38 @set edition 4.2.0-beta1 39 @set update-date 1 June 1997 40 @set update-month June 1997 38 @set edition 970904 39 @set version 970904 40 @set update-date 4 September 1997 41 @set update-month September 1997 41 42 42 43 @c … … 51 52 52 53 @title RTEMS Intel i960 Applications Supplement 53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease54 @subtitle Edition @value{edition}, for RTEMS @value{version} 54 55 @sp 1 55 56 @subtitle @value{update-month} -
doc/supplements/m68k/m68k.texi
r1d012410 r173c59c8 36 36 @c 37 37 38 @set edition 4.2.0-beta1 39 @set update-date 1 June 1997 40 @set update-month June 1997 38 @set edition 970904 39 @set version 970904 40 @set update-date 4 September 1997 41 @set update-month September 1997 41 42 42 43 @c … … 51 52 52 53 @title RTEMS Motorola MC68xxx Applications Supplement 53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease54 @subtitle Edition @value{edition}, for RTEMS @value{version} 54 55 @sp 1 55 56 @subtitle @value{update-month} -
doc/supplements/powerpc/bsp.t
r1d012410 r173c59c8 88 88 89 89 @itemize @bullet 90 @item Must leave the PR bit of the machine state 90 @item Must leave the PR bit of the machine state register set so that 91 91 the PowerPC remains in the supervisor state. 92 92 -
doc/supplements/powerpc/bsp.texi
r1d012410 r173c59c8 88 88 89 89 @itemize @bullet 90 @item Must leave the PR bit of the machine state 90 @item Must leave the PR bit of the machine state register set so that 91 91 the PowerPC remains in the supervisor state. 92 92 -
doc/supplements/powerpc/callconv.t
r1d012410 r173c59c8 154 154 @subsection Floating Point Registers 155 155 156 The SPARC V7 architecture includes thirty-two, 157 thirty-two bit registers. These registers may be viewed as 158 follows: 159 160 @itemize @bullet 161 @item 32 single precision floating point or integer registers 162 (f0, f1, ... f31) 163 164 @item 16 double precision floating point registers (f0, f2, 165 f4, ... f30) 166 167 @item 8 extended precision floating point registers (f0, f4, 168 f8, ... f28) 169 @end itemize 170 171 The floating point status register (fpsr) specifies 172 the behavior of the floating point unit for rounding, contains 173 its condition codes, version specification, and trap information. 174 156 The PowerPC architecture includes thirty-two, 157 sixty-four bit registers. All PowwerPC floating point instructions 158 interprete these registers as 32 double precision floating point registers, 159 regardless of whether the processor has 64-bit or 32-bit implementation. 160 161 The floating point status and control register (fpscr) records exceptions 162 and the type of result generated by floating-point operations. 163 Additionally, it controls the rounding mode of operations and allows the 164 reporting of floating exceptions to be enabled or disabled. 165 166 XXXXXX 175 167 A queue of the floating point instructions which have 176 168 started execution but not yet completed is maintained. This … … 184 176 handlers with the store double floating point queue (stdfq) 185 177 instruction. 178 XXX 186 179 187 180 @ifinfo … … 190 183 @subsection Special Registers 191 184 192 The SPARC architecture includes two special registers 193 which are critical to the programming model: the Processor State 194 Register (psr) and the Window Invalid Mask (wim). The psr 195 contains the condition codes, processor interrupt level, trap 185 The PowerPC architecture includes XXX special registers 186 which are critical to the programming model: the Machine State 187 Register (msr) and XXX the Window Invalid Mask (wim) XXX. The msr 188 contains the processor mode, power management mode, endian mode, exception 189 information, privlige level, floating point available and floating point 190 excepiton mode, address translation information and the exception prefix. 191 192 XXX 193 condition codes, processor interrupt level, trap 196 194 enable bit, supervisor mode and previous supervisor mode bits, 197 195 version information, floating point unit and coprocessor enable … … 200 198 in the SPARC architecture. The register windows are discussed 201 199 in more detail below. 200 XXX 202 201 203 202 @ifinfo … … 370 369 adhere to these calling conventions. 371 370 371 372 -
doc/supplements/powerpc/callconv.texi
r1d012410 r173c59c8 154 154 @subsection Floating Point Registers 155 155 156 The SPARC V7 architecture includes thirty-two, 157 thirty-two bit registers. These registers may be viewed as 158 follows: 159 160 @itemize @bullet 161 @item 32 single precision floating point or integer registers 162 (f0, f1, ... f31) 163 164 @item 16 double precision floating point registers (f0, f2, 165 f4, ... f30) 166 167 @item 8 extended precision floating point registers (f0, f4, 168 f8, ... f28) 169 @end itemize 170 171 The floating point status register (fpsr) specifies 172 the behavior of the floating point unit for rounding, contains 173 its condition codes, version specification, and trap information. 174 156 The PowerPC architecture includes thirty-two, 157 sixty-four bit registers. All PowwerPC floating point instructions 158 interprete these registers as 32 double precision floating point registers, 159 regardless of whether the processor has 64-bit or 32-bit implementation. 160 161 The floating point status and control register (fpscr) records exceptions 162 and the type of result generated by floating-point operations. 163 Additionally, it controls the rounding mode of operations and allows the 164 reporting of floating exceptions to be enabled or disabled. 165 166 XXXXXX 175 167 A queue of the floating point instructions which have 176 168 started execution but not yet completed is maintained. This … … 184 176 handlers with the store double floating point queue (stdfq) 185 177 instruction. 178 XXX 186 179 187 180 @ifinfo … … 190 183 @subsection Special Registers 191 184 192 The SPARC architecture includes two special registers 193 which are critical to the programming model: the Processor State 194 Register (psr) and the Window Invalid Mask (wim). The psr 195 contains the condition codes, processor interrupt level, trap 185 The PowerPC architecture includes XXX special registers 186 which are critical to the programming model: the Machine State 187 Register (msr) and XXX the Window Invalid Mask (wim) XXX. The msr 188 contains the processor mode, power management mode, endian mode, exception 189 information, privlige level, floating point available and floating point 190 excepiton mode, address translation information and the exception prefix. 191 192 XXX 193 condition codes, processor interrupt level, trap 196 194 enable bit, supervisor mode and previous supervisor mode bits, 197 195 version information, floating point unit and coprocessor enable … … 200 198 in the SPARC architecture. The register windows are discussed 201 199 in more detail below. 200 XXX 202 201 203 202 @ifinfo … … 370 369 adhere to these calling conventions. 371 370 371 372 -
doc/supplements/powerpc/powerpc.texi
r1d012410 r173c59c8 36 36 @c 37 37 38 @set edition 4.2.0-beta1 39 @set update-date 1 June 1997 40 @set update-month June 1997 38 @set edition 970904 39 @set version 970904 40 @set update-date 4 September 1997 41 @set update-month September 1997 41 42 42 43 @c … … 51 52 52 53 @title RTEMS PowerPC Applications Supplement 53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease54 @subtitle Edition @value{edition}, for RTEMS @value{version} 54 55 @sp 1 55 56 @subtitle @value{update-month} -
doc/supplements/sparc/sparc.texi
r1d012410 r173c59c8 36 36 @c 37 37 38 @set edition 4.2.0-beta1 39 @set update-date 1 June 1997 40 @set update-month June 1997 38 @set edition 970904 39 @set version 970904 40 @set update-date 4 September 1997 41 @set update-month September 1997 41 42 42 43 @c … … 51 52 52 53 @title RTEMS SPARC Applications Supplement 53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease54 @subtitle Edition @value{edition}, for RTEMS @value{version} 54 55 @sp 1 55 56 @subtitle @value{update-month} -
doc/user/c_user.texi
r1d012410 r173c59c8 54 54 @c 55 55 56 @set edition 4.2.0-beta1 57 @set update-date 1 June 1997 58 @set update-month June 1997 56 @set edition 970904 57 @set version 970904 58 @set update-date 4 September 1997 59 @set update-month September 1997 59 60 60 61 @c … … 69 70 70 71 @title RTEMS C User's Guide 71 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease72 @subtitle Edition @value{edition}, for RTEMS @value{version} 72 73 @sp 1 73 74 @subtitle @value{update-month} -
doc/user/intr.t
r1d012410 r173c59c8 316 316 @code{SUCCESSFUL} - ISR established successfully@* 317 317 @code{INVALID_NUMBER} - illegal vector number@* 318 @code{INVALID_ADDRESS} - illegal ISR entry point 318 @code{INVALID_ADDRESS} - illegal ISR entry point or invalid old_isr_handler 319 319 320 320 @subheading DESCRIPTION:
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