Changeset 173c59c8 in rtems


Ignore:
Timestamp:
Jan 23, 1998, 4:57:29 PM (23 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
bd620fe
Parents:
1d012410
Message:

minor updates .. mostly version

Location:
doc
Files:
20 edited

Legend:

Unmodified
Added
Removed
  • doc/Make.config

    r1d012410 r173c59c8  
    1212GHOSTVIEW=ghostview -magstep -1
    1313
    14 DOC_INSTALL_BASE=/usr1/tmp/rtemsdoc-970804
     14DOC_INSTALL_BASE=/usr1/tmp/rtemsdoc-970904
    1515
    1616WWW_INSTALL=$(DOC_INSTALL_BASE)/html
  • doc/ada_user/ada_user.texi

    r1d012410 r173c59c8  
    5454@c
    5555
    56 @set edition 4.2.0-beta1
    57 @set update-date 1 June 1997
    58 @set update-month June 1997
     56@set edition 970904
     57@set version 970904
     58@set update-date 4 September 1997
     59@set update-month September 1997
    5960
    6061@c
     
    6970
    7071@title RTEMS Applications Ada User's Guide
    71 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     72@subtitle Edition @value{edition}, for RTEMS @value{version}
    7273@sp 1
    7374@subtitle @value{update-month}
  • doc/develenv/develenv.texi

    r1d012410 r173c59c8  
    4949@c
    5050
    51 @set edition 4.2.0-beta1
    52 @set update-date 1 June 1997
    53 @set update-month June 1997
     51@set edition 970904
     52@set version 970904
     53@set update-date 4 September 1997
     54@set update-month September 1997
    5455
    5556@c
     
    6465
    6566@title RTEMS Development Environment Guide
    66 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     67@subtitle Edition @value{edition}, for RTEMS @value{version}
    6768@sp 1
    6869@subtitle @value{update-month}
  • doc/new_chapters/clock.texi

    r1d012410 r173c59c8  
    245245@subsection nanosleep
    246246 
    247 @subheading time SEQUENCE:
     247@subheading CALLING SEQUENCE:
    248248 
    249249@example
  • doc/new_chapters/posix_test_plan.texi

    r1d012410 r173c59c8  
    4949@c
    5050
    51 @set edition 4.2.0-beta1
    52 @set update-date 1 June 1997
    53 @set update-month June 1997
    54 
     51@set edition 970904
     52@set version 970904
     53@set update-date 4 September 1997
     54@set update-month September 1997
    5555@c
    5656@c  I don't really like having a short title page.  --joel
     
    6464
    6565@title RTEMS POSIX API Test Plan
    66 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     66@subtitle Edition @value{edition}, for RTEMS @value{version}
    6767@sp 1
    6868@subtitle @value{update-month}
  • doc/posix_users/clock.texi

    r1d012410 r173c59c8  
    245245@subsection nanosleep
    246246 
    247 @subheading time SEQUENCE:
     247@subheading CALLING SEQUENCE:
    248248 
    249249@example
  • doc/posix_users/posix_test_plan.texi

    r1d012410 r173c59c8  
    4949@c
    5050
    51 @set edition 4.2.0-beta1
    52 @set update-date 1 June 1997
    53 @set update-month June 1997
    54 
     51@set edition 970904
     52@set version 970904
     53@set update-date 4 September 1997
     54@set update-month September 1997
    5555@c
    5656@c  I don't really like having a short title page.  --joel
     
    6464
    6565@title RTEMS POSIX API Test Plan
    66 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     66@subtitle Edition @value{edition}, for RTEMS @value{version}
    6767@sp 1
    6868@subtitle @value{update-month}
  • doc/relnotes/relnotes.texi

    r1d012410 r173c59c8  
    4949@c
    5050
    51 @set edition 4.2.0-beta1
    52 @set update-date 1 June 1997
    53 @set update-month June 1997
     51@set edition 970904
     52@set version 970904
     53@set update-date 4 September 1997
     54@set update-month September 1997
    5455
    5556@c
     
    6465
    6566@title RTEMS Release Notes
    66 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     67@subtitle Edition @value{edition}, for RTEMS @value{version}
    6768@sp 1
    6869@subtitle @value{update-month}
  • doc/supplements/hppa1_1/hppa1_1.texi

    r1d012410 r173c59c8  
    3636@c
    3737
    38 @set edition 4.2.0-beta1
    39 @set update-date 1 June 1997
    40 @set update-month June 1997
     38@set edition 970904
     39@set version 970904
     40@set update-date 4 September 1997
     41@set update-month September 1997
    4142
    4243@c
     
    5152
    5253@title RTEMS Hewlett Packard PA-RISC Applications Supplement
    53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     54@subtitle Edition @value{edition}, for RTEMS @value{version}
    5455@sp 1
    5556@subtitle @value{update-month}
  • doc/supplements/i386/i386.texi

    r1d012410 r173c59c8  
    1 @c
    2 @c  COPYRIGHT (c) 1988-1997.
    3 @c  On-Line Applications Research Corporation (OAR).
    4 @c  All rights reserved.
    5 @c
    6 @c  $Id$
    7 @c
    8 
    91\input ../texinfo/texinfo   @c -*-texinfo-*-
    102@c %**start of header
     
    4436@c
    4537
    46 @set edition 4.2.0-beta1
    47 @set update-date 1 June 1997
    48 @set update-month June 1997
     38@set edition 970904
     39@set version 970904
     40@set update-date 4 September 1997
     41@set update-month September 1997
    4942
    5043@c
     
    5952
    6053@title RTEMS Intel i386 Applications Supplement
    61 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     54@subtitle Edition @value{edition}, for RTEMS @value{version}
    6255@sp 1
    6356@subtitle @value{update-month}
  • doc/supplements/i960/i960.texi

    r1d012410 r173c59c8  
    3636@c
    3737
    38 @set edition 4.2.0-beta1
    39 @set update-date 1 June 1997
    40 @set update-month June 1997
     38@set edition 970904
     39@set version 970904
     40@set update-date 4 September 1997
     41@set update-month September 1997
    4142
    4243@c
     
    5152
    5253@title RTEMS Intel i960 Applications Supplement
    53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     54@subtitle Edition @value{edition}, for RTEMS @value{version}
    5455@sp 1
    5556@subtitle @value{update-month}
  • doc/supplements/m68k/m68k.texi

    r1d012410 r173c59c8  
    3636@c
    3737
    38 @set edition 4.2.0-beta1
    39 @set update-date 1 June 1997
    40 @set update-month June 1997
     38@set edition 970904
     39@set version 970904
     40@set update-date 4 September 1997
     41@set update-month September 1997
    4142
    4243@c
     
    5152
    5253@title RTEMS Motorola MC68xxx Applications Supplement
    53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     54@subtitle Edition @value{edition}, for RTEMS @value{version}
    5455@sp 1
    5556@subtitle @value{update-month}
  • doc/supplements/powerpc/bsp.t

    r1d012410 r173c59c8  
    8888
    8989@itemize @bullet
    90 @item Must leave the PR bit of the machine state  register set so that
     90@item Must leave the PR bit of the machine state register set so that
    9191the PowerPC remains in the supervisor state.
    9292
  • doc/supplements/powerpc/bsp.texi

    r1d012410 r173c59c8  
    8888
    8989@itemize @bullet
    90 @item Must leave the PR bit of the machine state  register set so that
     90@item Must leave the PR bit of the machine state register set so that
    9191the PowerPC remains in the supervisor state.
    9292
  • doc/supplements/powerpc/callconv.t

    r1d012410 r173c59c8  
    154154@subsection Floating Point Registers
    155155
    156 The SPARC V7 architecture includes thirty-two,
    157 thirty-two bit registers.  These registers may be viewed as
    158 follows:
    159 
    160 @itemize @bullet
    161 @item 32 single precision floating point or integer registers
    162 (f0, f1,  ... f31)
    163 
    164 @item 16 double precision floating point registers (f0, f2,
    165 f4, ... f30)
    166 
    167 @item 8 extended precision floating point registers (f0, f4,
    168 f8, ... f28)
    169 @end itemize
    170 
    171 The floating point status register (fpsr) specifies
    172 the behavior of the floating point unit for rounding, contains
    173 its condition codes, version specification, and trap information.
    174 
     156The PowerPC architecture includes thirty-two,
     157sixty-four bit registers.  All PowwerPC floating point instructions
     158interprete these registers as 32 double precision floating point registers,
     159regardless of whether the processor has 64-bit or 32-bit implementation.
     160
     161The floating point status and control register (fpscr) records exceptions
     162and the type of result generated by floating-point operations.
     163Additionally, it controls the rounding mode of operations and allows the
     164reporting of floating exceptions to be enabled or disabled.
     165
     166XXXXXX
    175167A queue of the floating point instructions which have
    176168started execution but not yet completed is maintained.  This
     
    184176handlers with the store double floating point queue (stdfq)
    185177instruction.
     178XXX
    186179
    187180@ifinfo
     
    190183@subsection Special Registers
    191184
    192 The SPARC architecture includes two special registers
    193 which are critical to the programming model: the Processor State
    194 Register (psr) and the Window Invalid Mask (wim).  The psr
    195 contains the condition codes, processor interrupt level, trap
     185The PowerPC architecture includes XXX special registers
     186which are critical to the programming model: the Machine State
     187Register (msr) and XXX the Window Invalid Mask (wim) XXX.  The msr
     188contains the processor mode, power management mode, endian mode, exception
     189information, privlige level, floating point available and floating point
     190excepiton mode, address translation information and the exception prefix.
     191
     192XXX
     193condition codes, processor interrupt level, trap
    196194enable bit, supervisor mode and previous supervisor mode bits,
    197195version information, floating point unit and coprocessor enable
     
    200198in the SPARC architecture.  The register windows are discussed
    201199in more detail below.
     200XXX
    202201
    203202@ifinfo
     
    370369adhere to these calling conventions.
    371370
     371
     372
  • doc/supplements/powerpc/callconv.texi

    r1d012410 r173c59c8  
    154154@subsection Floating Point Registers
    155155
    156 The SPARC V7 architecture includes thirty-two,
    157 thirty-two bit registers.  These registers may be viewed as
    158 follows:
    159 
    160 @itemize @bullet
    161 @item 32 single precision floating point or integer registers
    162 (f0, f1,  ... f31)
    163 
    164 @item 16 double precision floating point registers (f0, f2,
    165 f4, ... f30)
    166 
    167 @item 8 extended precision floating point registers (f0, f4,
    168 f8, ... f28)
    169 @end itemize
    170 
    171 The floating point status register (fpsr) specifies
    172 the behavior of the floating point unit for rounding, contains
    173 its condition codes, version specification, and trap information.
    174 
     156The PowerPC architecture includes thirty-two,
     157sixty-four bit registers.  All PowwerPC floating point instructions
     158interprete these registers as 32 double precision floating point registers,
     159regardless of whether the processor has 64-bit or 32-bit implementation.
     160
     161The floating point status and control register (fpscr) records exceptions
     162and the type of result generated by floating-point operations.
     163Additionally, it controls the rounding mode of operations and allows the
     164reporting of floating exceptions to be enabled or disabled.
     165
     166XXXXXX
    175167A queue of the floating point instructions which have
    176168started execution but not yet completed is maintained.  This
     
    184176handlers with the store double floating point queue (stdfq)
    185177instruction.
     178XXX
    186179
    187180@ifinfo
     
    190183@subsection Special Registers
    191184
    192 The SPARC architecture includes two special registers
    193 which are critical to the programming model: the Processor State
    194 Register (psr) and the Window Invalid Mask (wim).  The psr
    195 contains the condition codes, processor interrupt level, trap
     185The PowerPC architecture includes XXX special registers
     186which are critical to the programming model: the Machine State
     187Register (msr) and XXX the Window Invalid Mask (wim) XXX.  The msr
     188contains the processor mode, power management mode, endian mode, exception
     189information, privlige level, floating point available and floating point
     190excepiton mode, address translation information and the exception prefix.
     191
     192XXX
     193condition codes, processor interrupt level, trap
    196194enable bit, supervisor mode and previous supervisor mode bits,
    197195version information, floating point unit and coprocessor enable
     
    200198in the SPARC architecture.  The register windows are discussed
    201199in more detail below.
     200XXX
    202201
    203202@ifinfo
     
    370369adhere to these calling conventions.
    371370
     371
     372
  • doc/supplements/powerpc/powerpc.texi

    r1d012410 r173c59c8  
    3636@c
    3737
    38 @set edition 4.2.0-beta1
    39 @set update-date 1 June 1997
    40 @set update-month June 1997
     38@set edition 970904
     39@set version 970904
     40@set update-date 4 September 1997
     41@set update-month September 1997
    4142
    4243@c
     
    5152
    5253@title RTEMS PowerPC Applications Supplement
    53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     54@subtitle Edition @value{edition}, for RTEMS @value{version}
    5455@sp 1
    5556@subtitle @value{update-month}
  • doc/supplements/sparc/sparc.texi

    r1d012410 r173c59c8  
    3636@c
    3737
    38 @set edition 4.2.0-beta1
    39 @set update-date 1 June 1997
    40 @set update-month June 1997
     38@set edition 970904
     39@set version 970904
     40@set update-date 4 September 1997
     41@set update-month September 1997
    4142
    4243@c
     
    5152
    5253@title RTEMS SPARC Applications Supplement
    53 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     54@subtitle Edition @value{edition}, for RTEMS @value{version}
    5455@sp 1
    5556@subtitle @value{update-month}
  • doc/user/c_user.texi

    r1d012410 r173c59c8  
    5454@c
    5555
    56 @set edition 4.2.0-beta1
    57 @set update-date 1 June 1997
    58 @set update-month June 1997
     56@set edition 970904
     57@set version 970904
     58@set update-date 4 September 1997
     59@set update-month September 1997
    5960
    6061@c
     
    6970
    7071@title RTEMS C User's Guide
    71 @subtitle Edition @value{edition}, for RTEMS 4.2.0-prerelease
     72@subtitle Edition @value{edition}, for RTEMS @value{version}
    7273@sp 1
    7374@subtitle @value{update-month}
  • doc/user/intr.t

    r1d012410 r173c59c8  
    316316@code{SUCCESSFUL} - ISR established successfully@*
    317317@code{INVALID_NUMBER} - illegal vector number@*
    318 @code{INVALID_ADDRESS} - illegal ISR entry point
     318@code{INVALID_ADDRESS} - illegal ISR entry point or invalid old_isr_handler
    319319
    320320@subheading DESCRIPTION:
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