Changeset 16ad7ea in rtems


Ignore:
Timestamp:
Jan 9, 2001, 4:48:26 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
026f4aa
Parents:
96e34e0
Message:

2001-01-09 Joel Sherrill <joel@…>

  • cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants to make it easier to conditionalize the code for various ISA levels.
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/mips/ChangeLog

    r96e34e0 r16ad7ea  
     12001-01-09      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
     4        to make it easier to conditionalize the code for various ISA levels.
     5
    162001-01-08      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/exec/score/cpu/mips/cpu_asm.S

    r96e34e0 r16ad7ea  
    368368
    369369        mfc0 t0,C0_SR
    370         li t1,~SR_IEC
     370        li t1,~(SR_INTERRUPT_ENABLE_BITS)
    371371        sw t0,C0_SR_OFFSET*4(a0)        /* save status register */
    372372        and t0,t1
     
    403403        mtc0 t0,C0_EPC
    404404        lw t0, C0_SR_OFFSET*4(a1)
    405         andi t0,SR_IEC                  /* we know IEC=0, e.g. disabled */
    406         beq t0,$0,_CPU_Context_1        /* set IEC level from restore context */
     405        andi t0,(SR_INTERRUPT_ENABLE_BITS) /* we know 0 disabled */
     406        beq t0,$0,_CPU_Context_1        /* set level from restore context */
    407407        mfc0 t0,C0_SR
    408408        nop
    409         or  t0,SR_IEC                   /* new_sr = sr | SR_IEC */
    410         mtc0 t0,C0_SR                   /* set with enabled */
     409        or  t0,(SR_INTERRUPT_ENABLE_BITS)  /* new_sr = old sr with enabled */
     410        mtc0 t0,C0_SR                      /* set with enabled */
    411411       
    412412
  • c/src/exec/score/cpu/mips/rtems/score/cpu.h

    r96e34e0 r16ad7ea  
    600600  do { \
    601601    mips_get_sr( _level ); \
    602     mips_set_sr( (_level) & ~SR_IMASK ); \
     602    mips_set_sr( (_level) & ~SR_INTERRUPT_ENABLE_BITS ); \
    603603  } while(0)
    604604
  • c/src/exec/score/cpu/mips/rtems/score/mips.h

    r96e34e0 r16ad7ea  
    2121#ifndef ASM
    2222#include <idtcpu.h>
     23#endif
     24
     25/*
     26 *  SR bits that enable/disable interrupts
     27 *
     28 *  NOTE: XXX what about SR_ERL?
     29 */
     30
     31#if __mips == 3
     32#ifdef ASM
     33#define SR_INTERRUPT_ENABLE_BITS 0x03
     34#else
     35#define SR_INTERRUPT_ENABLE_BITS SR_IE|SR_EXL
     36#endif
     37#else
     38#define SR_INTERRUPT_ENABLE_BITS SR_IEC
    2339#endif
    2440
  • cpukit/score/cpu/mips/ChangeLog

    r96e34e0 r16ad7ea  
     12001-01-09      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
     4        to make it easier to conditionalize the code for various ISA levels.
     5
    162001-01-08      Joel Sherrill <joel@OARcorp.com>
    27
  • cpukit/score/cpu/mips/cpu_asm.S

    r96e34e0 r16ad7ea  
    368368
    369369        mfc0 t0,C0_SR
    370         li t1,~SR_IEC
     370        li t1,~(SR_INTERRUPT_ENABLE_BITS)
    371371        sw t0,C0_SR_OFFSET*4(a0)        /* save status register */
    372372        and t0,t1
     
    403403        mtc0 t0,C0_EPC
    404404        lw t0, C0_SR_OFFSET*4(a1)
    405         andi t0,SR_IEC                  /* we know IEC=0, e.g. disabled */
    406         beq t0,$0,_CPU_Context_1        /* set IEC level from restore context */
     405        andi t0,(SR_INTERRUPT_ENABLE_BITS) /* we know 0 disabled */
     406        beq t0,$0,_CPU_Context_1        /* set level from restore context */
    407407        mfc0 t0,C0_SR
    408408        nop
    409         or  t0,SR_IEC                   /* new_sr = sr | SR_IEC */
    410         mtc0 t0,C0_SR                   /* set with enabled */
     409        or  t0,(SR_INTERRUPT_ENABLE_BITS)  /* new_sr = old sr with enabled */
     410        mtc0 t0,C0_SR                      /* set with enabled */
    411411       
    412412
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    r96e34e0 r16ad7ea  
    600600  do { \
    601601    mips_get_sr( _level ); \
    602     mips_set_sr( (_level) & ~SR_IMASK ); \
     602    mips_set_sr( (_level) & ~SR_INTERRUPT_ENABLE_BITS ); \
    603603  } while(0)
    604604
  • cpukit/score/cpu/mips/rtems/score/mips.h

    r96e34e0 r16ad7ea  
    2121#ifndef ASM
    2222#include <idtcpu.h>
     23#endif
     24
     25/*
     26 *  SR bits that enable/disable interrupts
     27 *
     28 *  NOTE: XXX what about SR_ERL?
     29 */
     30
     31#if __mips == 3
     32#ifdef ASM
     33#define SR_INTERRUPT_ENABLE_BITS 0x03
     34#else
     35#define SR_INTERRUPT_ENABLE_BITS SR_IE|SR_EXL
     36#endif
     37#else
     38#define SR_INTERRUPT_ENABLE_BITS SR_IEC
    2339#endif
    2440
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