Changeset 1693c131 in rtems


Ignore:
Timestamp:
Nov 26, 2007, 9:20:33 PM (12 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
bab02ab
Parents:
f9f8239
Message:

2007-11-26 Joel Sherrill <joel.sherrill@…>

  • startup/bspstart.c: Eliminate the interrupt_vector_table field in the m68k CPU Table since it is never read.
Location:
c/src/lib/libbsp/m68k
Files:
30 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/av5282/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/av5282/startup/bspstart.c

    rf9f8239 r1693c131  
    193193  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    194194  Cpu_table.interrupt_stack_size = 4096;
    195   Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
    196 
    197     /*
    198      * Invalidate the cache and disable it
    199      */
    200     m68k_set_acr0(0);
    201     m68k_set_acr1(0);
    202     m68k_set_cacr(MCF5XXX_CACR_CINV);
    203 
    204     /*
    205      * Cache SDRAM and FLASH
    206      */
    207     m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
    208                   MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
    209                   MCF5XXX_ACR_EN                |
    210                   MCF5XXX_ACR_BWE               |
    211                   MCF5XXX_ACR_SM_IGNORE);
    212 
    213     /*
    214      * Enable the cache
    215      */
    216     m68k_set_cacr(cacr_mode);
    217 
     195
     196  /*
     197   * Invalidate the cache and disable it
     198   */
     199  m68k_set_acr0(0);
     200  m68k_set_acr1(0);
     201  m68k_set_cacr(MCF5XXX_CACR_CINV);
     202
     203  /*
     204   * Cache SDRAM and FLASH
     205   */
     206  m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
     207                MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
     208                MCF5XXX_ACR_EN                |
     209                MCF5XXX_ACR_BWE               |
     210                MCF5XXX_ACR_SM_IGNORE);
     211
     212  /*
     213   * Enable the cache
     214   */
     215  m68k_set_cacr(cacr_mode);
    218216}
    219217
    220218uint32_t get_CPU_clock_speed(void)
    221219{
    222     extern char _CPUClockSpeed[];
    223     return( (uint32_t)_CPUClockSpeed);
    224 }
     220  extern char _CPUClockSpeed[];
     221  return( (uint32_t)_CPUClockSpeed);
     222}
  • c/src/lib/libbsp/m68k/csb360/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/csb360/startup/bspstart.c

    rf9f8239 r1693c131  
    8080    Cpu_table.postdriver_hook = bsp_postdriver_hook;
    8181    Cpu_table.interrupt_stack_size = 4096;
    82     Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
    8382}
  • c/src/lib/libbsp/m68k/gen68302/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c

    rf9f8239 r1693c131  
    6363   *  of work space from the last physical address on the CPU board.
    6464   */
    65 #if 0
    66   Cpu_table.interrupt_vector_table = (mc68000_isr *) 0/*&M68Kvec*/;
    67 #endif
    6865
    6966  /*
  • c/src/lib/libbsp/m68k/gen68340/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/gen68340/startup/bspstart.c

    rf9f8239 r1693c131  
    6666   *  of work space from the last physical address on the CPU board.
    6767   */
    68 #if 0
    69   Cpu_table.interrupt_vector_table = (mc68000_isr *) 0/*&M68Kvec*/;
    70 #endif
    7168
    7269  /*
  • c/src/lib/libbsp/m68k/idp/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-06-22      Joel Sherrill <joel.sherrill@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/idp/startup/bspstart.c

    rf9f8239 r1693c131  
    9898  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    9999  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    100   Cpu_table.interrupt_vector_table = (m68k_isr_entry *) &M68Kvec;
    101100  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
    102101
  • c/src/lib/libbsp/m68k/mcf5206elite/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/mcf5206elite/startup/bspstart.c

    rf9f8239 r1693c131  
    6060void bsp_start( void )
    6161{
    62     extern void *_WorkspaceBase;
     62  extern void *_WorkspaceBase;
    6363
    64     /*
    65      *  Need to "allocate" the memory for the RTEMS Workspace and
    66      *  tell the RTEMS configuration where it is.  This memory is
    67      *  not malloc'ed.  It is just "pulled from the air".
    68      */
     64  /*
     65   *  Need to "allocate" the memory for the RTEMS Workspace and
     66   *  tell the RTEMS configuration where it is.  This memory is
     67   *  not malloc'ed.  It is just "pulled from the air".
     68   */
    6969
    70     BSP_Configuration.work_space_start = (void *)&_WorkspaceBase;
     70  BSP_Configuration.work_space_start = (void *)&_WorkspaceBase;
    7171
    72     /*
    73      *  initialize the CPU table for this BSP
    74      */
    75     Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    76     Cpu_table.postdriver_hook = bsp_postdriver_hook;
    77     Cpu_table.interrupt_stack_size = 4096;
    78     Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
     72  /*
     73   *  initialize the CPU table for this BSP
     74   */
     75  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
     76  Cpu_table.postdriver_hook = bsp_postdriver_hook;
     77  Cpu_table.interrupt_stack_size = 4096;
    7978}
  • c/src/lib/libbsp/m68k/mcf5235/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c

    rf9f8239 r1693c131  
    186186  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    187187  Cpu_table.interrupt_stack_size = 4096;
    188   Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
    189 
    190     /*
    191      * Invalidate the cache and disable it
    192      */
    193     m68k_set_acr0(0);
    194     m68k_set_acr1(0);
    195     m68k_set_cacr(MCF5XXX_CACR_CINV);
    196 
    197     /*
    198      * Cache SDRAM
    199      */
    200     m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
    201                   MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
    202                   MCF5XXX_ACR_EN                |
    203                   MCF5XXX_ACR_BWE               |
    204                   MCF5XXX_ACR_SM_IGNORE);
    205 
    206     /*
    207      * Enable the cache
    208      */
    209     m68k_set_cacr(cacr_mode);
    210 
     188
     189  /*
     190   * Invalidate the cache and disable it
     191   */
     192  m68k_set_acr0(0);
     193  m68k_set_acr1(0);
     194  m68k_set_cacr(MCF5XXX_CACR_CINV);
     195
     196  /*
     197   * Cache SDRAM
     198   */
     199  m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
     200                MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
     201                MCF5XXX_ACR_EN                |
     202                MCF5XXX_ACR_BWE               |
     203                MCF5XXX_ACR_SM_IGNORE);
     204
     205  /*
     206   * Enable the cache
     207   */
     208  m68k_set_cacr(cacr_mode);
    211209}
    212210
    213211uint32_t get_CPU_clock_speed(void)
    214212{
    215     extern char _CPUClockSpeed[];
    216     return( (uint32_t)_CPUClockSpeed);
    217 }
     213  extern char _CPUClockSpeed[];
     214  return( (uint32_t)_CPUClockSpeed);
     215}
  • c/src/lib/libbsp/m68k/mrm332/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/mrm332/startup/bspstart.c

    rf9f8239 r1693c131  
    7575
    7676  m68k_get_vbr( vbr );
    77   Cpu_table.interrupt_vector_table = vbr;
    7877
    7978  BSP_Configuration.work_space_start = (void *) &_WorkspaceBase;
  • c/src/lib/libbsp/m68k/mvme136/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c

    rf9f8239 r1693c131  
    8181  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    8282  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    83   Cpu_table.interrupt_vector_table = (m68k_isr_entry *) &M68Kvec;
    8483  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
    8584
  • c/src/lib/libbsp/m68k/mvme147/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c

    rf9f8239 r1693c131  
    8888  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    8989  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    90   Cpu_table.interrupt_vector_table = (m68k_isr_entry *) &M68Kvec;
    9190  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
    9291
  • c/src/lib/libbsp/m68k/mvme147s/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c

    rf9f8239 r1693c131  
    147147  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    148148  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    149   Cpu_table.interrupt_vector_table = (m68k_isr_entry *) &M68Kvec;
    150149  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
    151150
  • c/src/lib/libbsp/m68k/mvme162/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/mvme162/startup/bspstart.c

    rf9f8239 r1693c131  
    6363  extern unsigned long  _M68k_Ramsize;
    6464
    65   _M68k_Ramsize = (unsigned long)&_RamSize;             /* RAM size set in linker script */
     65  _M68k_Ramsize = (unsigned long)&_RamSize;  /* RAM size set in linker script */
    6666
    6767  /*
     
    105105  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    106106  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    107   Cpu_table.interrupt_vector_table = (m68k_isr_entry *) &M68Kvec;
    108107  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
    109108
  • c/src/lib/libbsp/m68k/mvme167/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/mvme167/startup/bspstart.c

    rf9f8239 r1693c131  
    128128  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    129129  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    130   Cpu_table.interrupt_vector_table = (m68k_isr_entry *) &M68Kvec;
    131130  /* Must match value in start.s */
    132131  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
  • c/src/lib/libbsp/m68k/ods68302/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-05-03      Joel Sherrill <joel@OARcorp.com>
    27
  • c/src/lib/libbsp/m68k/ods68302/startup/bspstart.c

    rf9f8239 r1693c131  
    5454  extern unsigned long  _M68k_Ramsize;
    5555
    56   _M68k_Ramsize = (unsigned long)&_RamSize;             /* RAM size set in linker script */
    57 
    58 #if 0
    59   Cpu_table.interrupt_vector_table = (mc68000_isr *) 0/*&M68Kvec*/;
    60 #endif
     56  _M68k_Ramsize = (unsigned long)&_RamSize;  /* RAM size set in linker script */
    6157
    6258  /*
  • c/src/lib/libbsp/m68k/uC5282/ChangeLog

    rf9f8239 r1693c131  
     12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * startup/bspstart.c: Eliminate the interrupt_vector_table field in the
     4        m68k CPU Table since it is never read.
     5
    162007-11-26      Eric Norum <norume@aps.anl.gov>
    27
  • c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c

    rf9f8239 r1693c131  
    277277    Cpu_table.idle_task = _BSP_Thread_Idle_body;
    278278  }
    279   Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
    280 
    281     /*
    282      * Invalidate the cache and disable it
    283      */
    284     m68k_set_acr0(mcf5282_acr0_mode);
    285     m68k_set_acr1(mcf5282_acr1_mode);
    286     m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
    287 
    288     /*
    289      * Cache SDRAM
    290      */
    291     mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
    292                         MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
    293                         MCF5XXX_ACR_EN                         |
    294                         MCF5XXX_ACR_BWE                        |
    295                         MCF5XXX_ACR_SM_IGNORE;
    296     m68k_set_acr0(mcf5282_acr0_mode);
    297 
    298     /*
    299      * Enable the cache
    300      */
    301     m68k_set_cacr(mcf5282_cacr_mode);
    302 
    303     /*
    304      * Set up CS* space (fake 'VME')
    305      *   Two A24/D16 spaces, supervisor data acces
    306      */
    307     MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
    308     MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
    309                        MCF5282_CS_CSMR_CI |
    310                        MCF5282_CS_CSMR_SC |
    311                        MCF5282_CS_CSMR_UC |
    312                        MCF5282_CS_CSMR_UD |
    313                        MCF5282_CS_CSMR_V;
    314     MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
    315     MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
    316     MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
    317                        MCF5282_CS_CSMR_CI |
    318                        MCF5282_CS_CSMR_SC |
    319                        MCF5282_CS_CSMR_UC |
    320                        MCF5282_CS_CSMR_UD |
    321                        MCF5282_CS_CSMR_V;
    322     MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
    323     MCF5282_GPIO_PJPAR |= 0x06;
     279
     280  /*
     281   * Invalidate the cache and disable it
     282   */
     283  m68k_set_acr0(mcf5282_acr0_mode);
     284  m68k_set_acr1(mcf5282_acr1_mode);
     285  m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
     286
     287  /*
     288   * Cache SDRAM
     289   */
     290  mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
     291                      MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
     292                      MCF5XXX_ACR_EN                         |
     293                      MCF5XXX_ACR_BWE                        |
     294                      MCF5XXX_ACR_SM_IGNORE;
     295  m68k_set_acr0(mcf5282_acr0_mode);
     296
     297  /*
     298   * Enable the cache
     299   */
     300  m68k_set_cacr(mcf5282_cacr_mode);
     301
     302  /*
     303   * Set up CS* space (fake 'VME')
     304   *   Two A24/D16 spaces, supervisor data acces
     305   */
     306  MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
     307  MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
     308                     MCF5282_CS_CSMR_CI |
     309                     MCF5282_CS_CSMR_SC |
     310                     MCF5282_CS_CSMR_UC |
     311                     MCF5282_CS_CSMR_UD |
     312                     MCF5282_CS_CSMR_V;
     313  MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
     314  MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
     315  MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
     316                     MCF5282_CS_CSMR_CI |
     317                     MCF5282_CS_CSMR_SC |
     318                     MCF5282_CS_CSMR_UC |
     319                     MCF5282_CS_CSMR_UD |
     320                     MCF5282_CS_CSMR_V;
     321  MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
     322  MCF5282_GPIO_PJPAR |= 0x06;
    324323}
    325324
    326325uint32_t bsp_get_CPU_clock_speed(void)
    327326{
    328     extern char _CPUClockSpeed[];
    329     return( (uint32_t)_CPUClockSpeed);
     327  extern char _CPUClockSpeed[];
     328  return( (uint32_t)_CPUClockSpeed);
    330329}
    331330
     
    336335bsp_allocate_interrupt(int level, int priority)
    337336{
    338     static char used[7];
    339     rtems_interrupt_level l;
    340     rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
    341 
    342     if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
    343         return RTEMS_INVALID_NUMBER;
    344     rtems_interrupt_disable(l);
    345     if ((used[level-1] & (1 << priority)) == 0) {
    346         used[level-1] |= (1 << priority);
    347         ret = RTEMS_SUCCESSFUL;
    348     }
    349     rtems_interrupt_enable(l);
    350     return ret;
     337  static char used[7];
     338  rtems_interrupt_level l;
     339  rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
     340
     341  if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
     342    return RTEMS_INVALID_NUMBER;
     343  rtems_interrupt_disable(l);
     344  if ((used[level-1] & (1 << priority)) == 0) {
     345    used[level-1] |= (1 << priority);
     346    ret = RTEMS_SUCCESSFUL;
     347  }
     348  rtems_interrupt_enable(l);
     349  return ret;
    351350}
    352351
     
    362361   return (type)(ret);                                 \
    363362} while (0)
     363
    364364#define syscall_1(type,name,d1type,d1)                      \
    365365type bsp_##name(d1type d1)                                  \
     
    375375   syscall_return(type,ret);                                \
    376376}
     377
    377378#define syscall_2(type,name,d1type,d1,d2type,d2)            \
    378379type bsp_##name(d1type d1, d2type d2)                       \
     
    390391   syscall_return(type,ret);                                \
    391392}
     393
    392394#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3)  \
    393395type bsp_##name(d1type d1, d2type d2, d3type d3)            \
     
    407409   syscall_return(type,ret);                                \
    408410}
     411
    409412#define SysCode_reset              0 /* reset */
    410413#define SysCode_program            5 /* program flash memory */
     
    450453
    451454static struct handlerTab {
    452     BSP_VME_ISR_t func;
    453     void         *arg;
     455  BSP_VME_ISR_t func;
     456  void         *arg;
    454457} handlerTab[NVECTOR];
    455458
     
    457460BSP_getVME_isr(unsigned long vector, void **pusrArg)
    458461{
    459     if (vector >= NVECTOR)
    460         return (BSP_VME_ISR_t)NULL;
    461     if (pusrArg)
    462         *pusrArg = handlerTab[vector].arg;
    463     return handlerTab[vector].func;
     462  if (vector >= NVECTOR)
     463    return (BSP_VME_ISR_t)NULL;
     464  if (pusrArg)
     465    *pusrArg = handlerTab[vector].arg;
     466  return handlerTab[vector].func;
    464467}
    465468
     
    467470fpga_trampoline (rtems_vector_number v)
    468471{
    469         /*
    470         * Handle FPGA interrupts until all have been consumed
    471         */
    472         int loopcount = 0;
    473         while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
    474                 v = 192 + (v & 0x3f);
    475                 if (++loopcount >= 50) {
    476                         rtems_interrupt_level level;
    477                         rtems_interrupt_disable(level);
    478                         printk("\nTOO MANY FPGA INTERRUPTS (LAST WAS 0x%x) -- DISABLING ALL FPGA INTERRUPTS.\n", v & 0x3f);
    479                         MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1;
    480                         rtems_interrupt_enable(level);
    481                         return;
    482                 }
    483                 if (handlerTab[v].func)  {
    484                         (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
    485                 }
    486                 else {
    487                         rtems_interrupt_level level;
    488                         rtems_vector_number nv;
    489                         rtems_interrupt_disable(level);
    490                         printk("\nSPURIOUS FPGA INTERRUPT (0x%x).\n", v & 0x3f);
    491                         if ((((nv = FPGA_IRQ_INFO) & 0x80) != 0)
    492                                         && ((nv & 0x3f) == (v & 0x3f))) {
    493                                 printk("DISABLING ALL FPGA INTERRUPTS.\n");
    494                                 MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1;
    495                         }
    496                         rtems_interrupt_enable(level);
    497                         return;
    498                 }
    499         }
     472  /*
     473  * Handle FPGA interrupts until all have been consumed
     474  */
     475  int loopcount = 0;
     476  while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
     477    v = 192 + (v & 0x3f);
     478    if (++loopcount >= 50) {
     479      rtems_interrupt_level level;
     480      rtems_interrupt_disable(level);
     481      printk("\nTOO MANY FPGA INTERRUPTS (LAST WAS 0x%x) -- DISABLING ALL FPGA INTERRUPTS.\n", v & 0x3f);
     482      MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1;
     483      rtems_interrupt_enable(level);
     484      return;
     485    }
     486    if (handlerTab[v].func)  {
     487      (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
     488    }
     489    else {
     490      rtems_interrupt_level level;
     491      rtems_vector_number nv;
     492      rtems_interrupt_disable(level);
     493      printk("\nSPURIOUS FPGA INTERRUPT (0x%x).\n", v & 0x3f);
     494      if ((((nv = FPGA_IRQ_INFO) & 0x80) != 0)
     495          && ((nv & 0x3f) == (v & 0x3f))) {
     496        printk("DISABLING ALL FPGA INTERRUPTS.\n");
     497        MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1;
     498      }
     499      rtems_interrupt_enable(level);
     500      return;
     501    }
     502  }
    500503}
    501504
     
    511514{
    512515rtems_interrupt_level level;
    513         rtems_interrupt_disable(level);
    514         if (source >= 32)
    515                 MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
    516         else
    517                 MCF5282_INTC0_IMRL &= ~((1 << source) |
    518                                 MCF5282_INTC_IMRL_MASKALL);
    519         rtems_interrupt_enable(level);
     516  rtems_interrupt_disable(level);
     517  if (source >= 32)
     518    MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
     519  else
     520    MCF5282_INTC0_IMRL &= ~((1 << source) |
     521        MCF5282_INTC_IMRL_MASKALL);
     522  rtems_interrupt_enable(level);
    520523}
    521524
     
    525528rtems_interrupt_level level;
    526529
    527         rtems_interrupt_disable(level);
    528         if (source >= 32)
    529                 MCF5282_INTC0_IMRH |= (1 << (source - 32));
    530         else
    531                 MCF5282_INTC0_IMRL |= (1 << source);
    532         rtems_interrupt_enable(level);
     530  rtems_interrupt_disable(level);
     531  if (source >= 32)
     532    MCF5282_INTC0_IMRH |= (1 << (source - 32));
     533  else
     534    MCF5282_INTC0_IMRL |= (1 << source);
     535  rtems_interrupt_enable(level);
    533536}
    534537
     
    538541int                   source = v - 64;
    539542
    540         if ( source > 0 && source < 64 ) {
    541                 enable_irq(source);
    542         }
     543  if ( source > 0 && source < 64 ) {
     544    enable_irq(source);
     545  }
    543546}
    544547
     
    548551int                   source = v - 64;
    549552
    550         if ( source > 0 && source < 64 ) {
    551                 disable_irq(source);
    552         }
     553  if ( source > 0 && source < 64 ) {
     554    disable_irq(source);
     555  }
    553556}
    554557
     
    558561int                   source = v - 64;
    559562
    560         if ( source > 0 && source < 64 ) {
    561                 return ! ((source >= 32) ?
    562                         MCF5282_INTC0_IMRH & (1 << (source - 32)) :
    563                         MCF5282_INTC0_IMRL & (1 << source));
    564         }
    565         return -1;
     563  if ( source > 0 && source < 64 ) {
     564    return ! ((source >= 32) ?
     565      MCF5282_INTC0_IMRH & (1 << (source - 32)) :
     566      MCF5282_INTC0_IMRL & (1 << source));
     567  }
     568  return -1;
    566569}
    567570
     
    598601                                                       MCF5282_INTC_ICR_IL(l) |
    599602                                                       MCF5282_INTC_ICR_IP(p);
    600                                         enable_irq(source);
     603          enable_irq(source);
    601604                    return 0;
    602605                }
     
    605608        return -1;
    606609    }
    607         return 0;
     610  return 0;
    608611}
    609612
     
    611614BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
    612615{
    613     rtems_isr_entry old_handler;
    614     rtems_interrupt_level level;
    615 
    616     /*
    617      * Register the handler information
    618      */
    619     if (vector >= NVECTOR)
    620         return -1;
    621     handlerTab[vector].func = handler;
    622     handlerTab[vector].arg = usrArg;
    623 
    624     /*
    625      * If this is an external FPGA ('VME') vector set up the real IRQ.
    626      */
    627     if ((vector >= 192) && (vector <= 255)) {
    628         int i;
    629         static volatile int setupDone;
    630         rtems_interrupt_disable(level);
    631         if (setupDone) {
    632             rtems_interrupt_enable(level);
    633             return 0;
    634         }
    635         MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
    636         MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
    637         MCF5282_EPORT_EPIER |=  FPGA_EPIER;
    638         MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 |
     616  rtems_isr_entry old_handler;
     617  rtems_interrupt_level level;
     618
     619  /*
     620   * Register the handler information
     621   */
     622  if (vector >= NVECTOR)
     623    return -1;
     624  handlerTab[vector].func = handler;
     625  handlerTab[vector].arg = usrArg;
     626
     627  /*
     628   * If this is an external FPGA ('VME') vector set up the real IRQ.
     629   */
     630  if ((vector >= 192) && (vector <= 255)) {
     631    int i;
     632    static volatile int setupDone;
     633    rtems_interrupt_disable(level);
     634    if (setupDone) {
     635      rtems_interrupt_enable(level);
     636      return 0;
     637    }
     638    MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
     639    MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
     640    MCF5282_EPORT_EPIER |=  FPGA_EPIER;
     641    MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 |
    639642                                MCF5282_INTC_IMRL_MASKALL);
    640         setupDone = 1;
    641         handlerTab[vector].func = NULL;
    642         handlerTab[vector].arg  = NULL;
    643                 rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler);
    644         i = init_intc0_bit(FPGA_VECTOR);
    645         rtems_interrupt_enable(level);
    646         return i;
    647     }
    648 
    649     /*
    650      * Make the connection between the interrupt and the local handler
    651      */
    652     rtems_interrupt_catch(trampoline, vector, &old_handler);
    653 
    654     return init_intc0_bit(vector);
     643    setupDone = 1;
     644    handlerTab[vector].func = NULL;
     645    handlerTab[vector].arg  = NULL;
     646    rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler);
     647    i = init_intc0_bit(FPGA_VECTOR);
     648    rtems_interrupt_enable(level);
     649    return i;
     650  }
     651
     652  /*
     653   * Make the connection between the interrupt and the local handler
     654   */
     655  rtems_interrupt_catch(trampoline, vector, &old_handler);
     656
     657  return init_intc0_bit(vector);
    655658}
    656659
     
    658661BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
    659662{
    660     if (vector >= NVECTOR)
    661         return -1;
    662     if ((handlerTab[vector].func != handler)
     663  if (vector >= NVECTOR)
     664    return -1;
     665  if ((handlerTab[vector].func != handler)
    663666     || (handlerTab[vector].arg != usrArg))
    664         return -1;
    665     handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
    666     return 0;
     667    return -1;
     668  handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
     669  return 0;
    667670}
    668671
     
    670673BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
    671674{
    672     unsigned long offset;
    673 
    674     switch (am) {
     675  unsigned long offset;
     676
     677  switch (am) {
    675678    default:    return -1;
    676679    case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
    677680    case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
    678681    case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
    679     }
    680     *plocaladdr = vmeaddr + offset;
    681     return 0;
     682  }
     683  *plocaladdr = vmeaddr + offset;
     684  return 0;
    682685}
    683686
     
    685688rtems_bsp_reset_cause(char *buf, size_t capacity)
    686689{
    687    int bit, rsr;
    688    size_t i;
    689    const char *cp;
     690  int bit, rsr;
     691  size_t i;
     692  const char *cp;
    690693   
    691     if (buf == NULL)
    692         return;
    693     if (capacity)
    694         buf[0] = '\0';
    695     rsr = MCF5282_RESET_RSR;
    696     for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) {
    697         if (rsr & bit) {
    698             switch (bit) {
    699             case MCF5282_RESET_RSR_LVD:  cp = "Low voltage";        break;
    700             case MCF5282_RESET_RSR_SOFT: cp = "Software reset";     break;
    701             case MCF5282_RESET_RSR_WDR:  cp = "Watchdog reset";     break;
    702             case MCF5282_RESET_RSR_POR:  cp = "Power-on reset";     break;
    703             case MCF5282_RESET_RSR_EXT:  cp = "External reset";     break;
    704             case MCF5282_RESET_RSR_LOC:  cp = "Loss of clock";      break;
    705             case MCF5282_RESET_RSR_LOL:  cp = "Loss of lock";       break;
    706             default:                     cp = "??";                 break;
    707             }
    708             i += snprintf(buf+i, capacity-i, cp);
    709             if (i >= capacity)
    710                 break;
    711             rsr &= ~bit;
    712             if (rsr == 0)
    713                 break;
    714             i += snprintf(buf+i, capacity-i, ", ");
    715             if (i >= capacity)
    716                 break;
    717         }
     694  if (buf == NULL)
     695    return;
     696  if (capacity)
     697    buf[0] = '\0';
     698  rsr = MCF5282_RESET_RSR;
     699  for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) {
     700    if (rsr & bit) {
     701      switch (bit) {
     702        case MCF5282_RESET_RSR_LVD:  cp = "Low voltage";        break;
     703        case MCF5282_RESET_RSR_SOFT: cp = "Software reset";     break;
     704        case MCF5282_RESET_RSR_WDR:  cp = "Watchdog reset";     break;
     705        case MCF5282_RESET_RSR_POR:  cp = "Power-on reset";     break;
     706        case MCF5282_RESET_RSR_EXT:  cp = "External reset";     break;
     707        case MCF5282_RESET_RSR_LOC:  cp = "Loss of clock";      break;
     708        case MCF5282_RESET_RSR_LOL:  cp = "Loss of lock";       break;
     709        default:                     cp = "??";                 break;
     710      }
     711      i += snprintf(buf+i, capacity-i, cp);
     712      if (i >= capacity)
     713        break;
     714      rsr &= ~bit;
     715      if (rsr == 0)
     716        break;
     717      i += snprintf(buf+i, capacity-i, ", ");
     718      if (i >= capacity)
     719        break;
    718720    }
    719 }
     721  }
     722}
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