Changeset 15b6f44d in rtems


Ignore:
Timestamp:
Aug 12, 2019, 3:58:31 AM (8 days ago)
Author:
Chris Johns <chrisj@…>
Branches:
master
Children:
d3c4d48
Parents:
df256505
Message:

arm/tlb: Fix the MP affinity check to invalidate ASIDs.

  • The TI's CortexA7 MP MPIDR register returns 0

Updates #3760

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c

    rdf256505 r15b6f44d  
    6767    void *mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT);
    6868#if defined(__ARM_ARCH_7A__)
    69     if ((arm_cp15_get_multiprocessor_affinity() & (1 << 30)) == 0) {
     69    /*
     70     * Bit 31 needs to be 1 to indicate the register implements the
     71     * Multiprocessing Extensions register format and the U (bit 30)
     72     * is 0.
     73     */
     74    #define MPIDR_MX_FMT (1 << 31)
     75    #define MPIDR_UP     (1 << 30)
     76    const uint32_t mpidr = arm_cp15_get_multiprocessor_affinity();
     77    if ((mpidr & (MPIDR_MX_FMT | MPIDR_UP)) == MPIDR_MX_FMT) {
    7078      arm_cp15_tlb_invalidate_entry_all_asids(mva);
    7179    }
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