Index: cpukit/libpci/pci/access.h
===================================================================
--- cpukit/libpci/pci/access.h	(revision dc623099cac2000f332d7791bca858143a8bb027)
+++ cpukit/libpci/pci/access.h	(revision 15620f5b6b4d5de29512b3467af1dcb53b7b3057)
@@ -15,4 +15,5 @@
 #include <stdint.h>
 #include <libcpu/byteorder.h>
+#include <rtems/score/basedefs.h>
 #include <pci.h>
 
@@ -130,30 +131,30 @@
 
 /* Enable Memory in command register */
-static inline void pci_mem_enable(pci_dev_t dev)
+RTEMS_INLINE_ROUTINE void pci_mem_enable(pci_dev_t dev)
 {
 	pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, PCIM_CMD_MEMEN);
 }
 
-static inline void pci_mem_disable(pci_dev_t dev)
+RTEMS_INLINE_ROUTINE void pci_mem_disable(pci_dev_t dev)
 {
 	pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, 0);
 }
 
-static inline void pci_io_enable(pci_dev_t dev)
+RTEMS_INLINE_ROUTINE void pci_io_enable(pci_dev_t dev)
 {
 	pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, PCIM_CMD_PORTEN);
 }
 
-static inline void pci_io_disable(pci_dev_t dev)
+RTEMS_INLINE_ROUTINE void pci_io_disable(pci_dev_t dev)
 {
 	pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, 0);
 }
 
-static inline void pci_master_enable(pci_dev_t dev)
+RTEMS_INLINE_ROUTINE void pci_master_enable(pci_dev_t dev)
 {
 	pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, PCIM_CMD_BUSMASTEREN);
 }
 
-static inline void pci_master_disable(pci_dev_t dev)
+RTEMS_INLINE_ROUTINE void pci_master_disable(pci_dev_t dev)
 {
 	pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, 0);
@@ -181,5 +182,5 @@
 
 /* Translate PCI address into CPU accessible address */
-static inline int pci_pci2cpu(uint32_t *address, int type)
+RTEMS_INLINE_ROUTINE int pci_pci2cpu(uint32_t *address, int type)
 {
 	return pci_access_ops.translate(address, type, 0);
@@ -187,5 +188,5 @@
 
 /* Translate CPU accessible address into PCI address (for DMA) */
-static inline int pci_cpu2pci(uint32_t *address, int type)
+RTEMS_INLINE_ROUTINE int pci_cpu2pci(uint32_t *address, int type)
 {
 	return pci_access_ops.translate(address, type, 1);
@@ -194,10 +195,10 @@
 /*** Read/Write a register over PCI Memory Space ***/
 
-static inline uint8_t pci_ld8(volatile uint8_t *addr)
+RTEMS_INLINE_ROUTINE uint8_t pci_ld8(volatile uint8_t *addr)
 {
 	return *addr;
 }
 
-static inline void pci_st8(volatile uint8_t *addr, uint8_t val)
+RTEMS_INLINE_ROUTINE void pci_st8(volatile uint8_t *addr, uint8_t val)
 {
 	*addr = val;
@@ -208,40 +209,40 @@
 /* BSP has decided Big Endian PCI Bus (non-standard) */
 
-static inline uint16_t pci_ld_le16(volatile uint16_t *addr)
+RTEMS_INLINE_ROUTINE uint16_t pci_ld_le16(volatile uint16_t *addr)
 {
 	return ld_be16(addr);
 }
 
-static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val)
+RTEMS_INLINE_ROUTINE void pci_st_le16(volatile uint16_t *addr, uint16_t val)
 {
 	st_be16(addr, val);
 }
 
-static inline uint32_t pci_ld_le32(volatile uint32_t *addr)
+RTEMS_INLINE_ROUTINE uint32_t pci_ld_le32(volatile uint32_t *addr)
 {
 	return ld_be32(addr);
 }
 
-static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val)
+RTEMS_INLINE_ROUTINE void pci_st_le32(volatile uint32_t *addr, uint32_t val)
 {
 	st_be32(addr, val);
 }
 
-static inline uint16_t pci_ld_be16(volatile uint16_t *addr)
+RTEMS_INLINE_ROUTINE uint16_t pci_ld_be16(volatile uint16_t *addr)
 {
 	return ld_le16(addr);
 }
 
-static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val)
+RTEMS_INLINE_ROUTINE void pci_st_be16(volatile uint16_t *addr, uint16_t val)
 {
 	st_le16(addr, val);
 }
 
-static inline uint32_t pci_ld_be32(volatile uint32_t *addr)
+RTEMS_INLINE_ROUTINE uint32_t pci_ld_be32(volatile uint32_t *addr)
 {
 	return ld_le32(addr);
 }
 
-static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val)
+RTEMS_INLINE_ROUTINE void pci_st_be32(volatile uint32_t *addr, uint32_t val)
 {
 	st_le32(addr, val);
@@ -252,40 +253,40 @@
 /* Little Endian PCI Bus */
 
-static inline uint16_t pci_ld_le16(volatile uint16_t *addr)
+RTEMS_INLINE_ROUTINE uint16_t pci_ld_le16(volatile uint16_t *addr)
 {
 	return ld_le16(addr);
 }
 
-static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val)
+RTEMS_INLINE_ROUTINE void pci_st_le16(volatile uint16_t *addr, uint16_t val)
 {
 	st_le16(addr, val);
 }
 
-static inline uint32_t pci_ld_le32(volatile uint32_t *addr)
+RTEMS_INLINE_ROUTINE uint32_t pci_ld_le32(volatile uint32_t *addr)
 {
 	return ld_le32(addr);
 }
 
-static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val)
+RTEMS_INLINE_ROUTINE void pci_st_le32(volatile uint32_t *addr, uint32_t val)
 {
 	st_le32(addr, val);
 }
 
-static inline uint16_t pci_ld_be16(volatile uint16_t *addr)
+RTEMS_INLINE_ROUTINE uint16_t pci_ld_be16(volatile uint16_t *addr)
 {
 	return ld_be16(addr);
 }
 
-static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val)
+RTEMS_INLINE_ROUTINE void pci_st_be16(volatile uint16_t *addr, uint16_t val)
 {
 	st_be16(addr, val);
 }
 
-static inline uint32_t pci_ld_be32(volatile uint32_t *addr)
+RTEMS_INLINE_ROUTINE uint32_t pci_ld_be32(volatile uint32_t *addr)
 {
 	return ld_be32(addr);
 }
 
-static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val)
+RTEMS_INLINE_ROUTINE void pci_st_be32(volatile uint32_t *addr, uint32_t val)
 {
 	st_be32(addr, val);
Index: cpukit/libpci/pci/irq.h
===================================================================
--- cpukit/libpci/pci/irq.h	(revision dc623099cac2000f332d7791bca858143a8bb027)
+++ cpukit/libpci/pci/irq.h	(revision 15620f5b6b4d5de29512b3467af1dcb53b7b3057)
@@ -1,6 +1,3 @@
 /* PCI IRQ Library
- *
- * IRQ handling does not have so much with PCI to do, this library depends
- * on the BSP to implement shared interrupts.
  *
  * COPYRIGHT (c) 2010 Cobham Gaisler AB.
@@ -11,11 +8,17 @@
  */
 
+/* IRQ handling does not have so much with PCI to do, this library depends
+ * on the BSP to implement shared interrupts.
+ */
+
 #ifndef __PCI_IRQ_H__
 #define __PCI_IRQ_H__
 
 #include <bsp.h>
+#include <rtems/irq-extension.h>
+#include <rtems/score/basedefs.h>
 
 /* PCI Handler (ISR) called when IRQ is generated by any of the PCI devices
- * connected to the same PCI IRQ Pin. This is been defined the same way as
+ * connected to the same PCI IRQ Pin. This has been defined the same way as
  * rtems_interrupt_handler in order for BSPs to "direct-map" the register
  * and unregister functions rtems_interrupt_handler_install/remove
@@ -38,5 +41,5 @@
  *  arg       Second argument to function isr
  */
-static inline int pci_interrupt_register(int irq, const char *info,
+RTEMS_INLINE_ROUTINE int pci_interrupt_register(int irq, const char *info,
 						pci_isr isr, void *arg)
 {
@@ -51,5 +54,6 @@
  *  arg       Second argument to function isr
  */
-static inline int pci_interrupt_unregister(int irq, pci_isr isr, void *arg)
+RTEMS_INLINE_ROUTINE int pci_interrupt_unregister(int irq, pci_isr isr,
+						  void *arg)
 {
 	return BSP_PCI_shared_interrupt_unregister(irq, isr, arg);
@@ -67,5 +71,5 @@
  *  arg       Second argument to function isr
  */
-static inline void pci_interrupt_unmask(int irq)
+RTEMS_INLINE_ROUTINE void pci_interrupt_unmask(int irq)
 {
 	BSP_PCI_shared_interrupt_unmask(irq);
@@ -83,5 +87,5 @@
  *  arg       Second argument to function isr
  */
-static inline void pci_interrupt_mask(int irq)
+RTEMS_INLINE_ROUTINE void pci_interrupt_mask(int irq)
 {
 	BSP_PCI_shared_interrupt_mask(irq);
@@ -97,5 +101,5 @@
  *  arg       Second argument to function isr
  */
-static inline void pci_interrupt_clear(int irq)
+RTEMS_INLINE_ROUTINE void pci_interrupt_clear(int irq)
 {
 	BSP_PCI_shared_interrupt_clear(irq);
