Changeset 15620f5b in rtems for cpukit/libpci


Ignore:
Timestamp:
Apr 8, 2015, 8:03:45 AM (4 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, master
Children:
346a9a5
Parents:
dc623099
git-author:
Daniel Hellstrom <daniel@…> (04/08/15 08:03:45)
git-committer:
Daniel Hellstrom <daniel@…> (04/16/15 23:10:28)
Message:

LIBPCI: use RTEMS_INLINE_ROUTINE

Location:
cpukit/libpci/pci
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/libpci/pci/access.h

    rdc623099 r15620f5b  
    1515#include <stdint.h>
    1616#include <libcpu/byteorder.h>
     17#include <rtems/score/basedefs.h>
    1718#include <pci.h>
    1819
     
    130131
    131132/* Enable Memory in command register */
    132 static inline void pci_mem_enable(pci_dev_t dev)
     133RTEMS_INLINE_ROUTINE void pci_mem_enable(pci_dev_t dev)
    133134{
    134135        pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, PCIM_CMD_MEMEN);
    135136}
    136137
    137 static inline void pci_mem_disable(pci_dev_t dev)
     138RTEMS_INLINE_ROUTINE void pci_mem_disable(pci_dev_t dev)
    138139{
    139140        pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, 0);
    140141}
    141142
    142 static inline void pci_io_enable(pci_dev_t dev)
     143RTEMS_INLINE_ROUTINE void pci_io_enable(pci_dev_t dev)
    143144{
    144145        pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, PCIM_CMD_PORTEN);
    145146}
    146147
    147 static inline void pci_io_disable(pci_dev_t dev)
     148RTEMS_INLINE_ROUTINE void pci_io_disable(pci_dev_t dev)
    148149{
    149150        pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, 0);
    150151}
    151152
    152 static inline void pci_master_enable(pci_dev_t dev)
     153RTEMS_INLINE_ROUTINE void pci_master_enable(pci_dev_t dev)
    153154{
    154155        pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, PCIM_CMD_BUSMASTEREN);
    155156}
    156157
    157 static inline void pci_master_disable(pci_dev_t dev)
     158RTEMS_INLINE_ROUTINE void pci_master_disable(pci_dev_t dev)
    158159{
    159160        pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, 0);
     
    181182
    182183/* Translate PCI address into CPU accessible address */
    183 static inline int pci_pci2cpu(uint32_t *address, int type)
     184RTEMS_INLINE_ROUTINE int pci_pci2cpu(uint32_t *address, int type)
    184185{
    185186        return pci_access_ops.translate(address, type, 0);
     
    187188
    188189/* Translate CPU accessible address into PCI address (for DMA) */
    189 static inline int pci_cpu2pci(uint32_t *address, int type)
     190RTEMS_INLINE_ROUTINE int pci_cpu2pci(uint32_t *address, int type)
    190191{
    191192        return pci_access_ops.translate(address, type, 1);
     
    194195/*** Read/Write a register over PCI Memory Space ***/
    195196
    196 static inline uint8_t pci_ld8(volatile uint8_t *addr)
     197RTEMS_INLINE_ROUTINE uint8_t pci_ld8(volatile uint8_t *addr)
    197198{
    198199        return *addr;
    199200}
    200201
    201 static inline void pci_st8(volatile uint8_t *addr, uint8_t val)
     202RTEMS_INLINE_ROUTINE void pci_st8(volatile uint8_t *addr, uint8_t val)
    202203{
    203204        *addr = val;
     
    208209/* BSP has decided Big Endian PCI Bus (non-standard) */
    209210
    210 static inline uint16_t pci_ld_le16(volatile uint16_t *addr)
     211RTEMS_INLINE_ROUTINE uint16_t pci_ld_le16(volatile uint16_t *addr)
    211212{
    212213        return ld_be16(addr);
    213214}
    214215
    215 static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val)
     216RTEMS_INLINE_ROUTINE void pci_st_le16(volatile uint16_t *addr, uint16_t val)
    216217{
    217218        st_be16(addr, val);
    218219}
    219220
    220 static inline uint32_t pci_ld_le32(volatile uint32_t *addr)
     221RTEMS_INLINE_ROUTINE uint32_t pci_ld_le32(volatile uint32_t *addr)
    221222{
    222223        return ld_be32(addr);
    223224}
    224225
    225 static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val)
     226RTEMS_INLINE_ROUTINE void pci_st_le32(volatile uint32_t *addr, uint32_t val)
    226227{
    227228        st_be32(addr, val);
    228229}
    229230
    230 static inline uint16_t pci_ld_be16(volatile uint16_t *addr)
     231RTEMS_INLINE_ROUTINE uint16_t pci_ld_be16(volatile uint16_t *addr)
    231232{
    232233        return ld_le16(addr);
    233234}
    234235
    235 static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val)
     236RTEMS_INLINE_ROUTINE void pci_st_be16(volatile uint16_t *addr, uint16_t val)
    236237{
    237238        st_le16(addr, val);
    238239}
    239240
    240 static inline uint32_t pci_ld_be32(volatile uint32_t *addr)
     241RTEMS_INLINE_ROUTINE uint32_t pci_ld_be32(volatile uint32_t *addr)
    241242{
    242243        return ld_le32(addr);
    243244}
    244245
    245 static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val)
     246RTEMS_INLINE_ROUTINE void pci_st_be32(volatile uint32_t *addr, uint32_t val)
    246247{
    247248        st_le32(addr, val);
     
    252253/* Little Endian PCI Bus */
    253254
    254 static inline uint16_t pci_ld_le16(volatile uint16_t *addr)
     255RTEMS_INLINE_ROUTINE uint16_t pci_ld_le16(volatile uint16_t *addr)
    255256{
    256257        return ld_le16(addr);
    257258}
    258259
    259 static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val)
     260RTEMS_INLINE_ROUTINE void pci_st_le16(volatile uint16_t *addr, uint16_t val)
    260261{
    261262        st_le16(addr, val);
    262263}
    263264
    264 static inline uint32_t pci_ld_le32(volatile uint32_t *addr)
     265RTEMS_INLINE_ROUTINE uint32_t pci_ld_le32(volatile uint32_t *addr)
    265266{
    266267        return ld_le32(addr);
    267268}
    268269
    269 static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val)
     270RTEMS_INLINE_ROUTINE void pci_st_le32(volatile uint32_t *addr, uint32_t val)
    270271{
    271272        st_le32(addr, val);
    272273}
    273274
    274 static inline uint16_t pci_ld_be16(volatile uint16_t *addr)
     275RTEMS_INLINE_ROUTINE uint16_t pci_ld_be16(volatile uint16_t *addr)
    275276{
    276277        return ld_be16(addr);
    277278}
    278279
    279 static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val)
     280RTEMS_INLINE_ROUTINE void pci_st_be16(volatile uint16_t *addr, uint16_t val)
    280281{
    281282        st_be16(addr, val);
    282283}
    283284
    284 static inline uint32_t pci_ld_be32(volatile uint32_t *addr)
     285RTEMS_INLINE_ROUTINE uint32_t pci_ld_be32(volatile uint32_t *addr)
    285286{
    286287        return ld_be32(addr);
    287288}
    288289
    289 static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val)
     290RTEMS_INLINE_ROUTINE void pci_st_be32(volatile uint32_t *addr, uint32_t val)
    290291{
    291292        st_be32(addr, val);
  • cpukit/libpci/pci/irq.h

    rdc623099 r15620f5b  
    11/* PCI IRQ Library
    2  *
    3  * IRQ handling does not have so much with PCI to do, this library depends
    4  * on the BSP to implement shared interrupts.
    52 *
    63 * COPYRIGHT (c) 2010 Cobham Gaisler AB.
     
    118 */
    129
     10/* IRQ handling does not have so much with PCI to do, this library depends
     11 * on the BSP to implement shared interrupts.
     12 */
     13
    1314#ifndef __PCI_IRQ_H__
    1415#define __PCI_IRQ_H__
    1516
    1617#include <bsp.h>
     18#include <rtems/irq-extension.h>
     19#include <rtems/score/basedefs.h>
    1720
    1821/* PCI Handler (ISR) called when IRQ is generated by any of the PCI devices
    19  * connected to the same PCI IRQ Pin. This is been defined the same way as
     22 * connected to the same PCI IRQ Pin. This has been defined the same way as
    2023 * rtems_interrupt_handler in order for BSPs to "direct-map" the register
    2124 * and unregister functions rtems_interrupt_handler_install/remove
     
    3841 *  arg       Second argument to function isr
    3942 */
    40 static inline int pci_interrupt_register(int irq, const char *info,
     43RTEMS_INLINE_ROUTINE int pci_interrupt_register(int irq, const char *info,
    4144                                                pci_isr isr, void *arg)
    4245{
     
    5154 *  arg       Second argument to function isr
    5255 */
    53 static inline int pci_interrupt_unregister(int irq, pci_isr isr, void *arg)
     56RTEMS_INLINE_ROUTINE int pci_interrupt_unregister(int irq, pci_isr isr,
     57                                                  void *arg)
    5458{
    5559        return BSP_PCI_shared_interrupt_unregister(irq, isr, arg);
     
    6771 *  arg       Second argument to function isr
    6872 */
    69 static inline void pci_interrupt_unmask(int irq)
     73RTEMS_INLINE_ROUTINE void pci_interrupt_unmask(int irq)
    7074{
    7175        BSP_PCI_shared_interrupt_unmask(irq);
     
    8387 *  arg       Second argument to function isr
    8488 */
    85 static inline void pci_interrupt_mask(int irq)
     89RTEMS_INLINE_ROUTINE void pci_interrupt_mask(int irq)
    8690{
    8791        BSP_PCI_shared_interrupt_mask(irq);
     
    97101 *  arg       Second argument to function isr
    98102 */
    99 static inline void pci_interrupt_clear(int irq)
     103RTEMS_INLINE_ROUTINE void pci_interrupt_clear(int irq)
    100104{
    101105        BSP_PCI_shared_interrupt_clear(irq);
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