Index: c/src/lib/libbsp/arm/beagle/Makefile.am
===================================================================
--- c/src/lib/libbsp/arm/beagle/Makefile.am	(revision b09a578e8ad4583a97349f866e981980f0ff6ade)
+++ c/src/lib/libbsp/arm/beagle/Makefile.am	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
@@ -40,4 +40,6 @@
 include_bsp_HEADERS += include/irq.h
 include_bsp_HEADERS += include/i2c.h
+include_bsp_HEADERS += include/beagleboneblack.h
+include_bsp_HEADERS += include/bbb-gpio.h
 
 include_libcpu_HEADERS =
@@ -83,4 +85,5 @@
 libbsp_a_SOURCES += ../../shared/sbrk.c
 libbsp_a_SOURCES += ../../shared/src/stackalloc.c
+libbsp_a_SOURCES += ../../shared/gpio.c
 libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
 libbsp_a_SOURCES += ../../shared/timerstub.c
@@ -115,4 +118,7 @@
 libbsp_a_SOURCES += misc/i2c.c
 
+# GPIO
+libbsp_a_SOURCES += gpio/bbb-gpio.c
+
 #RTC
 libbsp_a_SOURCES += rtc.c
Index: c/src/lib/libbsp/arm/beagle/gpio/bbb-gpio.c
===================================================================
--- c/src/lib/libbsp/arm/beagle/gpio/bbb-gpio.c	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
+++ c/src/lib/libbsp/arm/beagle/gpio/bbb-gpio.c	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
@@ -0,0 +1,564 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief Support for the BeagleBone Black.
+ */
+
+/**
+ * Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/* BSP specific function definitions for BeagleBone Black.
+ * It is totally beased on Generic GPIO API definition. 
+ * For more details related to GPIO API please have a 
+ * look at libbbsp/shared/include/gpio.h
+ */
+
+#include <bsp/beagleboneblack.h>
+#include <bsp/irq-generic.h>
+#include <bsp/gpio.h>
+#include <bsp/bbb-gpio.h>
+#include <libcpu/am335x.h>
+
+#include <assert.h>
+#include <stdlib.h>
+
+/* Currently these definitions are for BeagleBone Black board only
+ * Later on Beagle-xM board support can be added in this code.
+ * After support gets added if condition should be removed
+ */
+#if IS_AM335X
+
+static const uint32_t gpio_bank_addrs[] = 
+  { AM335X_GPIO0_BASE,
+  	AM335X_GPIO1_BASE, 
+  	AM335X_GPIO2_BASE, 
+  	AM335X_GPIO3_BASE };
+
+static const rtems_vector_number gpio_bank_vector[] =
+  { AM335X_INT_GPIOINT0A,
+  	AM335X_INT_GPIOINT1A,
+  	AM335X_INT_GPIOINT2A,
+  	AM335X_INT_GPIOINT3A };
+
+/* Macro for the gpio pin not having control module offset mapping */
+#define CONF_NOT_DEFINED 0x00000000
+
+/* Mapping of gpio pin nuber to the  Control module mapped register offset */
+static const uint32_t gpio_pad_conf[GPIO_BANK_COUNT][BSP_GPIO_PINS_PER_BANK] =
+{
+  /* GPIO Module 0 */
+  { CONF_NOT_DEFINED,             /* GPIO0[0] */
+    CONF_NOT_DEFINED,             /* GPIO0[1] */
+    AM335X_CONF_SPI0_SCLK,        /* GPIO0[2] */
+    AM335X_CONF_SPI0_D0,          /* GPIO0[3] */
+    AM335X_CONF_SPI0_D1,          /* GPIO0[4] */
+    AM335X_CONF_SPI0_CS0,         /* GPIO0[5] */
+    CONF_NOT_DEFINED,             /* GPIO0[6] */
+    CONF_NOT_DEFINED,             /* GPIO0[7] */
+    AM335X_CONF_LCD_DATA12,       /* GPIO0[8] */
+    AM335X_CONF_LCD_DATA13,       /* GPIO0[9] */
+    AM335X_CONF_LCD_DATA14,       /* GPIO0[10] */
+    AM335X_CONF_LCD_DATA15,       /* GPIO0[11] */
+    AM335X_CONF_UART1_CTSN,       /* GPIO0[12] */
+    AM335X_CONF_UART1_RTSN,       /* GPIO0[13] */
+    AM335X_CONF_UART1_RXD,        /* GPIO0[14] */
+    AM335X_CONF_UART1_TXD,        /* GPIO0[15] */
+    CONF_NOT_DEFINED,             /* GPIO0[16] */
+    CONF_NOT_DEFINED,             /* GPIO0[17] */
+    CONF_NOT_DEFINED,             /* GPIO0[18] */
+    CONF_NOT_DEFINED,             /* GPIO0[19] */
+    CONF_NOT_DEFINED,             /* GPIO0[20] */
+    CONF_NOT_DEFINED,             /* GPIO0[21] */
+    AM335X_CONF_GPMC_AD8,         /* GPIO0[22] */
+    AM335X_CONF_GPMC_AD9,         /* GPIO0[23] */
+    CONF_NOT_DEFINED,             /* GPIO0[24] */
+    CONF_NOT_DEFINED,             /* GPIO0[25] */
+    AM335X_CONF_GPMC_AD10,        /* GPIO0[26] */
+    AM335X_CONF_GPMC_AD11,        /* GPIO0[27] */
+    CONF_NOT_DEFINED,             /* GPIO0[28] */
+    CONF_NOT_DEFINED,             /* GPIO0[29] */
+    AM335X_CONF_GPMC_WAIT0,       /* GPIO0[30] */
+    AM335X_CONF_GPMC_WPN          /* GPIO0[31] */ },
+  
+  /* GPIO Module 1 */
+  { AM335X_CONF_GPMC_AD0,         /* GPIO1[0] */
+    AM335X_CONF_GPMC_AD1,         /* GPIO1[1] */
+    AM335X_CONF_GPMC_AD2,         /* GPIO1[2] */
+    AM335X_CONF_GPMC_AD3,         /* GPIO1[3] */
+    AM335X_CONF_GPMC_AD4,         /* GPIO1[4] */
+    AM335X_CONF_GPMC_AD5,         /* GPIO1[5] */
+    AM335X_CONF_GPMC_AD6,         /* GPIO1[6] */
+    AM335X_CONF_GPMC_AD7,         /* GPIO1[7] */
+    CONF_NOT_DEFINED,             /* GPIO1[8] */
+    CONF_NOT_DEFINED,             /* GPIO1[9] */
+    CONF_NOT_DEFINED,             /* GPIO1[10] */
+    CONF_NOT_DEFINED,             /* GPIO1[11] */
+    AM335X_CONF_GPMC_AD12,        /* GPIO1[12] */
+    AM335X_CONF_GPMC_AD13,        /* GPIO1[13] */
+    AM335X_CONF_GPMC_AD14,        /* GPIO1[14] */
+    AM335X_CONF_GPMC_AD15,        /* GPIO1[15] */
+    AM335X_CONF_GPMC_A0,          /* GPIO1[16] */
+    AM335X_CONF_GPMC_A1,          /* GPIO1[17] */
+    AM335X_CONF_GPMC_A2,          /* GPIO1[18] */
+    AM335X_CONF_GPMC_A3,          /* GPIO1[19] */
+    CONF_NOT_DEFINED,             /* GPIO1[20] */
+    CONF_NOT_DEFINED,             /* GPIO1[21] */
+    CONF_NOT_DEFINED,             /* GPIO1[22] */
+    CONF_NOT_DEFINED,             /* GPIO1[23] */
+    CONF_NOT_DEFINED,             /* GPIO1[24] */
+    CONF_NOT_DEFINED,             /* GPIO1[25] */
+    CONF_NOT_DEFINED,             /* GPIO1[26] */
+    CONF_NOT_DEFINED,             /* GPIO1[27] */
+    AM335X_CONF_GPMC_BEN1,        /* GPIO1[28] */
+    AM335X_CONF_GPMC_CSN0,        /* GPIO1[29] */
+    AM335X_CONF_GPMC_CSN1,        /* GPIO1[30] */
+    AM335X_CONF_GPMC_CSN2         /* GPIO1[31] */ },
+
+  /* GPIO Module 2 */
+  { CONF_NOT_DEFINED,             /* GPIO2[0] */
+    AM335X_CONF_GPMC_CLK,         /* GPIO2[1] */
+    AM335X_CONF_GPMC_ADVN_ALE,    /* GPIO2[2] */
+    AM335X_CONF_GPMC_OEN_REN,     /* GPIO2[3] */
+    AM335X_CONF_GPMC_WEN,         /* GPIO2[4] */
+    AM335X_CONF_GPMC_BEN0_CLE,    /* GPIO2[5] */
+    AM335X_CONF_LCD_DATA0,        /* GPIO2[6] */
+    AM335X_CONF_LCD_DATA1,        /* GPIO2[7] */
+    AM335X_CONF_LCD_DATA2,        /* GPIO2[8] */
+    AM335X_CONF_LCD_DATA3,        /* GPIO2[9] */
+    AM335X_CONF_LCD_DATA4,        /* GPIO2[10] */
+    AM335X_CONF_LCD_DATA5,        /* GPIO2[11] */
+    AM335X_CONF_LCD_DATA6,        /* GPIO2[12] */
+    AM335X_CONF_LCD_DATA7,        /* GPIO2[13] */
+    AM335X_CONF_LCD_DATA8,        /* GPIO2[14] */
+    AM335X_CONF_LCD_DATA9,        /* GPIO2[15] */
+    AM335X_CONF_LCD_DATA10,       /* GPIO2[16] */
+    AM335X_CONF_LCD_DATA11,       /* GPIO2[17] */
+    CONF_NOT_DEFINED,             /* GPIO2[18] */
+    CONF_NOT_DEFINED,             /* GPIO2[19] */
+    CONF_NOT_DEFINED,             /* GPIO2[20] */
+    CONF_NOT_DEFINED,             /* GPIO2[21] */
+    AM335X_CONF_LCD_VSYNC,        /* GPIO2[22] */
+    AM335X_CONF_LCD_HSYNC,        /* GPIO2[23] */
+    AM335X_CONF_LCD_PCLK,         /* GPIO2[24] */
+    AM335X_CONF_LCD_AC_BIAS_EN    /* GPIO2[25] */ },
+
+  /* GPIO Module 3 */
+  { CONF_NOT_DEFINED,             /* GPIO3[0] */
+    CONF_NOT_DEFINED,             /* GPIO3[1] */
+    CONF_NOT_DEFINED,             /* GPIO3[2] */
+    CONF_NOT_DEFINED,             /* GPIO3[3] */
+    CONF_NOT_DEFINED,             /* GPIO3[4] */
+    CONF_NOT_DEFINED,             /* GPIO3[5] */
+    CONF_NOT_DEFINED,             /* GPIO3[6] */
+    CONF_NOT_DEFINED,             /* GPIO3[7] */
+    CONF_NOT_DEFINED,             /* GPIO3[8] */
+    CONF_NOT_DEFINED,             /* GPIO3[9] */
+    CONF_NOT_DEFINED,             /* GPIO3[10] */
+    CONF_NOT_DEFINED,             /* GPIO3[11] */
+    CONF_NOT_DEFINED,             /* GPIO3[12] */
+    CONF_NOT_DEFINED,             /* GPIO3[13] */
+    AM335X_CONF_MCASP0_ACLKX,     /* GPIO3[14] */
+    AM335X_CONF_MCASP0_FSX,       /* GPIO3[15] */
+    AM335X_CONF_MCASP0_AXR0,      /* GPIO3[16] */
+    AM335X_CONF_MCASP0_AHCLKR,    /* GPIO3[17] */
+    CONF_NOT_DEFINED,             /* GPIO3[18] */
+    AM335X_CONF_MCASP0_FSR,       /* GPIO3[19] */
+    CONF_NOT_DEFINED,             /* GPIO3[20] */
+    AM335X_CONF_MCASP0_AHCLKX     /* GPIO3[21] */ }
+};
+
+/* Get the address of Base Register + Offset for pad config */
+uint32_t static inline bbb_conf_reg(uint32_t bank, uint32_t pin)
+{
+  return (AM335X_PADCONF_BASE + gpio_pad_conf[bank][pin]);
+}
+
+/* Get the value of Base Register + Offset */
+uint32_t static inline bbb_reg(uint32_t bank, uint32_t reg)
+{
+  return (gpio_bank_addrs[bank] + reg);
+}
+
+static rtems_status_code bbb_select_pin_function(
+  uint32_t bank,
+  uint32_t pin,
+  uint32_t type
+) {
+
+  if ( type == BBB_DIGITAL_IN ) {
+    mmio_set(bbb_reg(bank, AM335X_GPIO_OE), BIT(pin));
+  } else {
+    mmio_clear(bbb_reg(bank, AM335X_GPIO_OE), BIT(pin));
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_gpio_bsp_multi_set(uint32_t bank, uint32_t bitmask)
+{
+  mmio_set(bbb_reg(bank, AM335X_GPIO_SETDATAOUT), bitmask);
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask)
+{
+  mmio_set(bbb_reg(bank, AM335X_GPIO_CLEARDATAOUT), bitmask);
+
+  return RTEMS_SUCCESSFUL;
+}
+
+uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask)
+{
+  return (bbb_reg(bank, AM335X_GPIO_DATAIN) & bitmask);
+}
+
+rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin)
+{
+  mmio_set(bbb_reg(bank, AM335X_GPIO_SETDATAOUT), BIT(pin));
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin)
+{
+  mmio_set(bbb_reg(bank, AM335X_GPIO_CLEARDATAOUT), BIT(pin));
+
+  return RTEMS_SUCCESSFUL;
+}
+
+uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin)
+{
+  return (mmio_read(bbb_reg(bank, AM335X_GPIO_DATAIN)) & BIT(pin));
+}
+
+rtems_status_code rtems_gpio_bsp_select_input(
+  uint32_t bank,
+  uint32_t pin,
+  void *bsp_specific
+) {
+  return bbb_select_pin_function(bank, pin, BBB_DIGITAL_IN);
+}
+
+rtems_status_code rtems_gpio_bsp_select_output(
+  uint32_t bank,
+  uint32_t pin,
+  void *bsp_specific
+) {
+  return bbb_select_pin_function(bank, pin, BBB_DIGITAL_OUT);
+}
+
+rtems_status_code rtems_bsp_select_specific_io(
+  uint32_t bank,
+  uint32_t pin,
+  uint32_t function,
+  void *pin_data
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_gpio_bsp_set_resistor_mode(
+  uint32_t bank,
+  uint32_t pin,
+  rtems_gpio_pull_mode mode
+) {
+  /* TODO: Add support for setting up resistor moode */
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank)
+{
+  return gpio_bank_vector[bank];
+}
+
+uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector)
+{
+  uint32_t event_status;
+  uint8_t bank_nr = 0;
+
+  /* Following loop will get the bank number from vector number */
+  while (bank_nr < GPIO_BANK_COUNT && vector != gpio_bank_vector[bank_nr])
+  {
+  	bank_nr++;
+  }
+
+  /* Retrieve the interrupt event status. */
+  event_status = mmio_read(bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0));
+
+  /* Clear the interrupt line. */
+  mmio_write(
+    (bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0)), event_status);
+  
+  return event_status;
+}
+
+rtems_status_code rtems_bsp_enable_interrupt(
+  uint32_t bank,
+  uint32_t pin,
+  rtems_gpio_interrupt interrupt
+) {
+  
+  /* Enable IRQ generation for the specific pin */
+  mmio_set(bbb_reg(bank, AM335X_GPIO_IRQSTATUS_SET_0), BIT(pin));
+  
+  switch ( interrupt ) {
+    case FALLING_EDGE:
+      /* Enables asynchronous falling edge detection. */
+      mmio_set(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
+      break;
+    case RISING_EDGE:
+      /* Enables asynchronous rising edge detection. */
+      mmio_set(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
+      break;
+    case BOTH_EDGES:
+      /* Enables asynchronous falling edge detection. */
+      mmio_set(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
+
+      /* Enables asynchronous rising edge detection. */
+      mmio_set(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
+      break;
+    case LOW_LEVEL:
+      /* Enables pin low level detection. */
+      mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
+      break;
+    case HIGH_LEVEL:
+       /* Enables pin high level detection. */
+      mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
+      break;
+    case BOTH_LEVELS:
+      /* Enables pin low level detection. */
+      mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
+
+      /* Enables pin high level detection. */
+      mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
+      break;
+    case NONE:
+    default:
+      return RTEMS_UNSATISFIED;
+  }
+
+  /* The detection starts after 5 clock cycles as per AM335X TRM
+   * This period is required to clean the synchronization edge/
+   * level detection pipeline
+   */
+  asm volatile("nop"); asm volatile("nop"); asm volatile("nop");
+  asm volatile("nop"); asm volatile("nop");
+  
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_bsp_disable_interrupt(
+  uint32_t bank,
+  uint32_t pin,
+  rtems_gpio_interrupt interrupt
+) {
+  /* Clear IRQ generation for the specific pin */
+  mmio_set(bbb_reg(bank, AM335X_GPIO_IRQSTATUS_CLR_0), BIT(pin));
+
+  switch ( interrupt ) {
+    case FALLING_EDGE:
+      /* Disables asynchronous falling edge detection. */
+      mmio_clear(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
+      break;
+    case RISING_EDGE:
+      /* Disables asynchronous rising edge detection. */
+      mmio_clear(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
+      break;
+    case BOTH_EDGES:
+      /* Disables asynchronous falling edge detection. */
+      mmio_clear(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin));
+
+      /* Disables asynchronous rising edge detection. */
+      mmio_clear(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin));
+      break;
+    case LOW_LEVEL:
+      /* Disables pin low level detection. */
+      mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
+      break;
+    case HIGH_LEVEL:
+      /* Disables pin high level detection. */
+       mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
+      break;
+    case BOTH_LEVELS:
+      /* Disables pin low level detection. */
+      mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin));
+
+      /* Disables pin high level detection. */
+      mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin));
+      break;
+    case NONE:
+    default:
+      return RTEMS_UNSATISFIED;
+  }
+
+  /* The detection starts after 5 clock cycles as per AM335X TRM
+   * This period is required to clean the synchronization edge/
+   * level detection pipeline
+   */
+  asm volatile("nop"); asm volatile("nop"); asm volatile("nop");
+  asm volatile("nop"); asm volatile("nop");
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_gpio_bsp_multi_select(
+  rtems_gpio_multiple_pin_select *pins,
+  uint32_t pin_count,
+  uint32_t select_bank
+) {
+  uint32_t register_address;
+  uint32_t select_register;
+  uint8_t i;
+
+  register_address = gpio_bank_addrs[select_bank] + AM335X_GPIO_OE;
+
+  select_register = REG(register_address);
+
+  for ( i = 0; i < pin_count; ++i ) {
+    if ( pins[i].function == DIGITAL_INPUT ) {
+      select_register |= BIT(pins[i].pin_number);
+    } else if ( pins[i].function == DIGITAL_OUTPUT ) {
+      select_register &= ~BIT(pins[i].pin_number);
+    } else { /* BSP_SPECIFIC function. */
+      return RTEMS_NOT_DEFINED;
+    }
+  }
+
+  REG(register_address) = select_register;
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code rtems_gpio_bsp_specific_group_operation(
+  uint32_t bank,
+  uint32_t *pins,
+  uint32_t pin_count,
+  void *arg
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+#endif /* IS_AM335X */
+
+/* For support of BeagleboardxM */
+#if IS_DM3730
+
+/* Currently this section is just to satisfy
+ * GPIO API and to make the build successful.
+ * Later on support can be added here.
+ */
+
+rtems_status_code rtems_gpio_bsp_multi_set(uint32_t bank, uint32_t bitmask)
+{
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask)
+{
+  return RTEMS_NOT_DEFINED;
+}
+
+uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask)
+{
+  return -1;
+}
+
+rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin)
+{
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin)
+{
+  return RTEMS_NOT_DEFINED;
+}
+
+uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin)
+{
+  return -1;
+}
+
+rtems_status_code rtems_gpio_bsp_select_input(
+  uint32_t bank,
+  uint32_t pin,
+  void *bsp_specific
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_gpio_bsp_select_output(
+  uint32_t bank,
+  uint32_t pin,
+  void *bsp_specific
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_bsp_select_specific_io(
+  uint32_t bank,
+  uint32_t pin,
+  uint32_t function,
+  void *pin_data
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_gpio_bsp_set_resistor_mode(
+  uint32_t bank,
+  uint32_t pin,
+  rtems_gpio_pull_mode mode
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank)
+{
+  return -1;
+}
+
+uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector)
+{
+  return -1;
+}
+
+rtems_status_code rtems_bsp_enable_interrupt(
+  uint32_t bank,
+  uint32_t pin,
+  rtems_gpio_interrupt interrupt
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_bsp_disable_interrupt(
+  uint32_t bank,
+  uint32_t pin,
+  rtems_gpio_interrupt interrupt
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_gpio_bsp_multi_select(
+  rtems_gpio_multiple_pin_select *pins,
+  uint32_t pin_count,
+  uint32_t select_bank
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+rtems_status_code rtems_gpio_bsp_specific_group_operation(
+  uint32_t bank,
+  uint32_t *pins,
+  uint32_t pin_count,
+  void *arg
+) {
+  return RTEMS_NOT_DEFINED;
+}
+
+#endif /* IS_DM3730 */
Index: c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h
===================================================================
--- c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
+++ c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
@@ -0,0 +1,43 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black BSP definitions.
+ */
+
+/**
+ * Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BBB_GPIO_H
+#define LIBBSP_ARM_BEAGLE_BBB_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief  BeagleBone Black GPIO functions.
+ */
+#define BBB_DIGITAL_IN  2
+#define BBB_DIGITAL_OUT 1
+
+/**
+ * @brief  BeagleBone Black GPIO pad configuration.
+ */
+#define BBB_PUDEN (1 << 3)
+#define BBB_PUDDIS ~BBB_PUDEN
+#define BBB_PU_EN (1 << 4)
+#define BBB_PD_EN ~BBB_PU_EN
+#define BBB_MUXMODE(X) (X & 0x7)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_BEAGLE_BBB_GPIO_H */
Index: c/src/lib/libbsp/arm/beagle/include/beagleboneblack.h
===================================================================
--- c/src/lib/libbsp/arm/beagle/include/beagleboneblack.h	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
+++ c/src/lib/libbsp/arm/beagle/include/beagleboneblack.h	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
@@ -0,0 +1,72 @@
+/**
+ * @file
+ *
+ * @ingroup arm_beagle
+ *
+ * @brief BeagleBone Black BSP definitions.
+ */
+
+/**
+ * Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H
+#define LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H
+
+/* In general GPIOs of BeagleBone Black/White can be addressed
+ * using two 46-pin dual-row expansion connectors P9 and P8,
+ * which are also known as Expansion A and Expansion B Connectors,
+ * respectively.
+ *
+ * Each Expansion Connector consists of 23 pins. So 2x23 pins would
+ * be available. It has 4 GPIO Banks each consists of 32 pins each.
+ * Toatal number of pins are 128 (32x4).
+ *
+ * So for mapping between generalized pin name and the unique pin
+ * numbers in this header file Macros are declared.
+ */
+
+/* USER LEDs of BeagleBone Black */
+#define BBB_LED_USR0  53 /* USR LED0 */
+#define BBB_LED_USR1  54 /* USR LED1 */
+#define BBB_LED_USR2  55 /* USR LED2 */
+#define BBB_LED_USR3  56 /* USR LED3 */
+
+/* Header P8 of BeagleBone Black */
+#define BBB_P8_7      66 /* GPIO2_2 */
+#define BBB_P8_8      67 /* GPIO2_3 */
+#define BBB_P8_9      69 /* GPIO2_5 */
+#define BBB_P8_10     68 /* GPIO2_4 */
+#define BBB_P8_11     45 /* GPIO1_13 */
+#define BBB_P8_12     44 /* GPIO1_12 */
+#define BBB_P8_13     23 /* GPIO0_23 */
+#define BBB_P8_14     26 /* GPIO0_26 */
+#define BBB_P8_15     47 /* GPIO1_15 */
+#define BBB_P8_16     46 /* GPIO1_14 */
+#define BBB_P8_17     27 /* GPIO0_27 */
+#define BBB_P8_18     65 /* GPIO2_1 */
+#define BBB_P8_19     22 /* GPIO0_22 */
+#define BBB_P8_26     61 /* GPIO1_29 */
+	
+/* Header P9 of BeagleBone Black */
+#define BBB_P9_11     30 /* GPIO0_30 */
+#define BBB_P9_12     60 /* GPIO1_28 */
+#define BBB_P9_13     31 /* GPIO0_31 */
+#define BBB_P9_14     50 /* GPIO1_18 */
+#define BBB_P9_15     48 /* GPIO1_16 */
+#define BBB_P9_16     51 /* GPIO1_19 */
+#define BBB_P9_17      5 /* GPIO0_5 */
+#define BBB_P9_18      4 /* GPIO0_4 */
+#define BBB_P9_23     49 /* GPIO1_17 */
+#define BBB_P9_24     15 /* GPIO0_15 */
+#define BBB_P9_26     14 /* GPIO1_14 */
+#define BBB_P9_27     115/* GPIO3_19 */
+#define BBB_P9_30     112/* GPIO3_16 */
+#define BBB_P9_41     20 /* GPIO0_20 */
+#define BBB_P9_42      7 /* GPIO0_7 */
+
+#endif /* LIBBSP_ARM_BEAGLE_GPIO_H */
Index: c/src/lib/libbsp/arm/beagle/include/bsp.h
===================================================================
--- c/src/lib/libbsp/arm/beagle/include/bsp.h	(revision b09a578e8ad4583a97349f866e981980f0ff6ade)
+++ c/src/lib/libbsp/arm/beagle/include/bsp.h	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
@@ -32,4 +32,5 @@
 #include <bsp/start.h>
 #include <bsp/default-initial-extension.h>
+#include <bsp/beagleboneblack.h>
 
 #include <rtems.h>
@@ -168,4 +169,15 @@
 #define BEAGLE_BASE_UART_2      0x4806C000
 #define BEAGLE_BASE_UART_3      0x49020000
+#endif
+
+/* GPIO pin config */
+#if IS_AM335X
+#define BSP_GPIO_PIN_COUNT 128
+#define BSP_GPIO_PINS_PER_BANK 32
+#endif
+
+#if IS_DM3730
+#define BSP_GPIO_PIN_COUNT 192
+#define BSP_GPIO_PINS_PER_BANK 32
 #endif
 
Index: c/src/lib/libbsp/arm/beagle/preinstall.am
===================================================================
--- c/src/lib/libbsp/arm/beagle/preinstall.am	(revision b09a578e8ad4583a97349f866e981980f0ff6ade)
+++ c/src/lib/libbsp/arm/beagle/preinstall.am	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
@@ -111,4 +111,12 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2c.h
 
+$(PROJECT_INCLUDE)/bsp/beagleboneblack.h: include/beagleboneblack.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/beagleboneblack.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/beagleboneblack.h
+
+$(PROJECT_INCLUDE)/bsp/bbb-gpio.h: include/bbb-gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bbb-gpio.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bbb-gpio.h
+
 $(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
Index: c/src/lib/libcpu/arm/shared/include/am335x.h
===================================================================
--- c/src/lib/libcpu/arm/shared/include/am335x.h	(revision b09a578e8ad4583a97349f866e981980f0ff6ade)
+++ c/src/lib/libcpu/arm/shared/include/am335x.h	(revision 151e53feabbe8ebdcbb491f06afeee8ea596ed6c)
@@ -301,2 +301,170 @@
 #define AM335X_RTC_KICK0_KEY    0x83E70B13
 #define AM335X_RTC_KICK1_KEY    0x95A4F1E0
+
+/* GPIO memory-mapped registers */
+
+#define AM335X_GPIO0_BASE           0x44E07000
+    /* GPIO Bank 0 base Register */
+#define AM335X_GPIO1_BASE           0x4804C000
+    /* GPIO Bank 1 base Register */
+#define AM335X_GPIO2_BASE           0x481AC000
+    /* GPIO Bank 2 base Register */
+#define AM335X_GPIO3_BASE           0x481AE000
+    /* GPIO Bank 3 base Register */
+
+#define AM335X_GPIO_REVISION        0x00
+#define AM335X_GPIO_SYSCONFIG       0x10
+#define AM335X_GPIO_EOI             0x20
+#define AM335X_GPIO_IRQSTATUS_RAW_0 0x24
+#define AM335X_GPIO_IRQSTATUS_RAW_1 0x28
+#define AM335X_GPIO_IRQSTATUS_0     0x2C
+#define AM335X_GPIO_IRQSTATUS_1     0x30
+#define AM335X_GPIO_IRQSTATUS_SET_0 0x34
+#define AM335X_GPIO_IRQSTATUS_SET_1 0x38
+#define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C
+#define AM335X_GPIO_IRQSTATUS_CLR_1 0x40
+#define AM335X_GPIO_IRQWAKEN_0      0x44
+#define AM335X_GPIO_IRQWAKEN_1      0x48
+#define AM335X_GPIO_SYSSTATUS       0x114
+#define AM335X_GPIO_CTRL            0x130
+#define AM335X_GPIO_OE              0x134
+#define AM335X_GPIO_DATAIN          0x138
+#define AM335X_GPIO_DATAOUT         0x13C
+#define AM335X_GPIO_LEVELDETECT0    0x140
+#define AM335X_GPIO_LEVELDETECT1    0x144
+#define AM335X_GPIO_RISINGDETECT    0x148
+#define AM335X_GPIO_FALLINGDETECT   0x14C
+#define AM335X_GPIO_DEBOUNCENABLE   0x150
+#define AM335X_GPIO_DEBOUNCINGTIME  0x154
+#define AM335X_GPIO_CLEARDATAOUT    0x190
+#define AM335X_GPIO_SETDATAOUT      0x194
+
+/* AM335X Pad Configuration Register Base */
+#define AM335X_PADCONF_BASE 0x44E10000
+
+/* Memory mapped register offset for Control Module */
+#define AM335X_CONF_GPMC_AD0 0x800
+#define AM335X_CONF_GPMC_AD1 0x804
+#define AM335X_CONF_GPMC_AD2 0x808
+#define AM335X_CONF_GPMC_AD3 0x80C
+#define AM335X_CONF_GPMC_AD4 0x810
+#define AM335X_CONF_GPMC_AD5 0x814
+#define AM335X_CONF_GPMC_AD6 0x818
+#define AM335X_CONF_GPMC_AD7 0x81C
+#define AM335X_CONF_GPMC_AD8 0x820
+#define AM335X_CONF_GPMC_AD9 0x824
+#define AM335X_CONF_GPMC_AD10 0x828
+#define AM335X_CONF_GPMC_AD11 0x82C
+#define AM335X_CONF_GPMC_AD12 0x830
+#define AM335X_CONF_GPMC_AD13 0x834
+#define AM335X_CONF_GPMC_AD14 0x838
+#define AM335X_CONF_GPMC_AD15 0x83C
+#define AM335X_CONF_GPMC_A0 0x840
+#define AM335X_CONF_GPMC_A1 0x844
+#define AM335X_CONF_GPMC_A2 0x848
+#define AM335X_CONF_GPMC_A3 0x84C
+#define AM335X_CONF_GPMC_A4 0x850
+#define AM335X_CONF_GPMC_A5 0x854
+#define AM335X_CONF_GPMC_A6 0x858
+#define AM335X_CONF_GPMC_A7 0x85C
+#define AM335X_CONF_GPMC_A8 0x860
+#define AM335X_CONF_GPMC_A9 0x864
+#define AM335X_CONF_GPMC_A10 0x868
+#define AM335X_CONF_GPMC_A11 0x86C
+#define AM335X_CONF_GPMC_WAIT0 0x870
+#define AM335X_CONF_GPMC_WPN 0x874
+#define AM335X_CONF_GPMC_BEN1 0x878
+#define AM335X_CONF_GPMC_CSN0 0x87C
+#define AM335X_CONF_GPMC_CSN1 0x880
+#define AM335X_CONF_GPMC_CSN2 0x884
+#define AM335X_CONF_GPMC_CSN3 0x888
+#define AM335X_CONF_GPMC_CLK 0x88C
+#define AM335X_CONF_GPMC_ADVN_ALE 0x890
+#define AM335X_CONF_GPMC_OEN_REN 0x894
+#define AM335X_CONF_GPMC_WEN 0x898
+#define AM335X_CONF_GPMC_BEN0_CLE 0x89C
+#define AM335X_CONF_LCD_DATA0 0x8A0
+#define AM335X_CONF_LCD_DATA1 0x8A4
+#define AM335X_CONF_LCD_DATA2 0x8A8
+#define AM335X_CONF_LCD_DATA3 0x8AC
+#define AM335X_CONF_LCD_DATA4 0x8B0
+#define AM335X_CONF_LCD_DATA5 0x8B4
+#define AM335X_CONF_LCD_DATA6 0x8B8
+#define AM335X_CONF_LCD_DATA7 0x8BC
+#define AM335X_CONF_LCD_DATA8 0x8C0
+#define AM335X_CONF_LCD_DATA9 0x8C4
+#define AM335X_CONF_LCD_DATA10 0x8C8
+#define AM335X_CONF_LCD_DATA11 0x8CC
+#define AM335X_CONF_LCD_DATA12 0x8D0
+#define AM335X_CONF_LCD_DATA13 0x8D4
+#define AM335X_CONF_LCD_DATA14 0x8D8
+#define AM335X_CONF_LCD_DATA15 0x8DC
+#define AM335X_CONF_LCD_VSYNC 0x8E0
+#define AM335X_CONF_LCD_HSYNC 0x8E4
+#define AM335X_CONF_LCD_PCLK 0x8E8
+#define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC
+#define AM335X_CONF_MMC0_DAT3 0x8F0
+#define AM335X_CONF_MMC0_DAT2 0x8F4
+#define AM335X_CONF_MMC0_DAT1 0x8F8
+#define AM335X_CONF_MMC0_DAT0 0x8FC
+#define AM335X_CONF_MMC0_CLK 0x900
+#define AM335X_CONF_MMC0_CMD 0x904
+#define AM335X_CONF_MII1_COL 0x908
+#define AM335X_CONF_MII1_CRS 0x90C
+#define AM335X_CONF_MII1_RX_ER 0x910
+#define AM335X_CONF_MII1_TX_EN 0x914
+#define AM335X_CONF_MII1_RX_DV 0x918
+#define AM335X_CONF_MII1_TXD3 0x91C
+#define AM335X_CONF_MII1_TXD2 0x920
+#define AM335X_CONF_MII1_TXD1 0x924
+#define AM335X_CONF_MII1_TXD0 0x928
+#define AM335X_CONF_MII1_TX_CLK 0x92C
+#define AM335X_CONF_MII1_RX_CLK 0x930
+#define AM335X_CONF_MII1_RXD3 0x934
+#define AM335X_CONF_MII1_RXD2 0x938
+#define AM335X_CONF_MII1_RXD1 0x93C
+#define AM335X_CONF_MII1_RXD0 0x940
+#define AM335X_CONF_RMII1_REF_CLK 0x944
+#define AM335X_CONF_MDIO 0x948
+#define AM335X_CONF_MDC 0x94C
+#define AM335X_CONF_SPI0_SCLK 0x950
+#define AM335X_CONF_SPI0_D0 0x954
+#define AM335X_CONF_SPI0_D1 0x958
+#define AM335X_CONF_SPI0_CS0 0x95C
+#define AM335X_CONF_SPI0_CS1 0x960
+#define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964
+#define AM335X_CONF_UART0_CTSN 0x968
+#define AM335X_CONF_UART0_RTSN 0x96C
+#define AM335X_CONF_UART0_RXD 0x970
+#define AM335X_CONF_UART0_TXD 0x974
+#define AM335X_CONF_UART1_CTSN 0x978
+#define AM335X_CONF_UART1_RTSN 0x97C
+#define AM335X_CONF_UART1_RXD 0x980
+#define AM335X_CONF_UART1_TXD 0x984
+#define AM335X_CONF_I2C0_SDA 0x988
+#define AM335X_CONF_I2C0_SCL 0x98C
+#define AM335X_CONF_MCASP0_ACLKX 0x990
+#define AM335X_CONF_MCASP0_FSX 0x994
+#define AM335X_CONF_MCASP0_AXR0 0x998
+#define AM335X_CONF_MCASP0_AHCLKR 0x99C
+#define AM335X_CONF_MCASP0_ACLKR 0x9A0
+#define AM335X_CONF_MCASP0_FSR 0x9A4
+#define AM335X_CONF_MCASP0_AXR1 0x9A8
+#define AM335X_CONF_MCASP0_AHCLKX 0x9AC
+#define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0
+#define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4
+#define AM335X_CONF_WARMRSTN 0x9B8
+#define AM335X_CONF_NNMI 0x9C0
+#define AM335X_CONF_TMS 0x9D0
+#define AM335X_CONF_TDI 0x9D4
+#define AM335X_CONF_TDO 0x9D8
+#define AM335X_CONF_TCK 0x9DC
+#define AM335X_CONF_TRSTN 0x9E0
+#define AM335X_CONF_EMU0 0x9E4
+#define AM335X_CONF_EMU1 0x9E8
+#define AM335X_CONF_RTC_PWRONRSTN 0x9F8
+#define AM335X_CONF_PMIC_POWER_EN 0x9FC
+#define AM335X_CONF_EXT_WAKEUP 0xA00
+#define AM335X_CONF_RTC_KALDO_ENN 0xA04
+#define AM335X_CONF_USB0_DRVVBUS 0xA1C
+#define AM335X_CONF_USB1_DRVVBUS 0xA34
