Changeset 14eefeab in rtems


Ignore:
Timestamp:
Jun 2, 2009, 9:13:44 PM (10 years ago)
Author:
Eric Norum <WENorum@…>
Branches:
4.10, 4.11, master
Children:
e7bde492
Parents:
222f8684
Message:

As per Freescale chip errata, disable buffered writes.

Location:
c/src/lib/libbsp/m68k/uC5282
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/uC5282/ChangeLog

    r222f8684 r14eefeab  
     12009-06-02  Eric Norum <norume@aps.anl.gov>
     2
     3    * startup/bspstart.c: Turn off buffered writes.
     4
    152009-04-28      Chris Johns <chrisj@rtems.org>
    26
  • c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c

    r222f8684 r14eefeab  
    6060 * corruption problem.
    6161 * DATECODES AFFECTED: All
     62 *
     63 *
     64 * Buffered writes must be disabled as described in "MCF5282 Chip Errata",
     65 * MCF5282DE, Rev. 6, 5/2009:
     66 *   SECF124: Buffered Write May Be Executed Twice
     67 *   Errata type: Silicon
     68 *   Affected component: Cache
     69 *   Description: If buffered writes are enabled using the CACR or ACR
     70 *                registers, the imprecise write transaction generated
     71 *                by a buffered write may be executed twice.
     72 *   Workaround: Do not enable buffered writes in the CACR or ACR registers:
     73 *               CACR[8] = DBWE (default buffered write enable) must be 0
     74 *               ACRn[5] = BUFW (buffered write enable) must be 0
     75 *   Fix plan: Currently, there are no plans to fix this.
    6276 */
    6377#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
     
    7084 *   Split instruction/data or instruction-only
    7185 *   Allow CPUSHL to invalidate a cache line
    72  *   Enable buffered writes
     86 *   Disable buffered writes
    7387 *   No burst transfers on non-cacheable accesses
    7488 *   Default cache mode is *disabled* (cache only ACRx areas)
     
    7892                             MCF5XXX_CACR_DISD |
    7993#endif
    80                              MCF5XXX_CACR_DBWE |
    8194                             MCF5XXX_CACR_DCM;
    8295uint32_t mcf5282_acr0_mode = 0;
     
    244257                      MCF5XXX_ACR_AM((uint32_t)RamSize-1)   |
    245258                      MCF5XXX_ACR_EN                         |
    246                       MCF5XXX_ACR_BWE                        |
    247259                      MCF5XXX_ACR_SM_IGNORE;
    248260  m68k_set_acr0(mcf5282_acr0_mode);
Note: See TracChangeset for help on using the changeset viewer.