Changeset 14ee5a1e in rtems


Ignore:
Timestamp:
Feb 11, 2012, 8:10:12 PM (8 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
e1ebfebf
Parents:
1f8771d2
git-author:
Sebastian Huber <sebastian.huber@…> (02/11/12 20:10:12)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/11/12 20:11:30)
Message:

Support for NXP LPC1700 family

Location:
c/src/lib/libbsp/arm/lpc24xx
Files:
6 added
16 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc24xx/Makefile.am

    r1f8771d2 r14ee5a1e  
    6767project_lib_DATA += startup/linkcmds
    6868EXTRA_DIST =
     69EXTRA_DIST += startup/linkcmds.lpc17xx_ea_ram
     70EXTRA_DIST += startup/linkcmds.lpc17xx_ea_rom_int
    6971EXTRA_DIST += startup/linkcmds.lpc2362
    7072EXTRA_DIST += startup/linkcmds.lpc23xx_tli800
     
    152154libbsp_a_SOURCES += startup/start-config-emc-dynamic.c
    153155libbsp_a_SOURCES += startup/start-config-emc-static.c
     156libbsp_a_SOURCES += startup/start-config-mpu.c
    154157libbsp_a_SOURCES += startup/start-config-pinsel.c
    155158
  • c/src/lib/libbsp/arm/lpc24xx/include/bsp.h

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    4141
    4242#define LPC24XX_EMCCLK (LPC24XX_CCLK / LPC24XX_EMCCLKDIV)
     43
     44#define LPC24XX_MPU_REGION_COUNT 8
    4345
    4446#ifndef ASM
  • c/src/lib/libbsp/arm/lpc24xx/include/io.h

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2009-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    7373  LPC24XX_MODULE_LCD,
    7474  LPC24XX_MODULE_MCI,
     75  #ifdef ARM_MULTILIB_ARCH_V7M
     76    LPC24XX_MODULE_MCPWM,
     77  #endif
    7578  LPC24XX_MODULE_PCB,
    7679  LPC24XX_MODULE_PWM_0,
    7780  LPC24XX_MODULE_PWM_1,
     81  #ifdef ARM_MULTILIB_ARCH_V7M
     82    LPC24XX_MODULE_QEI,
     83  #endif
    7884  LPC24XX_MODULE_RTC,
    7985  #ifdef ARM_MULTILIB_ARCH_V4
     
    8288  LPC24XX_MODULE_SSP_0,
    8389  LPC24XX_MODULE_SSP_1,
     90  #ifdef ARM_MULTILIB_ARCH_V7M
     91    LPC24XX_MODULE_SSP_2,
     92  #endif
    8493  LPC24XX_MODULE_SYSCON,
    8594  LPC24XX_MODULE_TIMER_0,
     
    91100  LPC24XX_MODULE_UART_2,
    92101  LPC24XX_MODULE_UART_3,
     102  #ifdef ARM_MULTILIB_ARCH_V7M
     103    LPC24XX_MODULE_UART_4,
     104  #endif
    93105  #ifdef ARM_MULTILIB_ARCH_V4
    94106    LPC24XX_MODULE_WDT,
     
    116128  LPC24XX_GPIO_RESISTOR_PULL_DOWN = 0x2U,
    117129  LPC24XX_GPIO_INPUT = 0x0U,
     130  #ifdef ARM_MULTILIB_ARCH_V7M
     131    LPC17XX_GPIO_REPEATER = 0x3U,
     132    LPC17XX_GPIO_HYSTERESIS = IOCON_HYS,
     133    LPC17XX_GPIO_INPUT_INVERT = IOCON_INV,
     134    LPC17XX_GPIO_FAST_MODE = IOCON_SLEW,
     135    LPC17XX_GPIO_OPEN_DRAIN = IOCON_OD,
     136    LPC17XX_GPIO_INPUT_FILTER = IOCON_FILTER,
     137  #endif
    118138  LPC24XX_GPIO_OUTPUT = 0x8000U
    119139} lpc24xx_gpio_settings;
     
    227247  #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \
    228248    { { p, i, f0, 0, 0 } }, { { p, j, f0, 0, 1 } }
     249#else
     250  #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f1, 0, 0 } }
     251  #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f1, t, 0 } }
     252  #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \
     253    { { p, i, f1, 0, 0 } }, { { p, j, f1, 0, 1 } }
    229254#endif
    230255
     
    797822/** @} */
    798823
     824#ifdef ARM_MULTILIB_ARCH_V4
     825
     826/**
     827 * @name SPI Pins
     828 *
     829 * @{
     830 */
     831
     832#define LPC24XX_PIN_SPI_SCK \
     833  LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_11)
     834#define LPC24XX_PIN_SPI_SSEL \
     835  LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_11)
     836#define LPC24XX_PIN_SPI_MISO \
     837  LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_11)
     838#define LPC24XX_PIN_SPI_MOSI \
     839  LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_11)
     840
     841/** @} */
     842
     843#endif /* ARM_MULTILIB_ARCH_V4 */
     844
    799845/**
    800846 * @name SSP 0 Pins
     
    869915/** @} */
    870916
     917#ifdef ARM_MULTILIB_ARCH_V7M
     918
     919/**
     920 * @name SSP 2 Pins
     921 *
     922 * @{
     923 */
     924
     925#define LPC24XX_PIN_SSP_2_SCK_P1_0 \
     926  LPC24XX_PIN(1, 0, LPC24XX_PIN_FUNCTION_00, 4)
     927
     928#define LPC24XX_PIN_SSP_2_SSEL_P1_8 \
     929  LPC24XX_PIN(1, 8, LPC24XX_PIN_FUNCTION_00, 4)
     930
     931#define LPC24XX_PIN_SSP_2_MISO_P1_4 \
     932  LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_00, 4)
     933
     934#define LPC24XX_PIN_SSP_2_MOSI_P1_1 \
     935  LPC24XX_PIN(1, 1, LPC24XX_PIN_FUNCTION_00, 4)
     936
     937/** @} */
     938
     939#endif /* ARM_MULTILIB_ARCH_V7M */
     940
    871941/**
    872942 * @name UART 0 Pins
     
    9461016#define LPC24XX_PIN_UART_3_RXD_P4_29 \
    9471017  LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_11, 2)
     1018
     1019/** @} */
     1020
     1021#ifdef ARM_MULTILIB_ARCH_V7M
     1022
     1023/**
     1024 * @name UART 4 Pins
     1025 *
     1026 * @{
     1027 */
     1028
     1029#define LPC24XX_PIN_UART_4_TXD_P0_22 \
     1030  LPC24XX_PIN(0, 22, LPC24XX_PIN_FUNCTION_00, 3)
     1031#define LPC24XX_PIN_UART_4_TXD_P1_29 \
     1032  LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_00, 5)
     1033#define LPC24XX_PIN_UART_4_TXD_P5_4 \
     1034  LPC24XX_PIN(5, 4, LPC24XX_PIN_FUNCTION_00, 4)
     1035
     1036#define LPC24XX_PIN_UART_4_RXD_P2_9 \
     1037  LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_00, 3)
     1038#define LPC24XX_PIN_UART_4_RXD_P5_3 \
     1039  LPC24XX_PIN(5, 3, LPC24XX_PIN_FUNCTION_00, 4)
     1040
     1041#define LPC24XX_PIN_UART_4_OE_P0_21 \
     1042  LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_00, 3)
     1043
     1044#define LPC24XX_PIN_UART_4_SCLK_P0_21 \
     1045  LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_00, 5)
     1046
     1047#endif /* ARM_MULTILIB_ARCH_V7M */
    9481048
    9491049/** @} */
  • c/src/lib/libbsp/arm/lpc24xx/include/irq.h

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    7373
    7474  #define BSP_INTERRUPT_VECTOR_MAX 31
     75#else
     76  #define LPC24XX_IRQ_WDT 0
     77  #define LPC24XX_IRQ_TIMER_0 1
     78  #define LPC24XX_IRQ_TIMER_1 2
     79  #define LPC24XX_IRQ_TIMER_2 3
     80  #define LPC24XX_IRQ_TIMER_3 4
     81  #define LPC24XX_IRQ_UART_0 5
     82  #define LPC24XX_IRQ_UART_1 6
     83  #define LPC24XX_IRQ_UART_2 7
     84  #define LPC24XX_IRQ_UART_3 8
     85  #define LPC24XX_IRQ_PWM_1 9
     86  #define LPC24XX_IRQ_I2C_0 10
     87  #define LPC24XX_IRQ_I2C_1 11
     88  #define LPC24XX_IRQ_I2C_2 12
     89  #define LPC24XX_IRQ_SPI_SSP_0 14
     90  #define LPC24XX_IRQ_SSP_1 15
     91  #define LPC24XX_IRQ_PLL 16
     92  #define LPC24XX_IRQ_RTC 17
     93  #define LPC24XX_IRQ_EINT_0 18
     94  #define LPC24XX_IRQ_EINT_1 19
     95  #define LPC24XX_IRQ_EINT_2 20
     96  #define LPC24XX_IRQ_EINT_3 21
     97  #define LPC24XX_IRQ_ADC_0 22
     98  #define LPC24XX_IRQ_BOD 23
     99  #define LPC24XX_IRQ_USB 24
     100  #define LPC24XX_IRQ_CAN 25
     101  #define LPC24XX_IRQ_DMA 26
     102  #define LPC24XX_IRQ_I2S 27
     103  #define LPC24XX_IRQ_ETHERNET 28
     104  #define LPC24XX_IRQ_SD_MMC 29
     105  #define LPC24XX_IRQ_MCPWM 30
     106  #define LPC24XX_IRQ_QEI 31
     107  #define LPC24XX_IRQ_PLL_ALT 32
     108  #define LPC24XX_IRQ_USB_ACTIVITY 33
     109  #define LPC24XX_IRQ_CAN_ACTIVITY 34
     110  #define LPC24XX_IRQ_UART_4 35
     111  #define LPC24XX_IRQ_SSP_2 36
     112  #define LPC24XX_IRQ_LCD 37
     113  #define LPC24XX_IRQ_GPIO 38
     114  #define LPC24XX_IRQ_PWM 39
     115  #define LPC24XX_IRQ_EEPROM 40
     116
     117  #define BSP_INTERRUPT_VECTOR_MAX 40
    75118#endif
    76119
     
    78121#ifdef ARM_MULTILIB_ARCH_V4
    79122  #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15
     123#else
     124  #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 31
    80125#endif
    81126#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1)
  • c/src/lib/libbsp/arm/lpc24xx/include/lcd.h

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2010-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    5353    LCD_MODE_TFT_24_BIT,
    5454    LCD_MODE_DISABLED
     55  #else
     56    LCD_MODE_STN_4_BIT = 0x4,
     57    LCD_MODE_STN_8_BIT = 0x6,
     58    LCD_MODE_STN_DUAL_PANEL_4_BIT = 0x84,
     59    LCD_MODE_STN_DUAL_PANEL_8_BIT = 0x86,
     60    LCD_MODE_TFT_12_BIT_4_4_4 = 0x2e,
     61    LCD_MODE_TFT_16_BIT_5_6_5 = 0x2c,
     62    LCD_MODE_TFT_16_BIT_1_5_5_5 = 0x28,
     63    LCD_MODE_TFT_24_BIT = 0x2a,
     64    LCD_MODE_DISABLED = 0xff
    5565  #endif
    5666} lpc24xx_lcd_mode;
  • c/src/lib/libbsp/arm/lpc24xx/include/start-config.h

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    2525#ifndef LIBBSP_ARM_LPC24XX_START_CONFIG_H
    2626#define LIBBSP_ARM_LPC24XX_START_CONFIG_H
     27
     28#include <rtems/score/armv7m.h>
    2729
    2830#include <bsp.h>
     
    9193  lpc24xx_start_config_emc_static_chip_count;
    9294
     95extern BSP_START_DATA_SECTION const ARMV7M_MPU_Region
     96  lpc24xx_start_config_mpu_regions [LPC24XX_MPU_REGION_COUNT];
     97
    9398#ifdef __cplusplus
    9499}
  • c/src/lib/libbsp/arm/lpc24xx/irq/irq-dispatch.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    4545    /* Acknowledge interrupt */
    4646    VICVectAddr = 0;
     47  #else
     48    rtems_vector_number vector =
     49      ARMV7M_SCB_ICSR_VECTACTIVE_GET(_ARMV7M_SCB->icsr);
     50
     51    _ARMV7M_Interrupt_service_enter();
     52    bsp_interrupt_handler_dispatch(ARMV7M_IRQ_OF_VECTOR(vector));
     53    _ARMV7M_Interrupt_service_leave();
    4754  #endif
    4855}
  • c/src/lib/libbsp/arm/lpc24xx/irq/irq.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    4343    #ifdef ARM_MULTILIB_ARCH_V4
    4444      VICVectPriorityBase [vector] = priority;
     45    #else
     46      _ARMV7M_NVIC_Set_priority((int) vector, (int) (priority << 3));
    4547    #endif
    4648  }
     
    5254    #ifdef ARM_MULTILIB_ARCH_V4
    5355      return VICVectPriorityBase [vector];
     56    #else
     57      return (unsigned) (_ARMV7M_NVIC_Get_priority((int) vector) >> 3);
    5458    #endif
    5559  } else {
     
    6266  #ifdef ARM_MULTILIB_ARCH_V4
    6367    VICIntEnable = 1U << vector;
     68  #else
     69    _ARMV7M_NVIC_Set_enable((int) vector);
    6470  #endif
    6571
     
    7177  #ifdef ARM_MULTILIB_ARCH_V4
    7278    VICIntEnClear = 1U << vector;
     79  #else
     80    _ARMV7M_NVIC_Clear_enable((int) vector);
    7381  #endif
    7482
     
    114122    /* Install the IRQ exception handler */
    115123    _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
     124  #else
     125    rtems_vector_number i = 0;
     126    ARMV7M_Exception_handler *vector_table =
     127      (ARMV7M_Exception_handler *) bsp_vector_table_begin;
     128
     129    memcpy(
     130      vector_table,
     131      bsp_start_vector_table_begin,
     132      (size_t) bsp_vector_table_size
     133    );
     134
     135    for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
     136      vector_table [ARMV7M_VECTOR_IRQ(i)] = bsp_interrupt_dispatch;
     137      _ARMV7M_NVIC_Clear_enable(i);
     138      _ARMV7M_NVIC_Clear_pending(i);
     139      lpc24xx_irq_set_priority(i, LPC24XX_IRQ_PRIORITY_VALUE_MAX - 1);
     140    }
     141
     142    _ARMV7M_SCB->vtor = vector_table;
    116143  #endif
    117144
  • c/src/lib/libbsp/arm/lpc24xx/misc/io.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2009-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    6161          return RTEMS_INVALID_NUMBER;
    6262      }
     63    #else
     64      uint32_t iocon_mask = IOCON_HYS | IOCON_INV
     65        | IOCON_SLEW | IOCON_OD | IOCON_FILTER;
     66      uint32_t iocon = (settings & iocon_mask) | IOCON_ADMODE;
     67      uint32_t iocon_invalid = settings & ~(iocon_mask | LPC24XX_GPIO_OUTPUT);
     68
     69      /* Get resistor flags */
     70      switch (resistor) {
     71        case LPC24XX_GPIO_RESISTOR_NONE:
     72          resistor = IOCON_MODE(0);
     73          break;
     74        case LPC24XX_GPIO_RESISTOR_PULL_DOWN:
     75          resistor = IOCON_MODE(1);
     76          break;
     77        case LPC24XX_GPIO_RESISTOR_PULL_UP:
     78          resistor = IOCON_MODE(2);
     79          break;
     80        case LPC17XX_GPIO_HYSTERESIS:
     81          resistor = IOCON_MODE(3);
     82          break;
     83      }
     84      iocon |= resistor;
     85
     86      if (iocon_invalid != 0) {
     87        return RTEMS_INVALID_NUMBER;
     88      }
     89
     90      if (output && (settings & LPC17XX_GPIO_INPUT_INVERT) != 0) {
     91        return RTEMS_INVALID_NUMBER;
     92      }
     93
     94      if ((settings & LPC17XX_GPIO_INPUT_FILTER) == 0) {
     95        iocon |= IOCON_FILTER;
     96      } else {
     97        iocon &= ~IOCON_FILTER;
     98      }
    6399    #endif
    64100
     
    70106        (LPC24XX_PINMODE [select] & ~(LPC24XX_PIN_SELECT_MASK << shift))
    71107          | ((resistor & LPC24XX_PIN_SELECT_MASK) << shift);
     108    #else
     109      LPC17XX_IOCON [index] = iocon;
    72110    #endif
    73111
     
    128166  #endif
    129167  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_MCI, 1, 1, 28),
     168  #ifdef ARM_MULTILIB_ARCH_V7M
     169    LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_MCPWM, 1, 1, 17),
     170  #endif
    130171  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PCB, 0, 1, 18),
    131172  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PWM_0, 1, 1, 5),
    132173  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_PWM_1, 1, 1, 6),
     174  #ifdef ARM_MULTILIB_ARCH_V7M
     175    LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_QEI, 1, 1, 18),
     176  #endif
    133177  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_RTC, 1, 1, 9),
    134178  #ifdef ARM_MULTILIB_ARCH_V4
     
    137181  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_0, 1, 1, 21),
    138182  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_1, 1, 1, 10),
     183  #ifdef ARM_MULTILIB_ARCH_V7M
     184    LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SSP_2, 1, 1, 20),
     185  #endif
    139186  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_SYSCON, 0, 1, 30),
    140187  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_TIMER_0, 1, 1, 1),
     
    146193  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_2, 1, 1, 24),
    147194  LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_3, 1, 1, 25),
     195  #ifdef ARM_MULTILIB_ARCH_V7M
     196    LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_UART_4, 1, 1, 8),
     197  #endif
    148198  #ifdef ARM_MULTILIB_ARCH_V4
    149199    LPC24XX_MODULE_ENTRY(LPC24XX_MODULE_WDT, 0, 1, 0),
     
    162212  bool has_clock = false;
    163213  unsigned index = 0;
     214  #ifdef ARM_MULTILIB_ARCH_V7M
     215    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     216  #endif
    164217
    165218  if ((unsigned) module >= LPC24XX_MODULE_COUNT) {
     
    183236      return RTEMS_INVALID_CLOCK;
    184237    }
     238  #else
     239    if (clock != LPC24XX_MODULE_PCLK_DEFAULT) {
     240      return RTEMS_INVALID_CLOCK;
     241    }
    185242  #endif
    186243
     
    195252      #ifdef ARM_MULTILIB_ARCH_V4
    196253        PCONP |= 1U << index;
     254      #else
     255        scb->pconp |= 1U << index;
    197256      #endif
    198257      rtems_interrupt_enable(level);
     
    230289
    231290        USBCLKCFG = usbsel;
     291      #else
     292        /* FIXME */
     293        scb->usbclksel = 0;
    232294      #endif
    233295    }
     
    237299      #ifdef ARM_MULTILIB_ARCH_V4
    238300        PCONP &= ~(1U << index);
     301      #else
     302        scb->pconp &= ~(1U << index);
    239303      #endif
    240304      rtems_interrupt_enable(level);
     
    265329    uint32_t pinsel_mask,
    266330    uint32_t pinsel_value,
     331  #else
     332    volatile uint32_t *iocon,
     333    lpc24xx_pin_range pin_range,
    267334  #endif
    268335  volatile uint32_t *fio_dir,
     
    276343    uint32_t pinsel_mask,
    277344    uint32_t pinsel_value,
     345  #else
     346    volatile uint32_t *iocon,
     347    lpc24xx_pin_range pin_range,
    278348  #endif
    279349  volatile uint32_t *fio_dir,
     
    287357    *pinsel = (*pinsel & ~pinsel_mask) | pinsel_value;
    288358    rtems_interrupt_enable(level);
     359  #else
     360    /* TODO */
     361    *iocon = IOCON_FUNC(pin_range.fields.function);
    289362  #endif
    290363
     
    297370    uint32_t pinsel_mask,
    298371    uint32_t pinsel_value,
     372  #else
     373    volatile uint32_t *iocon,
     374    lpc24xx_pin_range pin_range,
    299375  #endif
    300376  volatile uint32_t *fio_dir,
     
    308384      return RTEMS_IO_ERROR;
    309385    }
     386  #else
     387    /* TODO */
     388    return RTEMS_IO_ERROR;
    310389  #endif
    311390}
     
    317396    uint32_t pinsel_mask,
    318397    uint32_t pinsel_value,
     398  #else
     399    volatile uint32_t *iocon,
     400    lpc24xx_pin_range pin_range,
    319401  #endif
    320402  volatile uint32_t *fio_dir,
     
    328410  #ifdef ARM_MULTILIB_ARCH_V4
    329411    *pinsel &= ~pinsel_mask;
     412  #else
     413    *iocon = IOCON_MODE(2) | IOCON_ADMODE | IOCON_FILTER;
    330414  #endif
    331415  rtems_interrupt_enable(level);
     
    339423    uint32_t pinsel_mask,
    340424    uint32_t pinsel_value,
     425  #else
     426    volatile uint32_t *iocon,
     427    lpc24xx_pin_range pin_range,
    341428  #endif
    342429  volatile uint32_t *fio_dir,
     
    350437    #ifdef ARM_MULTILIB_ARCH_V4
    351438      bool is_gpio = (*pinsel & pinsel_mask) == 0;
     439    #else
     440      bool is_gpio = IOCON_FUNC_GET(*iocon) == 0;
    352441    #endif
    353442
     
    406495
    407496          sc = (*visitor)(pinsel, pinsel_mask, pinsel_value, fio_dir, fio_bit);
     497        #else
     498          volatile uint32_t *iocon = &LPC17XX_IOCON [index];
     499
     500          sc = (*visitor)(iocon, pin_range, fio_dir, fio_bit);
    408501        #endif
    409502
  • c/src/lib/libbsp/arm/lpc24xx/misc/lcd.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    111111      return LCD_MODE_DISABLED;
    112112    }
     113  #else
     114    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     115
     116    if ((scb->pconp & LPC17XX_SCB_PCONP_LCD) != 0) {
     117      return LCD_CTRL & 0xae;
     118    } else {
     119      return LCD_MODE_DISABLED;
     120    }
    113121  #endif
    114122}
  • c/src/lib/libbsp/arm/lpc24xx/misc/restart.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    4242      : [addr] "r" (addr)
    4343    );
     44  #else
     45    rtems_interrupt_level level;
     46    void (*start)(void) = addr;
     47
     48    rtems_interrupt_disable(level);
     49    (*start)();
    4450  #endif
    4551}
  • c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    7575}
    7676
     77#ifdef ARM_MULTILIB_ARCH_V7M
     78  unsigned lpc17xx_sysclk(unsigned clksrcsel)
     79  {
     80    return (clksrcsel & LPC17XX_SCB_CLKSRCSEL_CLKSRC) != 0 ?
     81      LPC24XX_OSCILLATOR_MAIN
     82        : LPC24XX_OSCILLATOR_INTERNAL;
     83  }
     84#endif
     85
    7786unsigned lpc24xx_pllclk(void)
    7887{
     
    107116      pllclk = pllinclk;
    108117    }
     118  #else
     119    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     120    unsigned sysclk = lpc17xx_sysclk(scb->clksrcsel);
     121    unsigned pllstat = scb->pll_0.stat;
     122    unsigned pllclk = 0;
     123    unsigned enabled_and_locked = LPC17XX_PLL_STAT_PLLE
     124      | LPC17XX_PLL_STAT_PLOCK;
     125
     126    if ((pllstat & enabled_and_locked) == enabled_and_locked) {
     127      unsigned m = LPC17XX_PLL_SEL_MSEL_GET(pllstat) + 1;
     128
     129      pllclk = sysclk * m;
     130    }
    109131  #endif
    110132
     
    120142    /* Get CPU frequency */
    121143    unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL(CCLKCFG) + 1);
     144  #else
     145    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     146    unsigned cclksel = scb->cclksel;
     147    unsigned cclk_in = 0;
     148    unsigned cclk = 0;
     149
     150    if ((cclksel & LPC17XX_SCB_CCLKSEL_CCLKSEL) != 0) {
     151      cclk_in = lpc24xx_pllclk();
     152    } else {
     153      cclk_in = lpc17xx_sysclk(scb->clksrcsel);
     154    }
     155
     156    cclk = cclk_in / LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(cclksel);
    122157  #endif
    123158
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * rtems@embedded-brains.de
     10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
    1611 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
     17 *
     18 * The license and distribution terms for this file may be
     19 * found in the file LICENSE in this distribution or at
     20 * http://www.rtems.com/license/LICENSE.
    1921 */
    2022
     
    3840    WDFEED = 0xaa;
    3941    WDFEED = 0x55;
     42  #else
     43    printk("reset\n");
    4044  #endif
    4145
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    7474    lpc24xx_module_enable(LPC24XX_MODULE_UART_0, LPC24XX_MODULE_PCLK_DEFAULT);
    7575    lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION);
    76     BSP_CONSOLE_UART_INIT(lpc24xx_cclk() / 16 / LPC24XX_UART_BAUD);
     76    BSP_CONSOLE_UART_INIT(LPC24XX_PCLK / 16 / LPC24XX_UART_BAUD);
    7777  #endif
    7878}
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    2121 */
    2222
    23 #include <stdbool.h>
    24 
    25 #include <rtems/score/armv7m.h>
    26 
    27 #include <bspopts.h>
     23#include <bsp.h>
    2824#include <bsp/io.h>
    2925#include <bsp/start.h>
     
    10298        &lpc24xx_start_config_emc_dynamic [0];
    10399      uint32_t dynamiccontrol = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS;
     100
     101      #ifdef ARM_MULTILIB_ARCH_V7M
     102        volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     103
     104        /* Delay control */
     105        scb->emcdlyctl = cfg->emcdlyctl;
     106      #endif
    104107
    105108      emc->dynamicreadconfig = cfg->readconfig;
     
    169172      }
    170173    }
     174  #else
     175    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     176
     177    if ((scb->scs & LPC17XX_SCB_SCS_OSC_STATUS) == 0) {
     178      scb->scs |= LPC17XX_SCB_SCS_OSC_ENABLE;
     179      while ((scb->scs & LPC17XX_SCB_SCS_OSC_STATUS) == 0) {
     180        /* Wait */
     181      }
     182    }
    171183  #endif
    172184}
     
    253265}
    254266
     267#else /* ARM_MULTILIB_ARCH_V4 */
     268
     269static BSP_START_TEXT_SECTION void lpc17xx_pll_config(
     270  volatile lpc17xx_pll *pll,
     271  uint32_t val
     272)
     273{
     274  pll->con = val;
     275  pll->feed = 0xaa;
     276  pll->feed = 0x55;
     277}
     278
     279static BSP_START_TEXT_SECTION void lpc17xx_set_pll(
     280  unsigned msel,
     281  unsigned psel,
     282  unsigned cclkdiv
     283)
     284{
     285  volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     286  volatile lpc17xx_pll *pll = &scb->pll_0;
     287  uint32_t pllcfg = LPC17XX_PLL_SEL_MSEL(msel)
     288    | LPC17XX_PLL_SEL_PSEL(psel);
     289  uint32_t pllstat = LPC17XX_PLL_STAT_PLLE
     290    | LPC17XX_PLL_STAT_PLOCK | pllcfg;
     291  uint32_t cclksel_cclkdiv = LPC17XX_SCB_CCLKSEL_CCLKDIV(cclkdiv);
     292  uint32_t cclksel = LPC17XX_SCB_CCLKSEL_CCLKSEL | cclksel_cclkdiv;
     293
     294  if (
     295    pll->stat != pllstat
     296      || scb->cclksel != cclksel
     297      || scb->clksrcsel != LPC17XX_SCB_CLKSRCSEL_CLKSRC
     298  ) {
     299    /* Use SYSCLK for CCLK */
     300    scb->cclksel = LPC17XX_SCB_CCLKSEL_CCLKDIV(1);
     301
     302    /* Turn off USB */
     303    scb->usbclksel = 0;
     304
     305    /* Disable PLL */
     306    lpc17xx_pll_config(pll, 0);
     307
     308    /* Select main oscillator as clock source */
     309    scb->clksrcsel = LPC17XX_SCB_CLKSRCSEL_CLKSRC;
     310
     311    /* Set PLL configuration */
     312    pll->cfg = pllcfg;
     313
     314    /* Set the CCLK, PCLK and EMCCLK divider */
     315    scb->cclksel = cclksel_cclkdiv;
     316    scb->pclksel = LPC17XX_SCB_PCLKSEL_PCLKDIV(LPC24XX_PCLKDIV);
     317    scb->emcclksel = LPC24XX_EMCCLKDIV == 1 ? 0 : LPC17XX_SCB_EMCCLKSEL_EMCDIV;
     318
     319    /* Enable PLL */
     320    lpc17xx_pll_config(pll, LPC17XX_PLL_CON_PLLE);
     321
     322    /* Wait for lock */
     323    while ((pll->stat & LPC17XX_PLL_STAT_PLOCK) == 0) {
     324      /* Wait */
     325    }
     326
     327    /* Use the PLL clock */
     328    scb->cclksel = cclksel;
     329  }
     330}
     331
    255332#endif /* ARM_MULTILIB_ARCH_V4 */
    256333
     
    275352      #error "unexpected main oscillator frequency"
    276353    #endif
     354  #else
     355    #if LPC24XX_OSCILLATOR_MAIN == 12000000U
     356      #if LPC24XX_CCLK == 120000000U
     357        lpc17xx_set_pll(9, 0, 1);
     358      #elif LPC24XX_CCLK == 96000000U
     359        lpc17xx_set_pll(7, 0, 1);
     360      #elif LPC24XX_CCLK == 72000000U
     361        lpc17xx_set_pll(5, 1, 1);
     362      #elif LPC24XX_CCLK == 48000000U
     363        lpc17xx_set_pll(3, 1, 1);
     364      #else
     365        #error "unexpected CCLK"
     366      #endif
     367    #else
     368      #error "unexpected main oscillator frequency"
     369    #endif
    277370  #endif
    278371}
     
    283376    /* Re-map interrupt vectors to internal RAM */
    284377    MEMMAP = SET_MEMMAP_MAP(MEMMAP, 2);
     378  #else
     379    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     380
     381    scb->memmap = LPC17XX_SCB_MEMMAP_MAP;
    285382  #endif
    286383
     
    307404    /* Enable fast IO for ports 0 and 1 */
    308405    SCS |= 0x1;
     406  #else
     407    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     408
     409    #if LPC24XX_CCLK <= 20000000U
     410      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x0);
     411    #elif LPC24XX_CCLK <= 40000000U
     412      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x1);
     413    #elif LPC24XX_CCLK <= 60000000U
     414      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x2);
     415    #elif LPC24XX_CCLK <= 80000000U
     416      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x3);
     417    #elif LPC24XX_CCLK <= 100000000U
     418      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x4);
     419    #else
     420      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x5);
     421    #endif
    309422  #endif
    310423}
     
    315428    #ifdef ARM_MULTILIB_ARCH_V4
    316429      bool has_power = (PCONP & PCONP_GPDMA) != 0;
     430    #else
     431      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     432      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_GPDMA) != 0;
    317433    #endif
    318434
     
    322438      #ifdef ARM_MULTILIB_ARCH_V4
    323439        PCONP &= ~PCONP_GPDMA;
     440      #else
     441        scb->pconp &= ~LPC17XX_SCB_PCONP_GPDMA;
    324442      #endif
    325443    }
     
    332450    #ifdef ARM_MULTILIB_ARCH_V4
    333451      bool has_power = (PCONP & PCONP_ETHERNET) != 0;
     452    #else
     453      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     454      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_ENET) != 0;
    334455    #endif
    335456
     
    341462      #ifdef ARM_MULTILIB_ARCH_V4
    342463        PCONP &= ~PCONP_ETHERNET;
     464      #else
     465        scb->pconp &= ~LPC17XX_SCB_PCONP_ENET;
    343466      #endif
    344467    }
     
    351474    #ifdef ARM_MULTILIB_ARCH_V4
    352475      bool has_power = (PCONP & PCONP_USB) != 0;
     476    #else
     477      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
     478      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_USB) != 0;
    353479    #endif
    354480
     
    358484      #ifdef ARM_MULTILIB_ARCH_V4
    359485        PCONP &= ~PCONP_USB;
    360       #endif
     486      #else
     487        scb->pconp &= ~LPC17XX_SCB_PCONP_USB;
     488        scb->usbclksel = 0;
     489      #endif
     490    }
     491  #endif
     492}
     493
     494static BSP_START_TEXT_SECTION void lpc24xx_init_mpu(void)
     495{
     496  #ifdef ARM_MULTILIB_ARCH_V7M
     497    volatile ARMV7M_MPU *mpu = _ARMV7M_MPU;
     498    size_t n = sizeof(lpc24xx_start_config_mpu_regions)
     499      / sizeof(lpc24xx_start_config_mpu_regions [0]);
     500    size_t i = 0;
     501
     502    for (i = 0; i < n; ++i) {
     503      mpu->rbar = lpc24xx_start_config_mpu_regions [i].rbar;
     504      mpu->rasr = lpc24xx_start_config_mpu_regions [i].rasr;
     505    }
     506
     507    if (n > 0) {
     508      mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE;
    361509    }
    362510  #endif
     
    376524  lpc24xx_init_memory_accelerator();
    377525  lpc24xx_init_emc_dynamic();
     526  lpc24xx_init_mpu();
    378527  lpc24xx_stop_gpdma();
    379528  lpc24xx_stop_ethernet();
  • c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c

    r1f8771d2 r14ee5a1e  
    88
    99/*
    10  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
     
    1919 * found in the file LICENSE in this distribution or at
    2020 * http://www.rtems.com/license/LICENSE.
    21  *
    22  * $Id$
    2321 */
    2422
     
    4139  LPC24XX_PIN_EMC_OE,
    4240  LPC24XX_PIN_EMC_CS_1,
     41#endif
     42#if defined(LPC24XX_EMC_IS42S32800B)
     43  LPC24XX_PIN_EMC_A_0_14,
     44  LPC24XX_PIN_EMC_D_0_31,
     45  LPC24XX_PIN_EMC_RAS,
     46  LPC24XX_PIN_EMC_CAS,
     47  LPC24XX_PIN_EMC_WE,
     48  LPC24XX_PIN_EMC_DYCS_0,
     49  LPC24XX_PIN_EMC_CLK_0,
     50  LPC24XX_PIN_EMC_CKE_0,
     51  LPC24XX_PIN_EMC_DQM_0,
     52  LPC24XX_PIN_EMC_DQM_1,
     53  LPC24XX_PIN_EMC_DQM_2,
     54  LPC24XX_PIN_EMC_DQM_3,
    4355#endif
    4456#if defined(LPC24XX_EMC_W9825G2JB75I) \
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