Changeset 1485a58 in rtems


Ignore:
Timestamp:
Sep 18, 2013, 1:44:42 PM (7 years ago)
Author:
Christian Mauderer <Christian.Mauderer@…>
Branches:
4.11, master
Children:
df74da0
Parents:
0282e83
git-author:
Christian Mauderer <Christian.Mauderer@…> (09/18/13 13:44:42)
git-committer:
Sebastian Huber <sebastian.huber@…> (09/19/13 11:18:04)
Message:

bsp/stm32f4: Add STM32F10XXX support.

Location:
c/src/lib/libbsp/arm/stm32f4
Files:
7 added
10 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/stm32f4/Makefile.am

    r0282e83 r1485a58  
    2020
    2121EXTRA_DIST = startup/linkcmds.stm32f4
     22EXTRA_DIST += startup/linkcmds.stm32f105rc
    2223
    2324###############################################################################
     
    4748include_bsp_HEADERS += include/usart.h
    4849include_bsp_HEADERS += include/stm32f4.h
     50include_bsp_HEADERS += include/stm32f10xxx_gpio.h
     51include_bsp_HEADERS += include/stm32f10xxx_rcc.h
     52include_bsp_HEADERS += include/stm32f4xxxx_gpio.h
     53include_bsp_HEADERS += include/stm32f4xxxx_rcc.h
     54include_bsp_HEADERS += include/stm32_usart.h
    4955include_bsp_HEADERS += include/io.h
    5056include_bsp_HEADERS += include/rcc.h
  • c/src/lib/libbsp/arm/stm32f4/configure.ac

    r0282e83 r1485a58  
    1818RTEMS_BSPOPTS_HELP([BSP_SMALL_MEMORY],[disable testsuite samples with high memory demands])
    1919
     20RTEMS_BSPOPTS_SET([STM32F4_FAMILY_F10XXX],[stm32f1*],[1])
     21RTEMS_BSPOPTS_HELP([STM32F4_FAMILY_F10XXX],[Chip belongs to the STM32F10XXX family.])
     22
     23RTEMS_BSPOPTS_SET([STM32F4_FAMILY_F4XXXX],[stm32f4*],[1])
     24RTEMS_BSPOPTS_HELP([STM32F4_FAMILY_F4XXXX],[Chip belongs to the STM32F4XXXX family.])
     25
    2026RTEMS_BSPOPTS_SET([STM32F4_HSE_OSCILLATOR],[*],[8000000])
    2127RTEMS_BSPOPTS_HELP([STM32F4_HSE_OSCILLATOR],[HSE oscillator frequency in Hz])
    2228
     29RTEMS_BSPOPTS_SET([STM32F4_SYSCLK],[stm32f1*],[8000000])
    2330RTEMS_BSPOPTS_SET([STM32F4_SYSCLK],[*],[16000000])
    2431RTEMS_BSPOPTS_HELP([STM32F4_SYSCLK],[SYSCLK frequency in Hz])
    2532
     33RTEMS_BSPOPTS_SET([STM32F4_HCLK],[stm32f1*],[8000000])
    2634RTEMS_BSPOPTS_SET([STM32F4_HCLK],[*],[16000000])
    2735RTEMS_BSPOPTS_HELP([STM32F4_HCLK],[HCLK frequency in Hz])
    2836
     37RTEMS_BSPOPTS_SET([STM32F4_PCLK1],[stm32f1*],[8000000])
    2938RTEMS_BSPOPTS_SET([STM32F4_PCLK1],[*],[16000000])
    3039RTEMS_BSPOPTS_HELP([STM32F4_PCLK1],[PCLK1 frequency in Hz])
    3140
     41RTEMS_BSPOPTS_SET([STM32F4_PCLK1],[stm32f1*],[8000000])
    3242RTEMS_BSPOPTS_SET([STM32F4_PCLK2],[*],[16000000])
    3343RTEMS_BSPOPTS_HELP([STM32F4_PCLK2],[PCLK2 frequency in Hz])
  • c/src/lib/libbsp/arm/stm32f4/console/usart.c

    r0282e83 r1485a58  
    4040  STM32F4_RCC_UART4,
    4141  STM32F4_RCC_UART5,
     42#ifdef STM32F4_FAMILY_F4XXXX
    4243  STM32F4_RCC_USART6
     44#endif /* STM32F4_FAMILY_F4XXXX */
    4345};
    4446
  • c/src/lib/libbsp/arm/stm32f4/include/io.h

    r0282e83 r1485a58  
    1717
    1818#include <stdbool.h>
    19 
    20 #include <bsp/stm32f4.h>
     19#include <stdint.h>
     20#include <bspopts.h>
    2121
    2222#ifdef __cplusplus
    2323extern "C" {
    2424#endif /* __cplusplus */
     25
     26#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
     27
     28#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
     29
     30#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
     31
     32#ifdef STM32F4_FAMILY_F4XXXX
    2533
    2634typedef enum {
     
    8795} stm32f4_gpio_af;
    8896
    89 #define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
    90 
    91 #define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
    92 
    93 #define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
    94 
    9597typedef union {
    9698  struct {
     
    109111} stm32f4_gpio_config;
    110112
    111 extern const stm32f4_gpio_config stm32f4_start_config_gpio [];
    112 
    113 void stm32f4_gpio_set_clock(int pin, bool set);
    114 
    115 void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
    116 
    117113#define STM32F4_GPIO_CONFIG_TERMINAL \
    118114  { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } }
     115
     116#endif /* STM32F4_FAMILY_F4XXXX */
     117#ifdef STM32F4_FAMILY_F10XXX
     118
     119typedef enum {
     120  STM32F4_GPIO_MODE_INPUT,
     121  STM32F4_GPIO_MODE_OUTPUT_10MHz,
     122  STM32F4_GPIO_MODE_OUTPUT_2MHz,
     123  STM32F4_GPIO_MODE_OUTPUT_50MHz
     124} stm32f4_gpio_mode;
     125
     126typedef enum {
     127  STM32F4_GPIO_CNF_IN_ANALOG = 0,
     128  STM32F4_GPIO_CNF_IN_FLOATING = 1,
     129  STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2,
     130
     131  STM32F4_GPIO_CNF_OUT_GPIO_PP = 0,
     132  STM32F4_GPIO_CNF_OUT_GPIO_OD = 1,
     133  STM32F4_GPIO_CNF_OUT_AF_PP = 2,
     134  STM32F4_GPIO_CNF_OUT_AF_OD = 3,
     135} stm32f4_gpio_cnf;
     136
     137typedef enum {
     138  STM32F4_GPIO_REMAP_DONT_CHANGE,
     139  STM32F4_GPIO_REMAP_SPI1_0,
     140  STM32F4_GPIO_REMAP_SPI1_1,
     141  STM32F4_GPIO_REMAP_I2C1_0,
     142  STM32F4_GPIO_REMAP_I2C1_1,
     143  STM32F4_GPIO_REMAP_USART1_0,
     144  STM32F4_GPIO_REMAP_USART1_1,
     145  STM32F4_GPIO_REMAP_USART2_0,
     146  STM32F4_GPIO_REMAP_USART2_1,
     147  STM32F4_GPIO_REMAP_USART3_0,
     148  STM32F4_GPIO_REMAP_USART3_1,
     149  STM32F4_GPIO_REMAP_USART3_3,
     150  STM32F4_GPIO_REMAP_TIM1_0,
     151  STM32F4_GPIO_REMAP_TIM1_1,
     152  STM32F4_GPIO_REMAP_TIM1_3,
     153  STM32F4_GPIO_REMAP_TIM2_0,
     154  STM32F4_GPIO_REMAP_TIM2_1,
     155  STM32F4_GPIO_REMAP_TIM2_2,
     156  STM32F4_GPIO_REMAP_TIM2_3,
     157  STM32F4_GPIO_REMAP_TIM3_0,
     158  STM32F4_GPIO_REMAP_TIM3_2,
     159  STM32F4_GPIO_REMAP_TIM3_3,
     160  STM32F4_GPIO_REMAP_TIM4_0,
     161  STM32F4_GPIO_REMAP_TIM4_1,
     162  STM32F4_GPIO_REMAP_CAN1_0,
     163  STM32F4_GPIO_REMAP_CAN1_2,
     164  STM32F4_GPIO_REMAP_CAN1_3,
     165  STM32F4_GPIO_REMAP_PD01_0,
     166  STM32F4_GPIO_REMAP_PD01_1,
     167  STM32F4_GPIO_REMAP_TIM5CH4_0,
     168  STM32F4_GPIO_REMAP_TIM5CH4_1,
     169  STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0,
     170  STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1,
     171  STM32F4_GPIO_REMAP_ADC1_ETRGREG_0,
     172  STM32F4_GPIO_REMAP_ADC1_ETRGREG_1,
     173  STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0,
     174  STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1,
     175  STM32F4_GPIO_REMAP_ADC2_ETRGREG_0,
     176  STM32F4_GPIO_REMAP_ADC2_ETRGREG_1,
     177  STM32F4_GPIO_REMAP_ETH_0,
     178  STM32F4_GPIO_REMAP_ETH_1,
     179  STM32F4_GPIO_REMAP_CAN2_0,
     180  STM32F4_GPIO_REMAP_CAN2_1,
     181  STM32F4_GPIO_REMAP_MII_RMII_0,
     182  STM32F4_GPIO_REMAP_MII_RMII_1,
     183  STM32F4_GPIO_REMAP_SWJ_0,
     184  STM32F4_GPIO_REMAP_SWJ_1,
     185  STM32F4_GPIO_REMAP_SWJ_2,
     186  STM32F4_GPIO_REMAP_SWJ_4,
     187  STM32F4_GPIO_REMAP_SPI3_0,
     188  STM32F4_GPIO_REMAP_SPI3_1,
     189  STM32F4_GPIO_REMAP_TIM2ITR1_0,
     190  STM32F4_GPIO_REMAP_TIM2ITR1_1,
     191  STM32F4_GPIO_REMAP_PTP_PPS_0,
     192  STM32F4_GPIO_REMAP_PTP_PPS_1,
     193  STM32F4_GPIO_REMAP_TIM15_0,
     194  STM32F4_GPIO_REMAP_TIM15_1,
     195  STM32F4_GPIO_REMAP_TIM16_0,
     196  STM32F4_GPIO_REMAP_TIM16_1,
     197  STM32F4_GPIO_REMAP_TIM17_0,
     198  STM32F4_GPIO_REMAP_TIM17_1,
     199  STM32F4_GPIO_REMAP_CEC_0,
     200  STM32F4_GPIO_REMAP_CEC_1,
     201  STM32F4_GPIO_REMAP_TIM1_DMA_0,
     202  STM32F4_GPIO_REMAP_TIM1_DMA_1,
     203  STM32F4_GPIO_REMAP_TIM9_0,
     204  STM32F4_GPIO_REMAP_TIM9_1,
     205  STM32F4_GPIO_REMAP_TIM10_0,
     206  STM32F4_GPIO_REMAP_TIM10_1,
     207  STM32F4_GPIO_REMAP_TIM11_0,
     208  STM32F4_GPIO_REMAP_TIM11_1,
     209  STM32F4_GPIO_REMAP_TIM13_0,
     210  STM32F4_GPIO_REMAP_TIM13_1,
     211  STM32F4_GPIO_REMAP_TIM14_0,
     212  STM32F4_GPIO_REMAP_TIM14_1,
     213  STM32F4_GPIO_REMAP_FSMC_0,
     214  STM32F4_GPIO_REMAP_FSMC_1,
     215  STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0,
     216  STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1,
     217  STM32F4_GPIO_REMAP_TIM12_0,
     218  STM32F4_GPIO_REMAP_TIM12_1,
     219  STM32F4_GPIO_REMAP_MISC_0,
     220  STM32F4_GPIO_REMAP_MISC_1,
     221} stm32f4_gpio_remap;
     222
     223typedef union {
     224  struct {
     225    uint32_t pin_first : 8;
     226    uint32_t pin_last : 8;
     227    uint32_t mode : 2;
     228    uint32_t cnf : 2;
     229    uint32_t output : 1;
     230    uint32_t remap : 8;
     231    uint32_t reserved : 3;
     232  } fields;
     233
     234  uint32_t value;
     235} stm32f4_gpio_config;
     236
     237#define STM32F4_GPIO_CONFIG_TERMINAL \
     238  { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } }
     239
     240#endif /* STM32F4_FAMILY_F10XXX */
     241
     242extern const stm32f4_gpio_config stm32f4_start_config_gpio [];
     243
     244void stm32f4_gpio_set_clock(int pin, bool set);
     245
     246void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
    119247
    120248/**
     
    127255
    128256bool stm32f4_gpio_get_input(int pin);
     257
     258#ifdef STM32F4_FAMILY_F4XXXX
    129259
    130260#define STM32F4_PIN_USART(port, idx, altfunc) \
     
    167297#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6)
    168298
     299#endif /* STM32F4_FAMILY_F4XXXX */
     300#ifdef STM32F4_FAMILY_F10XXX
     301
     302#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \
     303  { \
     304    { \
     305      .pin_first = STM32F4_GPIO_PIN(port, idx), \
     306      .pin_last = STM32F4_GPIO_PIN(port, idx), \
     307      .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
     308      .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \
     309      .output = 0, \
     310      .remap = remapvalue \
     311    } \
     312  }
     313
     314#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \
     315  { \
     316    { \
     317      .pin_first = STM32F4_GPIO_PIN(port, idx), \
     318      .pin_last = STM32F4_GPIO_PIN(port, idx), \
     319      .mode = STM32F4_GPIO_MODE_INPUT, \
     320      .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \
     321      .output = 0, \
     322      .remap = remapvalue \
     323    } \
     324  }
     325
     326#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0,  9, STM32F4_GPIO_REMAP_USART1_0)
     327#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0)
     328#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1,  6, STM32F4_GPIO_REMAP_USART1_1)
     329#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1,  7, STM32F4_GPIO_REMAP_USART1_1)
     330
     331#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0,  2, STM32F4_GPIO_REMAP_USART2_0)
     332#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0,  3, STM32F4_GPIO_REMAP_USART2_0)
     333#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3,  5, STM32F4_GPIO_REMAP_USART2_1)
     334#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3,  6, STM32F4_GPIO_REMAP_USART2_1)
     335
     336#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0)
     337#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0)
     338#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1)
     339#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1)
     340#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3,  8, STM32F4_GPIO_REMAP_USART3_3)
     341#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3,  9, STM32F4_GPIO_REMAP_USART3_3)
     342
     343#define STM32F4_PIN_UART4_TX        STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
     344#define STM32F4_PIN_UART4_RX        STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
     345
     346#define STM32F4_PIN_UART5_TX        STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE)
     347#define STM32F4_PIN_UART5_RX        STM32F4_PIN_USART_RX(3,  2, STM32F4_GPIO_REMAP_DONT_CHANGE)
     348
     349#endif /* STM32F4_FAMILY_F10XXX */
     350
    169351#ifdef __cplusplus
    170352}
  • c/src/lib/libbsp/arm/stm32f4/include/rcc.h

    r0282e83 r1485a58  
    1717
    1818#include <stdbool.h>
    19 
    20 #include <bsp/stm32f4.h>
     19#include <bspopts.h>
    2120
    2221#ifdef __cplusplus
     
    2726
    2827typedef enum {
     28#ifdef STM32F4_FAMILY_F4XXXX
    2929  STM32F4_RCC_OTGHS = STM32F4_RCC_INDEX(0, 29),
    3030  STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 25),
     
    8787  STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(5, 1),
    8888  STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(5, 0),
     89#endif /* STM32F4_FAMILY_F4XXXX */
     90#ifdef STM32F4_FAMILY_F10XXX
     91  STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 0),
     92  STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 1),
     93  STM32F4_RCC_SRAM = STM32F4_RCC_INDEX(0, 2),
     94  STM32F4_RCC_FLITF = STM32F4_RCC_INDEX(0, 4),
     95  STM32F4_RCC_CRCEN = STM32F4_RCC_INDEX(0, 6),
     96  STM32F4_RCC_FSMC = STM32F4_RCC_INDEX(0, 8),
     97  STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(0, 10),
     98  STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(0, 12),
     99  STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 14),
     100  STM32F4_RCC_ETHMACTX = STM32F4_RCC_INDEX(0, 15),
     101  STM32F4_RCC_ETHMACRX = STM32F4_RCC_INDEX(0, 16),
     102
     103  STM32F4_RCC_AFIO = STM32F4_RCC_INDEX(1, 0),
     104  STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(1, 2),
     105  STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(1, 3),
     106  STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(1, 4),
     107  STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(1, 5),
     108  STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(1, 6),
     109  STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(1, 7),
     110  STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(1, 8),
     111  STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(1, 9),
     112  STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(1, 10),
     113  STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(1, 11),
     114  STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(1, 12),
     115  STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(1, 13),
     116  STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(1, 14),
     117  STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(1, 15),
     118  STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(1, 19),
     119  STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(1, 20),
     120  STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(1, 21),
     121
     122  STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(2, 0),
     123  STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(2, 1),
     124  STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(2, 2),
     125  STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(2, 3),
     126  STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(2, 4),
     127  STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(2, 5),
     128  STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(2, 6),
     129  STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(2, 7),
     130  STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(2, 8),
     131  STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(2, 11),
     132  STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(2, 14),
     133  STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(2, 15),
     134  STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(2, 17),
     135  STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(2, 18),
     136  STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(2, 19),
     137  STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(2, 20),
     138  STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(2, 21),
     139  STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(2, 22),
     140  STM32F4_RCC_USB = STM32F4_RCC_INDEX(2, 23),
     141  STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(2, 24),
     142  STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(2, 25),
     143  STM32F4_RCC_BKP = STM32F4_RCC_INDEX(2, 27),
     144  STM32F4_RCC_PWR = STM32F4_RCC_INDEX(2, 28),
     145  STM32F4_RCC_DAC = STM32F4_RCC_INDEX(2, 29),
     146#endif /* STM32F4_FAMILY_F10XXX */
    89147} stm32f4_rcc_index;
    90148
     
    95153void stm32f4_rcc_set_clock(stm32f4_rcc_index index, bool set);
    96154
     155#ifdef STM32F4_FAMILY_F4XXXX
    97156void stm32f4_rcc_set_low_power_clock(stm32f4_rcc_index index, bool set);
     157#endif /* STM32F4_FAMILY_F4XXXX */
    98158
    99159#ifdef __cplusplus
  • c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h

    r0282e83 r1485a58  
    1717
    1818#include <bsp/utility.h>
     19#include <bspopts.h>
    1920
    2021#define STM32F4_BASE 0x00
    2122
    22 typedef struct {
    23         uint32_t moder;
    24         uint32_t otyper;
    25         uint32_t ospeedr;
    26         uint32_t pupdr;
    27         uint32_t idr;
    28         uint32_t odr;
    29         uint32_t bsrr;
    30         uint32_t lckr;
    31         uint32_t afr [2];
    32         uint32_t reserved_28 [246];
    33 } stm32f4_gpio;
     23#ifdef STM32F4_FAMILY_F4XXXX
    3424
     25#include <bsp/stm32f4xxxx_gpio.h>
    3526#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40020000) + (i))
    3627
    37 typedef struct {
    38         uint32_t cr;
    39         uint32_t pllcfgr;
    40         uint32_t cfgr;
    41         uint32_t cir;
    42         uint32_t ahbrstr [3];
    43         uint32_t reserved_1c;
    44         uint32_t apbrstr [2];
    45         uint32_t reserved_28 [2];
    46         uint32_t ahbenr [3];
    47         uint32_t reserved_3c;
    48         uint32_t apbenr [2];
    49         uint32_t reserved_48 [2];
    50         uint32_t ahblpenr [3];
    51         uint32_t reserved_5c;
    52         uint32_t apblpenr [2];
    53         uint32_t reserved_68 [2];
    54         uint32_t bdcr;
    55         uint32_t csr;
    56         uint32_t reserved_78 [2];
    57         uint32_t sscgr;
    58         uint32_t plli2scfgr;
    59 } stm32f4_rcc;
    60 
     28#include <bsp/stm32f4xxxx_rcc.h>
    6129#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800))
    6230
    63 typedef struct {
    64         uint32_t sr;
    65 #define STM32F4_USART_SR_CTS BSP_BIT32(9)
    66 #define STM32F4_USART_SR_LBD BSP_BIT32(8)
    67 #define STM32F4_USART_SR_TXE BSP_BIT32(7)
    68 #define STM32F4_USART_SR_TC BSP_BIT32(6)
    69 #define STM32F4_USART_SR_RXNE BSP_BIT32(5)
    70 #define STM32F4_USART_SR_IDLE BSP_BIT32(4)
    71 #define STM32F4_USART_SR_ORE BSP_BIT32(3)
    72 #define STM32F4_USART_SR_NF BSP_BIT32(2)
    73 #define STM32F4_USART_SR_FE BSP_BIT32(1)
    74 #define STM32F4_USART_SR_PE BSP_BIT32(0)
    75         uint32_t dr;
    76 #define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7)
    77 #define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7)
    78 #define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
    79         uint32_t bbr;
    80 #define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15)
    81 #define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15)
    82 #define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15)
    83 #define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3)
    84 #define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3)
    85 #define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
    86         uint32_t cr1;
    87 #define STM32F4_USART_CR1_OVER8 BSP_BIT32(15)
    88 #define STM32F4_USART_CR1_UE BSP_BIT32(13)
    89 #define STM32F4_USART_CR1_M BSP_BIT32(12)
    90 #define STM32F4_USART_CR1_WAKE BSP_BIT32(11)
    91 #define STM32F4_USART_CR1_PCE BSP_BIT32(10)
    92 #define STM32F4_USART_CR1_PS BSP_BIT32(9)
    93 #define STM32F4_USART_CR1_PEIE BSP_BIT32(8)
    94 #define STM32F4_USART_CR1_TXEIE BSP_BIT32(7)
    95 #define STM32F4_USART_CR1_TCIE BSP_BIT32(6)
    96 #define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5)
    97 #define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4)
    98 #define STM32F4_USART_CR1_TE BSP_BIT32(3)
    99 #define STM32F4_USART_CR1_RE BSP_BIT32(2)
    100 #define STM32F4_USART_CR1_RWU BSP_BIT32(1)
    101 #define STM32F4_USART_CR1_SBK BSP_BIT32(0)
    102         uint32_t cr2;
    103 #define STM32F4_USART_CR2_LINEN BSP_BIT32(14)
    104 #define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13)
    105 #define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13)
    106 #define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
    107 #define STM32F4_USART_CR2_CLKEN BSP_BIT32(11)
    108 #define STM32F4_USART_CR2_CPOL BSP_BIT32(10)
    109 #define STM32F4_USART_CR2_CPHA BSP_BIT32(9)
    110 #define STM32F4_USART_CR2_LBCL BSP_BIT32(8)
    111 #define STM32F4_USART_CR2_LBDIE BSP_BIT32(6)
    112 #define STM32F4_USART_CR2_LBDL BSP_BIT32(5)
    113 #define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3)
    114 #define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3)
    115 #define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
    116         uint32_t cr3;
    117 #define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11)
    118 #define STM32F4_USART_CR3_CTSIE BSP_BIT32(10)
    119 #define STM32F4_USART_CR3_CTSE BSP_BIT32(9)
    120 #define STM32F4_USART_CR3_RTSE BSP_BIT32(8)
    121 #define STM32F4_USART_CR3_DMAT BSP_BIT32(7)
    122 #define STM32F4_USART_CR3_DMAR BSP_BIT32(6)
    123 #define STM32F4_USART_CR3_SCEN BSP_BIT32(5)
    124 #define STM32F4_USART_CR3_NACK BSP_BIT32(4)
    125 #define STM32F4_USART_CR3_HDSEL BSP_BIT32(3)
    126 #define STM32F4_USART_CR3_IRLP BSP_BIT32(2)
    127 #define STM32F4_USART_CR3_IREN BSP_BIT32(1)
    128 #define STM32F4_USART_CR3_EIE BSP_BIT32(0)
    129         uint32_t gtpr;
    130 #define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15)
    131 #define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15)
    132 #define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
    133 #define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7)
    134 #define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7)
    135 #define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
    136 } stm32f4_usart;
    137 
     31#include <bsp/stm32_usart.h>
    13832#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000))
    13933#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400))
     
    14337#define STM32F4_USART_6 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400))
    14438
    145 typedef struct {
    146         uint32_t reserved_00 [268439808];
    147         stm32f4_usart usart_2;
    148         uint32_t reserved_4000441c [249];
    149         stm32f4_usart usart_3;
    150         uint32_t reserved_4000481c [249];
    151         stm32f4_usart usart_4;
    152         uint32_t reserved_40004c1c [249];
    153         stm32f4_usart usart_5;
    154         uint32_t reserved_4000501c [12281];
    155         stm32f4_usart usart_1;
    156         uint32_t reserved_4001101c [249];
    157         stm32f4_usart usart_6;
    158         uint32_t reserved_4001141c [15097];
    159         stm32f4_gpio gpio [9];
    160         uint32_t reserved_40022400 [1280];
    161         stm32f4_rcc rcc;
    162 } stm32f4;
     39#endif /* STM32F4_FAMILY_F4XXXX */
    16340
    164 #define STM32F4 (*(volatile stm32f4 *) (STM32F4_BASE))
     41#ifdef STM32F4_FAMILY_F10XXX
     42
     43#include <bsp/stm32f10xxx_gpio.h>
     44#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40010800 + i * 0x400))
     45#define STM32F4_AFIO ((volatile stm32f4_afio *) (STM32F4_BASE + 0x40010000))
     46
     47#include <bsp/stm32f10xxx_rcc.h>
     48#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40021000))
     49
     50#include <bsp/stm32_usart.h>
     51#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40013800))
     52#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400))
     53#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800))
     54#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00))
     55#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000))
     56
     57#endif /* STM32F4_FAMILY_F10XXX */
    16558
    16659#endif /* LIBBSP_ARM_STM32F4_STM32F4_H */
  • c/src/lib/libbsp/arm/stm32f4/preinstall.am

    r0282e83 r1485a58  
    106106PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4.h
    107107
     108$(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h: include/stm32f10xxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     109        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h
     110PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h
     111
     112$(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h: include/stm32f10xxx_rcc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     113        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h
     114PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h
     115
     116$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h: include/stm32f4xxxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     117        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h
     118PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h
     119
     120$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h: include/stm32f4xxxx_rcc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     121        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h
     122PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h
     123
     124$(PROJECT_INCLUDE)/bsp/stm32_usart.h: include/stm32_usart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     125        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32_usart.h
     126PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32_usart.h
     127
    108128$(PROJECT_INCLUDE)/bsp/io.h: include/io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    109129        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/io.h
  • c/src/lib/libbsp/arm/stm32f4/startup/io.c

    r0282e83 r1485a58  
    1515#include <bsp/io.h>
    1616#include <bsp/rcc.h>
     17#include <bsp/stm32f4.h>
    1718
    1819#include <rtems.h>
     
    4546}
    4647
     48#ifdef STM32F4_FAMILY_F10XXX
     49#define STM32F4_AFIO_REMAP_ENTRY(mod, afio_reg_v, start_v, width_v, value_v) \
     50  [mod] = { \
     51    .afio_reg = afio_reg_v, \
     52    .start = start_v, \
     53    .width = width_v, \
     54    .value = value_v, \
     55    .reserved = 0 \
     56  }
     57
     58typedef struct {
     59  uint16_t afio_reg : 3;
     60  uint16_t start : 5;
     61  uint16_t width : 2;
     62  uint16_t value : 3;
     63  uint16_t reserved : 3;
     64} stm32f4_afio_remap_entry;
     65
     66static const stm32f4_afio_remap_entry stm32f4_afio_remap_table [] = {
     67  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_DONT_CHANGE, 0, 0, 0, 0),
     68  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI1_0, 1, 0, 1, 0),
     69  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI1_1, 1, 0, 1, 1),
     70  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_I2C1_0, 1, 1, 1, 0),
     71  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_I2C1_1, 1, 1, 1, 1),
     72  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART1_0, 1, 2, 1, 0),
     73  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART1_1, 1, 2, 1, 1),
     74  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART2_0, 1, 3, 1, 0),
     75  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART2_1, 1, 3, 1, 1),
     76  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_0, 1, 4, 2, 0),
     77  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_1, 1, 4, 2, 1),
     78  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_USART3_3, 1, 4, 2, 3),
     79  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_0, 1, 6, 2, 0),
     80  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_1, 1, 6, 2, 1),
     81  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_3, 1, 6, 2, 3),
     82  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_0, 1, 8, 2, 0),
     83  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_1, 1, 8, 2, 1),
     84  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_2, 1, 8, 2, 2),
     85  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2_3, 1, 8, 2, 3),
     86  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_0, 1, 10, 2, 0),
     87  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_2, 1, 10, 2, 2),
     88  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM3_3, 1, 10, 2, 3),
     89  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM4_0, 1, 12, 1, 0),
     90  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM4_1, 1, 12, 1, 1),
     91  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_0, 1, 13, 2, 0),
     92  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_2, 1, 13, 2, 2),
     93  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN1_3, 1, 13, 2, 3),
     94  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PD01_0, 1, 15, 1, 0),
     95  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PD01_1, 1, 15, 1, 1),
     96  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM5CH4_0, 1, 16, 1, 0),
     97  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM5CH4_1, 1, 16, 1, 1),
     98  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, 1, 17, 1, 0),
     99  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, 1, 17, 1, 1),
     100  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, 1, 18, 1, 0),
     101  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, 1, 18, 1, 1),
     102  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, 1, 19, 1, 0),
     103  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, 1, 19, 1, 1),
     104  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, 1, 20, 1, 0),
     105  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, 1, 20, 1, 1),
     106  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ETH_0, 1, 21, 1, 0),
     107  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_ETH_1, 1, 21, 1, 1),
     108  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN2_0, 1, 22, 1, 0),
     109  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CAN2_1, 1, 22, 1, 1),
     110  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MII_RMII_0, 1, 23, 1, 0),
     111  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MII_RMII_1, 1, 23, 1, 1),
     112  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_0, 1, 24, 3, 0),
     113  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_1, 1, 24, 3, 1),
     114  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_2, 1, 24, 3, 2),
     115  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SWJ_4, 1, 24, 3, 4),
     116  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI3_0, 1, 28, 1, 0),
     117  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_SPI3_1, 1, 28, 1, 1),
     118  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2ITR1_0, 1, 29, 1, 0),
     119  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM2ITR1_1, 1, 29, 1, 1),
     120  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PTP_PPS_0, 1, 30, 1, 0),
     121  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_PTP_PPS_1, 1, 30, 1, 1),
     122  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM15_0, 6, 0, 1, 0),
     123  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM15_1, 6, 0, 1, 1),
     124  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM16_0, 6, 1, 1, 0),
     125  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM16_1, 6, 1, 1, 1),
     126  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM17_0, 6, 2, 1, 0),
     127  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM17_1, 6, 2, 1, 1),
     128  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CEC_0, 6, 3, 1, 0),
     129  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_CEC_1, 6, 3, 1, 1),
     130  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_DMA_0, 6, 4, 1, 0),
     131  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM1_DMA_1, 6, 4, 1, 1),
     132  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM9_0, 6, 5, 1, 0),
     133  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM9_1, 6, 5, 1, 1),
     134  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM10_0, 6, 6, 1, 0),
     135  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM10_1, 6, 6, 1, 1),
     136  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM11_0, 6, 7, 1, 0),
     137  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM11_1, 6, 7, 1, 1),
     138  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM13_0, 6, 8, 1, 0),
     139  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM13_1, 6, 8, 1, 1),
     140  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM14_0, 6, 9, 1, 0),
     141  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM14_1, 6, 9, 1, 1),
     142  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_FSMC_0, 6, 10, 1, 0),
     143  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_FSMC_1, 6, 10, 1, 1),
     144  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, 6, 11, 1, 0),
     145  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, 6, 11, 1, 1),
     146  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM12_0, 6, 12, 1, 0),
     147  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_TIM12_1, 6, 12, 1, 1),
     148  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MISC_0, 6, 13, 1, 0),
     149  STM32F4_AFIO_REMAP_ENTRY(STM32F4_GPIO_REMAP_MISC_1, 6, 13, 1, 1),
     150};
     151
     152static void set_remap_config(stm32f4_gpio_remap remap)
     153{
     154  if(remap != STM32F4_GPIO_REMAP_DONT_CHANGE)
     155  {
     156    stm32f4_afio_remap_entry entry = stm32f4_afio_remap_table[remap];
     157    volatile stm32f4_afio *afio = STM32F4_AFIO;
     158    volatile uint32_t *reg = ((uint32_t*) afio) + entry.afio_reg;
     159    uint32_t mask = (1 << entry.width) - 1;
     160    uint32_t value = *reg;
     161
     162    value &= mask << entry.start;
     163    value |= entry.value << entry.start;
     164
     165    *reg = value;
     166  }
     167}
     168
     169#endif /* STM32F4_FAMILY_F10XXX */
     170
    47171static void set_config(unsigned pin, const stm32f4_gpio_config *config)
    48172{
     
    50174  volatile stm32f4_gpio *gpio = STM32F4_GPIO(port);
    51175  unsigned index = STM32F4_GPIO_INDEX_OF_PIN(pin);
     176  rtems_interrupt_level level;
     177  int set_or_clear_offset = config->fields.output ? 0 : 16;
     178#ifdef STM32F4_FAMILY_F4XXXX
    52179  unsigned af_reg = index >> 3;
    53180  unsigned af_index = index & 0x7;
    54   int set_or_clear_offset = config->fields.output ? 0 : 16;
    55   rtems_interrupt_level level;
    56181
    57182  rtems_interrupt_disable(level);
     
    63188  clear_and_set(&gpio->moder, index, 2, config->fields.mode);
    64189  rtems_interrupt_enable(level);
     190
     191#endif /* STM32F4_FAMILY_F4XXXX */
     192#ifdef STM32F4_FAMILY_F10XXX
     193  unsigned cr_reg = index >> 3;
     194  unsigned cr_index = index & 3;
     195
     196  rtems_interrupt_disable(level);
     197  gpio->bsrr = 1U << (index + set_or_clear_offset);
     198  clear_and_set(&gpio->cr[cr_reg], cr_index, 4,
     199    (config->fields.cnf << 2) | config->fields.mode);
     200  set_remap_config(config->fields.remap);
     201  rtems_interrupt_enable(level);
     202
     203#endif /* STM32F4_FAMILY_F10XXX */
    65204}
    66205
     
    69208  int current = config->fields.pin_first;
    70209  int last = config->fields.pin_last;
     210
     211#ifdef STM32F4_FAMILY_F10XXX
     212  stm32f4_rcc_set_clock(STM32F4_RCC_AFIO, true);
     213#endif /* STM32F4_FAMILY_F10XXX */
    71214
    72215  while (current <= last) {
  • c/src/lib/libbsp/arm/stm32f4/startup/rcc.c

    r0282e83 r1485a58  
    1414
    1515#include <bsp/rcc.h>
     16#include <bsp/stm32f4.h>
    1617
    1718#include <rtems.h>
     
    5051  volatile stm32f4_rcc *rcc = STM32F4_RCC;
    5152
     53#ifdef STM32F4_FAMILY_F4XXXX
    5254  rcc_set(index, set, &rcc->ahbrstr [0]);
     55#endif/* STM32F4_FAMILY_F4XXXX */
     56#ifdef STM32F4_FAMILY_F10XXX
     57  /* The first register is missing for the reset-block */
     58  rcc_set(index, set, &rcc->cir);
     59#endif /* STM32F4_FAMILY_F10XXX */
    5360}
    5461
     
    6067}
    6168
     69#ifdef STM32F4_FAMILY_F4XXXX
    6270void stm32f4_rcc_set_low_power_clock(stm32f4_rcc_index index, bool set)
    6371{
     
    6674  rcc_set(index, set, &rcc->ahblpenr [0]);
    6775}
     76#endif /* STM32F4_FAMILY_F4XXXX */
  • c/src/lib/libbsp/arm/stm32f4/startup/start-config-io.c

    r0282e83 r1485a58  
    1717
    1818const stm32f4_gpio_config stm32f4_start_config_gpio [] = {
     19#ifdef STM32F4_FAMILY_F4XXXX
    1920  #ifdef STM32F4_ENABLE_USART_1
    2021    STM32F4_PIN_USART1_TX_PA9,
     
    4142    STM32F4_PIN_USART6_RX_PC7,
    4243  #endif
     44#endif /* STM32F4_FAMILY_F4XXXX */
     45#ifdef STM32F4_FAMILY_F10XXX
     46  #ifdef STM32F4_ENABLE_USART_1
     47    STM32F4_PIN_USART1_TX_MAP_0,
     48    STM32F4_PIN_USART1_RX_MAP_0,
     49  #endif
     50  #ifdef STM32F4_ENABLE_USART_2
     51    STM32F4_PIN_USART2_TX_MAP_0,
     52    STM32F4_PIN_USART2_RX_MAP_0,
     53  #endif
     54  #ifdef STM32F4_ENABLE_USART_3
     55    STM32F4_PIN_USART3_TX_MAP_0,
     56    STM32F4_PIN_USART3_RX_MAP_0,
     57  #endif
     58  #ifdef STM32F4_ENABLE_UART_4
     59    STM32F4_PIN_UART4_TX,
     60    STM32F4_PIN_UART4_RX,
     61  #endif
     62  #ifdef STM32F4_ENABLE_UART_5
     63    STM32F4_PIN_UART5_TX,
     64    STM32F4_PIN_UART5_RX,
     65  #endif
     66#endif /* STM32F4_FAMILY_F10XXX */
    4367  STM32F4_GPIO_CONFIG_TERMINAL
    4468};
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