Ignore:
Timestamp:
Jun 5, 2014, 8:03:55 AM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
c19342a7
Parents:
2a1d86c
git-author:
Sebastian Huber <sebastian.huber@…> (06/05/14 08:03:55)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/06/14 06:02:10)
Message:

bsp/altera-cyclone-v: Enable unified L2 cache

Location:
c/src/lib/libbsp/arm/altera-cyclone-v/startup
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c

    r2a1d86c r1468d70  
    5656    );
    5757
    58     started = true;
     58    /*
     59     * Wait for secondary processor to complete its basic initialization so
     60     * that we can enable the unified L2 cache.
     61     */
     62    started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
    5963  } else {
    6064    started = false;
     
    7781    );
    7882    assert(sc == RTEMS_SUCCESSFUL);
     83
     84    /* Enable unified L2 cache */
     85    rtems_cache_enable_data();
    7986  }
    8087}
  • c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c

    r2a1d86c r1468d70  
    105105  bsp_start_copy_sections();
    106106  setup_mmu_and_cache();
     107#ifndef RTEMS_SMP
     108  /* Enable unified L2 cache */
     109  rtems_cache_enable_data();
     110#endif
    107111  bsp_start_clear_bss();
    108112}
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