Changeset 143c8d0 in rtems for bsps


Ignore:
Timestamp:
Oct 17, 2018, 7:43:55 AM (12 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
c980eaf
Parents:
d7c13c8
git-author:
Sebastian Huber <sebastian.huber@…> (10/17/18 07:43:55)
git-committer:
Sebastian Huber <sebastian.huber@…> (10/17/18 07:58:14)
Message:

serial/ns16550: Fix precision clock synthesizer

The precision clock synthesizer support broke the driver on the QorIQ
P1020. On this device the Alternate Function Register is accessed with
DLAB == 1 instead of the FIFO Control Register (FCR). Restructure the
code to account for this.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/shared/dev/serial/ns16550-context.c

    rd7c13c8 r143c8d0  
    192192  );
    193193
    194   /* Enable and reset transmit and receive FIFOs. TJA     */
    195   ucDataByte = SP_FIFO_ENABLE;
    196   (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte);
    197 
    198   ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST;
     194  /* Clear the divisor latch and set the character size to eight bits */
     195  /* with one stop bit and no parity checking. */
     196  ucDataByte = EIGHT_BITS;
     197  ctx->line_control = ucDataByte;
    199198
    200199  if (ctx->has_precision_clock_synthesizer) {
     200    uint8_t fcr;
     201
    201202    /*
    202203     * Enable precision clock synthesizer.  This must be done with DLAB == 1 in
    203204     * the line control register.
    204205     */
    205     ucDataByte |= 0x10;
    206   }
    207 
    208   (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte);
    209 
    210   /* Clear the divisor latch and set the character size to eight bits */
    211   /* with one stop bit and no parity checking. */
    212   ucDataByte = EIGHT_BITS;
    213   ctx->line_control = ucDataByte;
    214 
    215   if (ctx->has_precision_clock_synthesizer) {
     206    fcr = (*getReg)(pNS16550, NS16550_FIFO_CONTROL );
     207    fcr |= 0x10;
     208    (*setReg)(pNS16550, NS16550_FIFO_CONTROL, fcr);
     209
    216210    (*setReg)(pNS16550, NS16550_SCRATCH_PAD, (uint8_t)(ulBaudDivisor >> 24));
    217211    (*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte );
     
    220214    (*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte);
    221215  }
     216
     217  /* Enable and reset transmit and receive FIFOs. TJA     */
     218  ucDataByte = SP_FIFO_ENABLE;
     219  (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte);
     220
     221  ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST;
     222  (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte);
    222223
    223224  ns16550_enable_interrupts(ctx, NS16550_DISABLE_ALL_INTR);
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