Changeset 13cc89e1 in rtems


Ignore:
Timestamp:
Feb 4, 1999, 11:45:55 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
26e663d
Parents:
7397638
Message:

Reorganized into libchip style but not yet split out into multiple files
and placed in the right shareable directories.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/dmv177/sonic/sonic.c

    r7397638 r13cc89e1  
    1 void break_when_you_get_here();
    21/*
    32 *******************************************************************
     
    3433#include "sonic.h"
    3534#include <rtems/rtems_bsdnet.h>
     35
     36/***** CONFIGURATION ****/
     37typedef void (*sonic_write_register_t)(
     38  void       *base,
     39  unsigned32  regno,
     40  unsigned32  value
     41);
     42
     43typedef unsigned32 (*sonic_read_register_t)(
     44  void       *base,
     45  unsigned32  regno
     46);
     47
     48typedef struct {
     49  unsigned32              base_address;
     50  unsigned32              vector;
     51  unsigned32              dcr_value;
     52  unsigned32              dc2_value;
     53  unsigned32              tda_count;
     54  unsigned32              rda_count;
     55  sonic_write_register_t  write_register;
     56  sonic_read_register_t   read_register;
     57} sonic_configuration_t;
     58
     59/***** CONFIGURATION ****/
    3660
    3761#include <stdio.h>
     
    105129
    106130/*
    107  * Default location of device registers
    108  */
    109 #ifndef SONIC_BASE_ADDRESS
    110 # define SONIC_BASE_ADDRESS 0xF3000000
    111 # warning "Using default SONIC_BASE_ADDRESS."
    112 #endif
    113 
    114 /*
    115  * Default interrupt vector
    116  */
    117 #ifndef SONIC_VECTOR
    118 # define SONIC_VECTOR 1
    119 # warning "Using default SONIC_VECTOR."
    120 #endif
    121 
    122 /*
    123  * Default device configuration register values
    124  * Conservative, generic values.
    125  * DCR:
    126  *      No extended bus mode
    127  *      Unlatched bus retry
    128  *      Programmable outputs unused
    129  *      Asynchronous bus mode
    130  *      User definable pins unused
    131  *      No wait states (access time controlled by DTACK*)
    132  *      32-bit DMA
    133  *      Empty/Fill DMA mode
    134  *      Maximum Transmit/Receive FIFO
    135  * DC2:
    136  *      Extended programmable outputs unused
    137  *      Normal HOLD request
    138  *      Packet compress output unused
    139  *      No reject on CAM match
    140  */
    141 #define SONIC_DCR \
    142    (DCR_DW32 | DCR_WAIT0 | DCR_PO0 | DCR_PO1  | DCR_RFT24 | DCR_TFT28)
    143 #ifndef SONIC_DCR
    144 # define SONIC_DCR (DCR_DW32 | DCR_TFT28)
    145 #endif
    146 #ifndef SONIC_DC2
    147 # define SONIC_DC2 (0)
    148 #endif
    149 
    150 /*
    151  * Default sizes of transmit and receive descriptor areas
    152  */
    153 #define RDA_COUNT     20 /* 20 */
    154 #define TDA_COUNT     20 /* 10 */
    155 
    156 /*
    157131 *
    158132 * As suggested by National Application Note 746, make the
     
    214188
    215189  /*
     190   *  Register access routines
     191   */
     192  sonic_write_register_t           write_register;
     193  sonic_read_register_t            read_register;
     194 
     195  /*
    216196   * Interrupt vector
    217197   */
    218198  rtems_vector_number             vector;
     199
     200  /*
     201   * Data Configuration Register values
     202   */
     203  rtems_unsigned32                dcr_value;
     204  rtems_unsigned32                dc2_value;
    219205
    220206  /*
     
    326312 */
    327313
    328 void sonic_write_register(
    329   void       *base,
    330   unsigned32  regno,
    331   unsigned32  value
    332 );
    333 
    334 unsigned32 sonic_read_register(
    335   void       *base,
    336   unsigned32  regno
    337 );
    338 
    339314void sonic_enable_interrupts(
    340   void       *rp,
     315  struct sonic_softc *sc,
    341316  unsigned32  mask
    342317)
    343318{
     319  void *rp = sc->sonic;
    344320  rtems_interrupt_level level;
    345321
    346322  rtems_interrupt_disable( level );
    347       sonic_write_register(
     323      (*sc->write_register)(
    348324         rp,
    349325         SONIC_REG_IMR,
    350          sonic_read_register(rp, SONIC_REG_IMR) | mask
     326         (*sc->read_register)(rp, SONIC_REG_IMR) | mask
    351327      );
    352328  rtems_interrupt_enable( level );
     
    396372   * Stop the transmitter and receiver.
    397373   */
    398   sonic_write_register( rp, SONIC_REG_CR, CR_HTX | CR_RXDIS );
     374  (*sc->write_register)( rp, SONIC_REG_CR, CR_HTX | CR_RXDIS );
    399375}
    400376
     
    457433  sc->Interrupts++;
    458434
    459   isr = sonic_read_register( rp, SONIC_REG_ISR );
    460   imr = sonic_read_register( rp, SONIC_REG_IMR );
     435  isr = (*sc->read_register)( rp, SONIC_REG_ISR );
     436  imr = (*sc->read_register)( rp, SONIC_REG_IMR );
    461437
    462438  /*
     
    480456  }
    481457
    482   sonic_write_register( rp, SONIC_REG_IMR, imr );
     458  (*sc->write_register)( rp, SONIC_REG_IMR, imr );
    483459}
    484460
     
    543519        void *rp = sc->sonic;
    544520
    545         sonic_write_register( rp, SONIC_REG_CTDA, link );
    546         sonic_write_register( rp, SONIC_REG_CR, CR_TXP );
     521        (*sc->write_register)( rp, SONIC_REG_CTDA, link );
     522        (*sc->write_register)( rp, SONIC_REG_CR, CR_TXP );
    547523      }
    548524    }
     
    626602     * Clear old events.
    627603     */
    628     sonic_write_register( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
     604    (*sc->write_register)( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
    629605
    630606    /*
     
    646622       * Enable transmitter interrupts.
    647623       */
    648       sonic_enable_interrupts( rp, (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN) );
     624      sonic_enable_interrupts( sc, (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN) );
    649625
    650626      /*
     
    655631            RTEMS_NO_TIMEOUT,
    656632            &events);
    657       sonic_write_register( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
     633      (*sc->write_register)( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
    658634      sonic_retire_tda (sc);
    659635    }
     
    743719
    744720/* XXX not in KA9Q */
    745   sonic_enable_interrupts( rp, (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN) );
    746   sonic_write_register( rp, SONIC_REG_CR, CR_TXP );
     721  sonic_enable_interrupts( sc, (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN) );
     722  (*sc->write_register)( rp, SONIC_REG_CR, CR_TXP );
    747723}
    748724
     
    833809     * This would be more difficult to recover from....
    834810     */
    835     if (sonic_read_register( rp, SONIC_REG_ISR ) & ISR_RBAE) {
     811    if ((*sc->read_register)( rp, SONIC_REG_ISR ) & ISR_RBAE) {
    836812
    837813#if (SONIC_DEBUG & SONIC_DEBUG_ERRORS)
     
    853829       * Check my interpretation of the SONIC manual.
    854830       */
    855       if (sonic_read_register( rp, SONIC_REG_CR ) & CR_RXEN)
     831      if ((*sc->read_register)( rp, SONIC_REG_CR ) & CR_RXEN)
    856832        rtems_panic ("SONIC RBAE/RXEN");
    857833
     
    873849       */
    874850      for (i = 0 ; i < 2 ; i++) {
    875         if (sonic_read_register( rp, SONIC_REG_RRP ) ==
    876             sonic_read_register( rp, SONIC_REG_RSA ))
    877           sonic_write_register(
     851        if ((*sc->read_register)( rp, SONIC_REG_RRP ) ==
     852            (*sc->read_register)( rp, SONIC_REG_RSA ))
     853          (*sc->write_register)(
    878854            rp,
    879855            SONIC_REG_RRP,
    880             sonic_read_register( rp, SONIC_REG_REA )
     856            (*sc->read_register)( rp, SONIC_REG_REA )
    881857          );
    882           sonic_write_register(
     858          (*sc->write_register)(
    883859             rp,
    884860             SONIC_REG_RRP,
    885              sonic_read_register(rp, SONIC_REG_RRP) - sizeof(ReceiveResource_t)
     861             (*sc->read_register)(rp, SONIC_REG_RRP) - sizeof(ReceiveResource_t)
    886862          );
    887863      }
     
    890866       * Restart reception
    891867       */
    892       sonic_write_register( rp, SONIC_REG_ISR, ISR_RBAE );
    893       sonic_write_register( rp, SONIC_REG_CR, CR_RXEN );
     868      (*sc->write_register)( rp, SONIC_REG_ISR, ISR_RBAE );
     869      (*sc->write_register)( rp, SONIC_REG_CR, CR_RXEN );
    894870    }
    895871
     
    897873     * Clear old packet-received events.
    898874     */
    899     sonic_write_register( rp, SONIC_REG_ISR, ISR_PKTRX );
     875    (*sc->write_register)( rp, SONIC_REG_ISR, ISR_PKTRX );
    900876
    901877    /*
     
    908884     * Enable interrupts.
    909885     */
    910     sonic_enable_interrupts( rp, (IMR_PRXEN | IMR_RBAEEN) );
     886    sonic_enable_interrupts( sc, (IMR_PRXEN | IMR_RBAEEN) );
    911887
    912888    /*
     
    952928   * Start the receiver
    953929   */
    954   oldMissedTally = sonic_read_register( rp, SONIC_REG_MPT );
     930  oldMissedTally = (*sc->read_register)( rp, SONIC_REG_MPT );
    955931
    956932  /*
     
    10431019        rwp = sc->rsa;
    10441020      }
    1045       sonic_write_register( rp, SONIC_REG_RWP , LSW(rwp) );
     1021      (*sc->write_register)( rp, SONIC_REG_RWP , LSW(rwp) );
    10461022
    10471023      /*
    10481024       * Tell the SONIC to reread the RRA.
    10491025       */
    1050       if (sonic_read_register( rp, SONIC_REG_ISR ) & ISR_RBE)
    1051         sonic_write_register( rp, SONIC_REG_ISR, ISR_RBE );
     1026      if ((*sc->read_register)( rp, SONIC_REG_ISR ) & ISR_RBE)
     1027        (*sc->write_register)( rp, SONIC_REG_ISR, ISR_RBE );
    10521028    }
    10531029    else {
     
    10631039     * Count missed packets
    10641040     */
    1065     newMissedTally = sonic_read_register( rp, SONIC_REG_MPT );
     1041    newMissedTally = (*sc->read_register)( rp, SONIC_REG_MPT );
    10661042    if (newMissedTally != oldMissedTally) {
    10671043      sc->rxMissed += (newMissedTally - oldMissedTally) & 0xFFFF;
     
    11121088   */
    11131089
    1114   if ( sonic_read_register( rp, SONIC_REG_SR ) < SONIC_REVISION_C ) {
     1090  if ( (*sc->read_register)( rp, SONIC_REG_SR ) < SONIC_REVISION_C ) {
    11151091    rtems_fatal_error_occurred( 0x0BADF00D );  /* don't eat this part :) */
    11161092  }
     
    12531229   * Issue a software reset.
    12541230   */
    1255   sonic_write_register( rp, SONIC_REG_CR, CR_RST | CR_STP | CR_RXDIS | CR_HTX );
     1231  (*sc->write_register)( rp, SONIC_REG_CR, CR_RST | CR_STP | CR_RXDIS | CR_HTX );
    12561232
    12571233  /*
    12581234   * Set up data configuration registers.
    12591235   */
    1260   sonic_write_register( rp, SONIC_REG_DCR, SONIC_DCR );
    1261   sonic_write_register( rp, SONIC_REG_DCR2, SONIC_DC2 );
    1262 
    1263   sonic_write_register( rp, SONIC_REG_CR, CR_STP | CR_RXDIS | CR_HTX );
     1236  (*sc->write_register)( rp, SONIC_REG_DCR, sc->dcr_value );
     1237  (*sc->write_register)( rp, SONIC_REG_DCR2, sc->dc2_value );
     1238
     1239  (*sc->write_register)( rp, SONIC_REG_CR, CR_STP | CR_RXDIS | CR_HTX );
    12641240
    12651241  /*
    12661242   * Mask all interrupts
    12671243   */
    1268   sonic_write_register( rp, SONIC_REG_IMR, 0x0 ); /* XXX was backwards */
     1244  (*sc->write_register)( rp, SONIC_REG_IMR, 0x0 ); /* XXX was backwards */
    12691245
    12701246  /*
    12711247   * Clear outstanding interrupts.
    12721248   */
    1273   sonic_write_register( rp, SONIC_REG_ISR, 0x7FFF );
     1249  (*sc->write_register)( rp, SONIC_REG_ISR, 0x7FFF );
    12741250
    12751251  /*
     
    12771253   */
    12781254
    1279   sonic_write_register( rp, SONIC_REG_CRCT, 0xFFFF );
    1280   sonic_write_register( rp, SONIC_REG_FAET, 0xFFFF );
    1281   sonic_write_register( rp, SONIC_REG_MPT, 0xFFFF );
    1282   sonic_write_register( rp, SONIC_REG_RSC, 0 );
     1255  (*sc->write_register)( rp, SONIC_REG_CRCT, 0xFFFF );
     1256  (*sc->write_register)( rp, SONIC_REG_FAET, 0xFFFF );
     1257  (*sc->write_register)( rp, SONIC_REG_MPT, 0xFFFF );
     1258  (*sc->write_register)( rp, SONIC_REG_RSC, 0 );
    12831259
    12841260  /*
     
    12891265
    12901266  if (sc->acceptBroadcast)
    1291     sonic_write_register( rp, SONIC_REG_RCR, RCR_BRD );
     1267    (*sc->write_register)( rp, SONIC_REG_RCR, RCR_BRD );
    12921268  else
    1293     sonic_write_register( rp, SONIC_REG_RCR, 0 );
     1269    (*sc->write_register)( rp, SONIC_REG_RCR, 0 );
    12941270
    12951271  /*
     
    12971273   */
    12981274
    1299   sonic_write_register( rp, SONIC_REG_URRA, MSW(sc->rsa) );
    1300   sonic_write_register( rp, SONIC_REG_RSA, LSW(sc->rsa) );
    1301 
    1302   sonic_write_register( rp, SONIC_REG_REA, LSW(sc->rea) );
    1303 
    1304   sonic_write_register( rp, SONIC_REG_RRP, LSW(sc->rsa) );
    1305   sonic_write_register( rp, SONIC_REG_RWP, LSW(sc->rsa) ); /* XXX was rea */
    1306 
    1307   sonic_write_register( rp, SONIC_REG_URDA, MSW(sc->rda) );
    1308   sonic_write_register( rp, SONIC_REG_CRDA, LSW(sc->rda) );
    1309 
    1310   sonic_write_register( rp, SONIC_REG_UTDA, MSW(sc->tdaTail) );
    1311   sonic_write_register( rp, SONIC_REG_CTDA, LSW(sc->tdaTail) );
     1275  (*sc->write_register)( rp, SONIC_REG_URRA, MSW(sc->rsa) );
     1276  (*sc->write_register)( rp, SONIC_REG_RSA, LSW(sc->rsa) );
     1277
     1278  (*sc->write_register)( rp, SONIC_REG_REA, LSW(sc->rea) );
     1279
     1280  (*sc->write_register)( rp, SONIC_REG_RRP, LSW(sc->rsa) );
     1281  (*sc->write_register)( rp, SONIC_REG_RWP, LSW(sc->rsa) ); /* XXX was rea */
     1282
     1283  (*sc->write_register)( rp, SONIC_REG_URDA, MSW(sc->rda) );
     1284  (*sc->write_register)( rp, SONIC_REG_CRDA, LSW(sc->rda) );
     1285
     1286  (*sc->write_register)( rp, SONIC_REG_UTDA, MSW(sc->tdaTail) );
     1287  (*sc->write_register)( rp, SONIC_REG_CTDA, LSW(sc->tdaTail) );
    13121288
    13131289  /*
     
    13161292   */
    13171293
    1318   sonic_write_register( rp, SONIC_REG_EOBC, RBUF_WC - 2 );
     1294  (*sc->write_register)( rp, SONIC_REG_EOBC, RBUF_WC - 2 );
    13191295
    13201296  /*
     
    13221298   */
    13231299
    1324   sonic_write_register( rp, SONIC_REG_CR, CR_RRRA );
    1325   while (sonic_read_register( rp, SONIC_REG_CR ) & CR_RRRA)
     1300  (*sc->write_register)( rp, SONIC_REG_CR, CR_RRRA );
     1301  while ((*sc->read_register)( rp, SONIC_REG_CR ) & CR_RRRA)
    13261302    continue;
    13271303
     
    13301306   */
    13311307
    1332   sonic_write_register( rp, SONIC_REG_CR, 0 );
     1308  (*sc->write_register)( rp, SONIC_REG_CR, 0 );
    13331309
    13341310  /*
     
    13501326  cdp->ce   = 0x0001;                /* Enable first entry in CAM */
    13511327
    1352   sonic_write_register( rp, SONIC_REG_CDC, 1 );      /* 1 entry in CDA */
    1353   sonic_write_register( rp, SONIC_REG_CDP, LSW(cdp) );
    1354   sonic_write_register( rp, SONIC_REG_CR,  CR_LCAM );  /* Load the CAM */
    1355 
    1356   while (sonic_read_register( rp, SONIC_REG_CR ) & CR_LCAM)
     1328  (*sc->write_register)( rp, SONIC_REG_CDC, 1 );      /* 1 entry in CDA */
     1329  (*sc->write_register)( rp, SONIC_REG_CDP, LSW(cdp) );
     1330  (*sc->write_register)( rp, SONIC_REG_CR,  CR_LCAM );  /* Load the CAM */
     1331
     1332  while ((*sc->read_register)( rp, SONIC_REG_CR ) & CR_LCAM)
    13571333    continue;
    13581334
     
    13611337   */
    13621338
    1363   sonic_write_register( rp, SONIC_REG_CR, CR_RST | CR_STP | CR_RXDIS | CR_HTX );
     1339  (*sc->write_register)( rp, SONIC_REG_CR, CR_RST | CR_STP | CR_RXDIS | CR_HTX );
    13641340
    13651341#if (SONIC_DEBUG & SONIC_DEBUG_CAM)
    1366   sonic_write_register( rp, SONIC_REG_CEP, 0 );  /* Select first entry in CAM */
     1342  (*sc->write_register)( rp, SONIC_REG_CEP, 0 );  /* Select first entry in CAM */
    13671343    printf ("Loaded Ethernet address into SONIC CAM.\n"
    13681344      "  Wrote %04x%04x%04x - %#x\n"
    13691345      "   Read %04x%04x%04x - %#x\n",
    13701346        cdp->cap2, cdp->cap1, cdp->cap0, cdp->ce,
    1371         sonic_read_register( rp, SONIC_REG_CAP2 ),
    1372         sonic_read_register( rp, SONIC_REG_CAP1 ),
    1373         sonic_read_register( rp, SONIC_REG_CAP0 ),
    1374         sonic_read_register( rp, SONIC_REG_CE ));
    1375 #endif
    1376 
    1377   sonic_write_register( rp, SONIC_REG_CEP, 0 );  /* Select first entry in CAM */
    1378   if ((sonic_read_register( rp, SONIC_REG_CAP2 ) != cdp->cap2)
    1379    || (sonic_read_register( rp, SONIC_REG_CAP1 ) != cdp->cap1)
    1380    || (sonic_read_register( rp, SONIC_REG_CAP0 ) != cdp->cap0)
    1381    || (sonic_read_register( rp, SONIC_REG_CE ) != cdp->ce)) {
     1347        (*sc->read_register)( rp, SONIC_REG_CAP2 ),
     1348        (*sc->read_register)( rp, SONIC_REG_CAP1 ),
     1349        (*sc->read_register)( rp, SONIC_REG_CAP0 ),
     1350        (*sc->read_register)( rp, SONIC_REG_CE ));
     1351#endif
     1352
     1353  (*sc->write_register)( rp, SONIC_REG_CEP, 0 );  /* Select first entry in CAM */
     1354  if (((*sc->read_register)( rp, SONIC_REG_CAP2 ) != cdp->cap2)
     1355   || ((*sc->read_register)( rp, SONIC_REG_CAP1 ) != cdp->cap1)
     1356   || ((*sc->read_register)( rp, SONIC_REG_CAP0 ) != cdp->cap0)
     1357   || ((*sc->read_register)( rp, SONIC_REG_CE ) != cdp->ce)) {
    13821358    printf ("Failed to load Ethernet address into SONIC CAM.\n"
    13831359      "  Wrote %04x%04x%04x - %#x\n"
    13841360      "   Read %04x%04x%04x - %#x\n",
    13851361        cdp->cap2, cdp->cap1, cdp->cap0, cdp->ce,
    1386         sonic_read_register( rp, SONIC_REG_CAP2 ),
    1387         sonic_read_register( rp, SONIC_REG_CAP1 ),
    1388         sonic_read_register( rp, SONIC_REG_CAP0 ),
    1389         sonic_read_register( rp, SONIC_REG_CE ));
     1362        (*sc->read_register)( rp, SONIC_REG_CAP2 ),
     1363        (*sc->read_register)( rp, SONIC_REG_CAP1 ),
     1364        (*sc->read_register)( rp, SONIC_REG_CAP0 ),
     1365        (*sc->read_register)( rp, SONIC_REG_CE ));
    13901366    rtems_panic ("SONIC LCAM");
    13911367  }
    13921368
    1393   sonic_write_register(rp, SONIC_REG_CR, /* CR_TXP | */CR_RXEN | CR_STP);
     1369  (*sc->write_register)(rp, SONIC_REG_CR, /* CR_TXP | */CR_RXEN | CR_STP);
    13941370
    13951371  /*
     
    13971373   */
    13981374/* XXX
    1399   sonic_write_register( rp, SONIC_REG_IMR, 0 );
     1375  (*sc->write_register)( rp, SONIC_REG_IMR, 0 );
    14001376*/
    14011377  old_handler = set_vector(sonic_interrupt_handler, sc->vector, 0);
     
    14471423   * Set flags appropriately
    14481424   */
    1449   rcr = sonic_read_register( rp, SONIC_REG_RCR );
     1425  rcr = (*sc->read_register)( rp, SONIC_REG_RCR );
    14501426  if (ifp->if_flags & IFF_PROMISC)
    14511427    rcr |= RCR_PRO;
    14521428  else
    14531429    rcr &= ~RCR_PRO;
    1454   sonic_write_register( rp, SONIC_REG_RCR, rcr);
     1430  (*sc->write_register)( rp, SONIC_REG_RCR, rcr);
    14551431
    14561432  /*
     
    14621438   * Enable receiver and transmitter
    14631439   */
    1464   /* sonic_write_register( rp, SONIC_REG_IMR, 0 ); */
    1465   sonic_enable_interrupts( rp,
     1440  /* (*sc->write_register)( rp, SONIC_REG_IMR, 0 ); */
     1441  sonic_enable_interrupts( sc,
    14661442        (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN) | (IMR_PRXEN | IMR_RBAEEN) );
    14671443
    1468   sonic_write_register(rp, SONIC_REG_CR, /* CR_TXP | */ CR_RXEN);
     1444  (*sc->write_register)(rp, SONIC_REG_CR, /* CR_TXP | */ CR_RXEN);
    14691445}
    14701446
     
    15221498 * This is the only `extern' function in the driver.
    15231499 */
     1500
    15241501int
    1525 rtems_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config)
     1502rtems_sonic_driver_attach_chip (
     1503  struct rtems_bsdnet_ifconfig *config,
     1504  sonic_configuration_t *chip
     1505)
    15261506{
    15271507  struct sonic_softc *sc;
     
    15701550    sc->rdaCount = config->rbuf_count;
    15711551  else
    1572     sc->rdaCount = RDA_COUNT;
     1552    sc->rdaCount = chip->rda_count;
    15731553  if (config->xbuf_count)
    15741554    sc->tdaCount = config->xbuf_count;
    15751555  else
    1576     sc->tdaCount = TDA_COUNT;
     1556    sc->tdaCount = chip->tda_count;
    15771557  sc->acceptBroadcast = !config->ignore_broadcast;
    15781558
    1579   sc->sonic = (void *) SONIC_BASE_ADDRESS;
    1580   sc->vector = SONIC_VECTOR;
     1559  sc->sonic = (void *) chip->base_address;
     1560  sc->vector = chip->vector;
     1561  sc->dcr_value = chip->dcr_value;
     1562  sc->dc2_value  = chip->dc2_value;
     1563  sc->write_register = chip->write_register;
     1564  sc->read_register  = chip->read_register;
    15811565
    15821566  /*
     
    16741658#endif
    16751659
    1676 void sonic_write_register(
     1660void dmv177_sonic_write_register(
    16771661  void       *base,
    16781662  unsigned32  regno,
     
    16901674}
    16911675
    1692 unsigned32 sonic_read_register(
     1676unsigned32 dmv177_sonic_read_register(
    16931677  void       *base,
    16941678  unsigned32  regno
     
    17061690  return value;
    17071691}
     1692/********  DMV177 SPECIFIC INFORMATION ***********/
     1693/*
     1694 * Default sizes of transmit and receive descriptor areas
     1695 */
     1696#define RDA_COUNT     20 /* 20 */
     1697#define TDA_COUNT     20 /* 10 */
     1698
     1699/*
     1700 * Default device configuration register values
     1701 * Conservative, generic values.
     1702 * DCR:
     1703 *      No extended bus mode
     1704 *      Unlatched bus retry
     1705 *      Programmable outputs unused
     1706 *      Asynchronous bus mode
     1707 *      User definable pins unused
     1708 *      No wait states (access time controlled by DTACK*)
     1709 *      32-bit DMA
     1710 *      Empty/Fill DMA mode
     1711 *      Maximum Transmit/Receive FIFO
     1712 * DC2:
     1713 *      Extended programmable outputs unused
     1714 *      Normal HOLD request
     1715 *      Packet compress output unused
     1716 *      No reject on CAM match
     1717 */
     1718#define SONIC_DCR \
     1719   (DCR_DW32 | DCR_WAIT0 | DCR_PO0 | DCR_PO1  | DCR_RFT24 | DCR_TFT28)
     1720#ifndef SONIC_DCR
     1721# define SONIC_DCR (DCR_DW32 | DCR_TFT28)
     1722#endif
     1723#ifndef SONIC_DC2
     1724# define SONIC_DC2 (0)
     1725#endif
     1726
     1727/*
     1728 * Default location of device registers
     1729 */
     1730#ifndef SONIC_BASE_ADDRESS
     1731# define SONIC_BASE_ADDRESS 0xF3000000
     1732# warning "Using default SONIC_BASE_ADDRESS."
     1733#endif
     1734
     1735/*
     1736 * Default interrupt vector
     1737 */
     1738#ifndef SONIC_VECTOR
     1739# define SONIC_VECTOR 1
     1740# warning "Using default SONIC_VECTOR."
     1741#endif
     1742
     1743sonic_configuration_t dmv177_sonic_configuration = {
     1744  SONIC_BASE_ADDRESS,        /* base address */
     1745  SONIC_VECTOR,              /* vector number */
     1746  SONIC_DCR,                 /* DCR register value */
     1747  SONIC_DC2,                 /* DC2 register value */
     1748  TDA_COUNT,                 /* number of transmit descriptors */
     1749  RDA_COUNT,                 /* number of receive descriptors */
     1750  dmv177_sonic_write_register,
     1751  dmv177_sonic_read_register
     1752};
     1753
     1754int rtems_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config)
     1755{
     1756  return rtems_sonic_driver_attach_chip ( config, &dmv177_sonic_configuration );
     1757 
     1758}
     1759
     1760/********  DMV177 SPECIFIC INFORMATION ***********/
     1761
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