Changeset 13c985c in rtems


Ignore:
Timestamp:
Aug 31, 2016, 2:49:15 PM (3 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
master
Children:
caf2cbd
Parents:
6deb4190
git-author:
Pavel Pisa <pisa@…> (08/31/16 14:49:15)
git-committer:
Chris Johns <chrisj@…> (09/01/16 01:10:54)
Message:

arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when initialization starts.

The u-boot loader enables the MMU plus the data and instruction caches
in some versions which results in RTEMS boot failure.

Closes #2774.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c

    r6deb4190 r13c985c  
    2222BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
    2323{
     24  uint32_t sctlr_val;
     25
     26  sctlr_val = arm_cp15_get_control();
     27
     28  /*
     29   * Current U-boot loader seems to start kernel image
     30   * with I and D caches on and MMU enabled.
     31   * If RTEMS application image finds that cache is on
     32   * during startup then disable caches.
     33   */
     34  if ( sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
     35    if ( sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
     36      /*
     37       * If the data cache is on then ensure that it is clean
     38       * before switching off to be extra carefull.
     39       */
     40      arm_cp15_data_cache_clean_all_levels();
     41    }
     42    arm_cp15_flush_prefetch_buffer();
     43    sctlr_val &= ~ ( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A );
     44    arm_cp15_set_control( sctlr_val );
     45  }
     46  arm_cp15_instruction_cache_invalidate();
     47  /*
     48   * The care should be taken there that no shared levels
     49   * are invalidated by secondary CPUs in SMP case.
     50   * It is not problem on Zynq because level of coherency
     51   * is L1 only and higher level is not maintained and seen
     52   * by CP15. So no special care to limit levels on the secondary
     53   * are required there.
     54   */
     55  arm_cp15_data_cache_invalidate_all_levels();
     56  arm_cp15_branch_predictor_invalidate_all();
     57  arm_cp15_tlb_invalidate();
     58  arm_cp15_flush_prefetch_buffer();
    2459  arm_a9mpcore_start_hook_0();
    2560}
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