Changeset 139e6efe in rtems


Ignore:
Timestamp:
May 27, 1998, 12:21:32 PM (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
448ba47
Parents:
a31f064
Message:

Fix from Jiri Gaisler <jgais@…> for a problem in which
external interrupt priorities were not being honored. Here is some
of his original report:

using rtems/erc32, I have a problem with interrupt priority when
interrupts occure simultaneously. Erc32 has an interrupt force
register where interrupts can be generated. If more than one
interrupt is generated, the interrupt handlers are scheduled in
the wrong order, i.e. with the lowest priority first.

I have attched a program that generates three interrupts, 0x11, 0x12
and 0x13. Interrupt 0x13 should be handled first, but is actually
handled last. Below is the output from sis:

sis> go
resuming at 0x02000000
RAM size: 4096 K, ROM size: 2048 K
Watchdog disabled
Waitstates = RAM read: 0, RAM write: 0, ROM read: 0, ROM write: 0
Power-down mode enabled
infinite UART baudrate
External interrupt received with vector 0x11
External interrupt received with vector 0x12
External interrupt received with vector 0x13

I have verified that sis generates the interrupts in the correct
order, i.e. 0x13 first, then 0x12 and then 0x11. So the problem
seems to be in the rtems interrupt handler. Do you use the PIL field
in the %psr register to mask lower priority interrupts or are all
external interrupts considered to have the same priority ..?

Here is a description of the fix:

it turned out that lower priority interrupts were not at all masked
off during interrupt handling. I made the following fix to cpu_asm.s:

... fix is in the code ...

There might be a simpler way of doing this, but this works...

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/sparc/cpu_asm.s

    ra31f064 r139e6efe  
    490490        sub      %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
    491491
    492         wr       %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
     492      /*
     493       *  Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
     494       *  set the PIL in the %psr to mask off interrupts with lower priority.
     495       *  The original %psr in %l0 is not modified since it will be restored
     496       *  when the interrupt handler returns.
     497       */
     498
     499      mov     %l0, %g5
     500      subcc   %l3, 0x11, %g0
     501      bl      dont_fix_pil
     502      subcc   %l3, 0x1f, %g0
     503      bg      dont_fix_pil
     504      sll     %l3, 8, %g4
     505      and     %g4, SPARC_PSR_PIL_MASK, %g4
     506      andn    %l0, SPARC_PSR_PIL_MASK, %g5
     507      or      %g4, %g5, %g5
     508dont_fix_pil:
     509        wr       %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
    493510
    494511        /*
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