Changeset 13512ec in rtems


Ignore:
Timestamp:
Jul 21, 2008, 8:38:06 PM (11 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.9, master
Children:
c607d50e
Parents:
f45169a
Message:

2008-07-21 Till Straumann <strauman@…>

  • new-exceptions/raw_exception,h, new-exceptions/raw_exception.c: Added more vectors for PPC405: watchdog, fpu-unavail, apu-unavail, itlbmiss, dtlbmiss, debug.
Location:
c/src/lib/libcpu/powerpc
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    rf45169a r13512ec  
     12008-07-21      Till Straumann <strauman@slac.stanford.edu>
     2
     3        * new-exceptions/raw_exception,h,
     4        new-exceptions/raw_exception.c: Added more vectors for PPC405:
     5        watchdog, fpu-unavail, apu-unavail, itlbmiss, dtlbmiss, debug.
     6       
    172008-07-18      Sebastian Huber <sebastian.huber@embedded-brains.de>
    28
  • c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.c

    rf45169a r13512ec  
    6161void* ppc_get_vector_addr(rtems_vector vector)
    6262{
    63   unsigned vaddr;
    64 
    65   vaddr = ((unsigned)vector) << 8;
    66 
    67   switch(vector) {
    68     /*
    69     * some vectors are located at odd addresses and only available
    70     * on some CPU derivates. this construct will handle them
    71     * if available
    72     */
    73   /* Special case; altivec unavailable doesn't fit :-( */
    74   case ASM_60X_VEC_VECTOR:
     63        unsigned vaddr;
     64
     65        vaddr = ((unsigned)vector) << 8;
     66
     67        switch(vector) {
     68                /*
     69                * some vectors are located at odd addresses and only available
     70                * on some CPU derivates. this construct will handle them
     71                * if available
     72                */
     73                /* Special case; altivec unavailable doesn't fit :-( */
     74                case ASM_60X_VEC_VECTOR:
    7575#ifndef ASM_60X_VEC_VECTOR_OFFSET
    7676#define ASM_60X_VEC_VECTOR_OFFSET 0xf20
    7777#endif
    78         if ( ppc_cpu_has_altivec() )
    79                 vaddr = ASM_60X_VEC_VECTOR_OFFSET;
    80     break;
    81 
    82   case ASM_BOOKE_FIT_VECTOR:
    83 #ifndef ASM_BOOKE_FIT_VECTOR_OFFSET
    84 #define ASM_BOOKE_FIT_VECTOR_OFFSET 0x1010
     78                        if ( ppc_cpu_has_altivec() )
     79                                vaddr = ASM_60X_VEC_VECTOR_OFFSET;
     80                        break;
     81
     82                default:
     83                        break;
     84        }
     85
     86        if ( PPC_405 == current_ppc_cpu ) {
     87                switch ( vector ) {
     88                        case ASM_BOOKE_FIT_VECTOR:
     89#ifndef ASM_PPC405_FIT_VECTOR_OFFSET
     90#define ASM_PPC405_FIT_VECTOR_OFFSET 0x1010
    8591#endif
    86         if ( PPC_405 == current_ppc_cpu )
    87         vaddr = ASM_BOOKE_FIT_VECTOR_OFFSET;
    88     break;
    89   case ASM_BOOKE_WDOG_VECTOR:
    90 #ifndef ASM_BOOKE_WDOG_VECTOR_OFFSET
    91 #define ASM_BOOKE_WDOG_VECTOR_OFFSET 0x1020
     92                                vaddr = ASM_PPC405_FIT_VECTOR_OFFSET;
     93                                break;
     94                        case ASM_BOOKE_WDOG_VECTOR:
     95#ifndef ASM_PPC405_WDOG_VECTOR_OFFSET
     96#define ASM_PPC405_WDOG_VECTOR_OFFSET 0x1020
    9297#endif
    93         if ( PPC_405 == current_ppc_cpu )
    94         vaddr = ASM_BOOKE_WDOG_VECTOR_OFFSET;
    95     break;
    96   default:
    97     break;
    98   }
    99   if (bsp_exceptions_in_RAM) {
    100     if (ppc_cpu_has_ivpr_and_ivor()) {
    101       return ((void*) ((vaddr >> 4) + ppc_exc_vector_base));
    102     } else {
    103       return ((void*) (vaddr + ppc_exc_vector_base));
    104     }
    105   }
    106 
    107   return ((void*)  (vaddr + 0xfff00000));
     98                                vaddr = ASM_PPC405_WDOG_VECTOR_OFFSET;
     99                                break;
     100                        case ASM_TRACE_VECTOR:
     101#ifndef ASM_PPC405_TRACE_VECTOR_OFFSET
     102#define ASM_PPC405_TRACE_VECTOR_OFFSET  0x2000
     103#endif
     104                                vaddr = ASM_PPC405_TRACE_VECTOR_OFFSET;
     105                                break;
     106                        case ASM_PPC405_APU_UNAVAIL_VECTOR:
     107                                vaddr = ASM_60X_VEC_VECTOR_OFFSET;
     108                        default:
     109                                break;
     110                }
     111        }
     112
     113        if (bsp_exceptions_in_RAM) {
     114                if (ppc_cpu_has_ivpr_and_ivor()) {
     115                        return ((void*) ((vaddr >> 4) + ppc_exc_vector_base));
     116                } else {
     117                        return ((void*) (vaddr + ppc_exc_vector_base));
     118                }
     119        }
     120
     121        return ((void*)  (vaddr + 0xfff00000));
    108122}
    109123
     
    162176
    163177static const cat_ini_t ppc_405_vector_categories[LAST_VALID_EXC + 1] = {
     178  [ ASM_BOOKE_CRIT_VECTOR      ] = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
     179  [ ASM_MACH_VECTOR            ] = PPC_EXC_405_CRITICAL,
     180  [ ASM_PROT_VECTOR            ] = PPC_EXC_CLASSIC,
     181  [ ASM_ISI_VECTOR             ] = PPC_EXC_CLASSIC,
    164182  [ ASM_EXT_VECTOR             ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
     183  [ ASM_ALIGN_VECTOR           ] = PPC_EXC_CLASSIC,
     184  [ ASM_PROG_VECTOR            ] = PPC_EXC_CLASSIC,
     185  [ ASM_FLOAT_VECTOR           ] = PPC_EXC_CLASSIC,
     186
     187  [ ASM_PPC405_APU_UNAVAIL_VECTOR] = PPC_EXC_CLASSIC,
     188
     189  [ ASM_SYS_VECTOR             ] = PPC_EXC_CLASSIC,
     190
     191
     192
    165193  [ ASM_BOOKE_DEC_VECTOR       ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,             /* PIT */
    166194  [ ASM_BOOKE_FIT_VECTOR       ] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,             /* FIT */
    167 
    168   [ ASM_PROT_VECTOR            ] = PPC_EXC_CLASSIC,
    169   [ ASM_ISI_VECTOR             ] = PPC_EXC_CLASSIC,
    170   [ ASM_ALIGN_VECTOR           ] = PPC_EXC_CLASSIC,
    171   [ ASM_PROG_VECTOR            ] = PPC_EXC_CLASSIC,
    172   [ ASM_SYS_VECTOR             ] = PPC_EXC_CLASSIC,
     195  [ ASM_BOOKE_WDOG_VECTOR      ] = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
     196  [ ASM_BOOKE_DTLBMISS_VECTOR  ] = PPC_EXC_CLASSIC,
    173197  [ ASM_BOOKE_ITLBMISS_VECTOR  ] = PPC_EXC_CLASSIC,
    174   [ ASM_BOOKE_DTLBMISS_VECTOR  ] = PPC_EXC_CLASSIC,
    175 
    176   [ ASM_BOOKE_CRIT_VECTOR      ] = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
    177   [ ASM_MACH_VECTOR            ] = PPC_EXC_405_CRITICAL,
     198  [ ASM_TRACE_VECTOR           ] = PPC_EXC_405_CRITICAL,
    178199};
    179200
  • c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.h

    rf45169a r13512ec  
    5959#define ASM_BOOKE_WDOG_VECTOR                0x14
    6060
     61#define ASM_PPC405_APU_UNAVAIL_VECTOR           ASM_60X_VEC_ASSIST_VECTOR
     62
    6163#define ASM_8XX_FLOATASSIST_VECTOR               0x0E
    6264#define ASM_8XX_SOFTEMUL_VECTOR              0x10
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