Changeset 133dcd92 in rtems


Ignore:
Timestamp:
10/05/99 14:02:57 (23 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
17978a1
Parents:
4075af6f
Message:

Patch from Eric Valette <valette@…> with two small
fixes related to GDB over TCP/IP debug.

Location:
c/src
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S

    r4075af6f r133dcd92  
    66 *  found in found in the file LICENSE in this distribution or at
    77 *  http://www.OARcorp.com/rtems/license.html.
     8 *
     9 *  Modified to support the MCP750.
     10 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
     11 *
    812 *
    913 * $Id$
    … …  
    220224         * store it at the right place
    221225         */
     226        stw     r2, GPR1_OFFSET(r1)
     227        /*
     228         * Call High Level signal handling code
     229         */
    222230        bl      _ISR_Signals_to_thread_executing
    223231        /*

  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S

    r4075af6f r133dcd92  
    66 *  found in found in the file LICENSE in this distribution or at
    77 *  http://www.OARcorp.com/rtems/license.html.
     8 *
     9 *  Modified to support the MCP750.
     10 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
     11 *
    812 *
    913 * $Id$
    … …  
    220224         * store it at the right place
    221225         */
     226        stw     r2, GPR1_OFFSET(r1)
     227        /*
     228         * Call High Level signal handling code
     229         */
    222230        bl      _ISR_Signals_to_thread_executing
    223231        /*

  • c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S

    r4075af6f r133dcd92  
    2626
    2727SYM (copyback_data_cache_and_invalidate_instr_cache):
     28        /* make sure the data changed is in the cache */
     29        sync
    2830        /* r3 address to handle, r4 length in bytes */
    2931        addi    r6, r0, PPC_CACHE_ALIGNMENT

  • c/src/librdbg/src/powerpc/rdbg_cpu_asm.S

    r4075af6f r133dcd92  
    2626
    2727SYM (copyback_data_cache_and_invalidate_instr_cache):
     28        /* make sure the data changed is in the cache */
     29        sync
    2830        /* r3 address to handle, r4 length in bytes */
    2931        addi    r6, r0, PPC_CACHE_ALIGNMENT
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