Changeset 133dcd92 in rtems
- Timestamp:
- 10/05/99 14:02:57 (23 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 17978a1
- Parents:
- 4075af6f
- Location:
- c/src
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S
r4075af6f r133dcd92 6 6 * found in found in the file LICENSE in this distribution or at 7 7 * http://www.OARcorp.com/rtems/license.html. 8 * 9 * Modified to support the MCP750. 10 * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr 11 * 8 12 * 9 13 * $Id$ … … 220 224 * store it at the right place 221 225 */ 226 stw r2, GPR1_OFFSET(r1) 227 /* 228 * Call High Level signal handling code 229 */ 222 230 bl _ISR_Signals_to_thread_executing 223 231 /* -
c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S
r4075af6f r133dcd92 6 6 * found in found in the file LICENSE in this distribution or at 7 7 * http://www.OARcorp.com/rtems/license.html. 8 * 9 * Modified to support the MCP750. 10 * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr 11 * 8 12 * 9 13 * $Id$ … … 220 224 * store it at the right place 221 225 */ 226 stw r2, GPR1_OFFSET(r1) 227 /* 228 * Call High Level signal handling code 229 */ 222 230 bl _ISR_Signals_to_thread_executing 223 231 /* -
c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S
r4075af6f r133dcd92 26 26 27 27 SYM (copyback_data_cache_and_invalidate_instr_cache): 28 /* make sure the data changed is in the cache */ 29 sync 28 30 /* r3 address to handle, r4 length in bytes */ 29 31 addi r6, r0, PPC_CACHE_ALIGNMENT -
c/src/librdbg/src/powerpc/rdbg_cpu_asm.S
r4075af6f r133dcd92 26 26 27 27 SYM (copyback_data_cache_and_invalidate_instr_cache): 28 /* make sure the data changed is in the cache */ 29 sync 28 30 /* r3 address to handle, r4 length in bytes */ 29 31 addi r6, r0, PPC_CACHE_ALIGNMENT
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