Index: cpukit/score/cpu/arm/arm_exc_interrupt.S
===================================================================
--- cpukit/score/cpu/arm/arm_exc_interrupt.S	(revision 84ba194477bdf4959ad71f8ea3760f643e15ce78)
+++ cpukit/score/cpu/arm/arm_exc_interrupt.S	(revision 12a2a8e4426c05161aa76a9c86de1e36e43e8a61)
@@ -38,4 +38,6 @@
 #define NON_VOLATILE_SCRATCH r9
 
+#ifndef ARM_MULTILIB_HAS_STORE_RETURN_STATE
+
 #define EXCHANGE_LR r4
 #define EXCHANGE_SPSR r5
@@ -49,8 +51,26 @@
 #define CONTEXT_SIZE 32
 
+#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
+
 .arm
 .globl _ARMV4_Exception_interrupt
 _ARMV4_Exception_interrupt:
 
+#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
+	/* Prepare return from interrupt */
+	sub	lr, lr, #4
+
+	/* Save LR_irq and SPSR_irq to the SVC stack */
+	srsfd	sp!, #ARM_PSR_M_SVC
+
+	/* Switch to SVC mode */
+	cps	#ARM_PSR_M_SVC
+
+	/*
+	 * Save the volatile registers, two non-volatile registers used for
+	 * interrupt processing, and the link register.
+	 */
+	push	{r0-r3, STACK_POINTER_ADJUST, NON_VOLATILE_SCRATCH, r12, lr}
+#else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
 	/* Save exchange registers to exchange area */
 	stmdb	sp, EXCHANGE_LIST
@@ -75,4 +95,5 @@
 	push	CONTEXT_LIST
 	push	{STACK_POINTER_ADJUST, lr}
+#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
 
 	/*
@@ -98,4 +119,5 @@
 #endif /* ARM_MULTILIB_VFP */
 
+#ifndef ARM_MULTILIB_HAS_STORE_RETURN_STATE
 	/* Remember INT stack pointer */
 	mov	r1, EXCHANGE_INT_SP
@@ -103,4 +125,5 @@
 	/* Restore exchange registers from exchange area */
 	ldmia	r1, EXCHANGE_LIST
+#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
 
 	/* Get interrupt nest level */
@@ -110,5 +133,9 @@
 	mov	NON_VOLATILE_SCRATCH, sp
 	cmp	r2, #0
+#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
+	ldreq	sp, [r0, #PER_CPU_INTERRUPT_STACK_HIGH]
+#else
 	moveq	sp, r1
+#endif
 
 	/* Increment interrupt nest and thread dispatch disable level */
@@ -216,4 +243,11 @@
 	add	sp, sp, STACK_POINTER_ADJUST
 
+#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
+	/*
+	 * Restore the volatile registers, two non-volatile registers used for
+	 * interrupt processing, and the link register.
+	 */
+	pop	{r0-r3, STACK_POINTER_ADJUST, NON_VOLATILE_SCRATCH, r12, lr}
+#else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
 	/* Restore STACK_POINTER_ADJUST register and link register */
 	pop	{STACK_POINTER_ADJUST, lr}
@@ -246,4 +280,5 @@
 	/* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */
 	pop	{EXCHANGE_LR, EXCHANGE_SPSR}
+#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
 
 #ifdef ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
@@ -275,5 +310,9 @@
 
 	/* Return from interrupt */
+#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
+	rfefd	sp!
+#else
 	subs	pc, lr, #4
+#endif
 
 #ifdef RTEMS_PROFILING
Index: cpukit/score/cpu/arm/include/rtems/score/arm.h
===================================================================
--- cpukit/score/cpu/arm/include/rtems/score/arm.h	(revision 84ba194477bdf4959ad71f8ea3760f643e15ce78)
+++ cpukit/score/cpu/arm/include/rtems/score/arm.h	(revision 12a2a8e4426c05161aa76a9c86de1e36e43e8a61)
@@ -48,4 +48,5 @@
   #define ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
   #define ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
+  #define ARM_MULTILIB_HAS_STORE_RETURN_STATE
 #endif
 
Index: cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
===================================================================
--- cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h	(revision 84ba194477bdf4959ad71f8ea3760f643e15ce78)
+++ cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h	(revision 12a2a8e4426c05161aa76a9c86de1e36e43e8a61)
@@ -80,4 +80,16 @@
   double d7;
 #endif /* ARM_MULTILIB_VFP */
+#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
+  uint32_t r0;
+  uint32_t r1;
+  uint32_t r2;
+  uint32_t r3;
+  uint32_t r7;
+  uint32_t r9;
+  uint32_t r12;
+  uint32_t lr;
+  uint32_t return_pc;
+  uint32_t return_cpsr;
+#else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
   uint32_t r9;
   uint32_t lr;
@@ -90,4 +102,5 @@
   uint32_t r7;
   uint32_t r12;
+#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
 } CPU_Interrupt_frame;
 
