Changeset 12a2a8e4 in rtems


Ignore:
Timestamp:
01/13/22 13:51:55 (4 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
fbd18c0
Parents:
84ba194
git-author:
Sebastian Huber <sebastian.huber@…> (01/13/22 13:51:55)
git-committer:
Sebastian Huber <sebastian.huber@…> (01/17/22 07:14:12)
Message:

arm: Optimize interrupt handling

Use the SRS (Store Return State) instruction if available. This
considerably simplifies the context save and restore.

Location:
cpukit/score/cpu/arm
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/arm_exc_interrupt.S

    r84ba194 r12a2a8e4  
    3838#define NON_VOLATILE_SCRATCH r9
    3939
     40#ifndef ARM_MULTILIB_HAS_STORE_RETURN_STATE
     41
    4042#define EXCHANGE_LR r4
    4143#define EXCHANGE_SPSR r5
     
    4951#define CONTEXT_SIZE 32
    5052
     53#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
     54
    5155.arm
    5256.globl _ARMV4_Exception_interrupt
    5357_ARMV4_Exception_interrupt:
    5458
     59#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
     60        /* Prepare return from interrupt */
     61        sub     lr, lr, #4
     62
     63        /* Save LR_irq and SPSR_irq to the SVC stack */
     64        srsfd   sp!, #ARM_PSR_M_SVC
     65
     66        /* Switch to SVC mode */
     67        cps     #ARM_PSR_M_SVC
     68
     69        /*
     70         * Save the volatile registers, two non-volatile registers used for
     71         * interrupt processing, and the link register.
     72         */
     73        push    {r0-r3, STACK_POINTER_ADJUST, NON_VOLATILE_SCRATCH, r12, lr}
     74#else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
    5575        /* Save exchange registers to exchange area */
    5676        stmdb   sp, EXCHANGE_LIST
     
    7595        push    CONTEXT_LIST
    7696        push    {STACK_POINTER_ADJUST, lr}
     97#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
    7798
    7899        /*
     
    98119#endif /* ARM_MULTILIB_VFP */
    99120
     121#ifndef ARM_MULTILIB_HAS_STORE_RETURN_STATE
    100122        /* Remember INT stack pointer */
    101123        mov     r1, EXCHANGE_INT_SP
     
    103125        /* Restore exchange registers from exchange area */
    104126        ldmia   r1, EXCHANGE_LIST
     127#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
    105128
    106129        /* Get interrupt nest level */
     
    110133        mov     NON_VOLATILE_SCRATCH, sp
    111134        cmp     r2, #0
     135#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
     136        ldreq   sp, [r0, #PER_CPU_INTERRUPT_STACK_HIGH]
     137#else
    112138        moveq   sp, r1
     139#endif
    113140
    114141        /* Increment interrupt nest and thread dispatch disable level */
     
    216243        add     sp, sp, STACK_POINTER_ADJUST
    217244
     245#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
     246        /*
     247         * Restore the volatile registers, two non-volatile registers used for
     248         * interrupt processing, and the link register.
     249         */
     250        pop     {r0-r3, STACK_POINTER_ADJUST, NON_VOLATILE_SCRATCH, r12, lr}
     251#else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
    218252        /* Restore STACK_POINTER_ADJUST register and link register */
    219253        pop     {STACK_POINTER_ADJUST, lr}
     
    246280        /* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */
    247281        pop     {EXCHANGE_LR, EXCHANGE_SPSR}
     282#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
    248283
    249284#ifdef ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
     
    275310
    276311        /* Return from interrupt */
     312#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
     313        rfefd   sp!
     314#else
    277315        subs    pc, lr, #4
     316#endif
    278317
    279318#ifdef RTEMS_PROFILING
  • cpukit/score/cpu/arm/include/rtems/score/arm.h

    r84ba194 r12a2a8e4  
    4848  #define ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
    4949  #define ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
     50  #define ARM_MULTILIB_HAS_STORE_RETURN_STATE
    5051#endif
    5152
  • cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h

    r84ba194 r12a2a8e4  
    8080  double d7;
    8181#endif /* ARM_MULTILIB_VFP */
     82#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE
     83  uint32_t r0;
     84  uint32_t r1;
     85  uint32_t r2;
     86  uint32_t r3;
     87  uint32_t r7;
     88  uint32_t r9;
     89  uint32_t r12;
     90  uint32_t lr;
     91  uint32_t return_pc;
     92  uint32_t return_cpsr;
     93#else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
    8294  uint32_t r9;
    8395  uint32_t lr;
     
    90102  uint32_t r7;
    91103  uint32_t r12;
     104#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */
    92105} CPU_Interrupt_frame;
    93106
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