Changeset 12a2a8e4 in rtems
- Timestamp:
- 01/13/22 13:51:55 (2 years ago)
- Branches:
- master
- Children:
- fbd18c0
- Parents:
- 84ba194
- git-author:
- Sebastian Huber <sebastian.huber@…> (01/13/22 13:51:55)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (01/17/22 07:14:12)
- Location:
- cpukit/score/cpu/arm
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/arm/arm_exc_interrupt.S
r84ba194 r12a2a8e4 38 38 #define NON_VOLATILE_SCRATCH r9 39 39 40 #ifndef ARM_MULTILIB_HAS_STORE_RETURN_STATE 41 40 42 #define EXCHANGE_LR r4 41 43 #define EXCHANGE_SPSR r5 … … 49 51 #define CONTEXT_SIZE 32 50 52 53 #endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ 54 51 55 .arm 52 56 .globl _ARMV4_Exception_interrupt 53 57 _ARMV4_Exception_interrupt: 54 58 59 #ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE 60 /* Prepare return from interrupt */ 61 sub lr, lr, #4 62 63 /* Save LR_irq and SPSR_irq to the SVC stack */ 64 srsfd sp!, #ARM_PSR_M_SVC 65 66 /* Switch to SVC mode */ 67 cps #ARM_PSR_M_SVC 68 69 /* 70 * Save the volatile registers, two non-volatile registers used for 71 * interrupt processing, and the link register. 72 */ 73 push {r0-r3, STACK_POINTER_ADJUST, NON_VOLATILE_SCRATCH, r12, lr} 74 #else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ 55 75 /* Save exchange registers to exchange area */ 56 76 stmdb sp, EXCHANGE_LIST … … 75 95 push CONTEXT_LIST 76 96 push {STACK_POINTER_ADJUST, lr} 97 #endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ 77 98 78 99 /* … … 98 119 #endif /* ARM_MULTILIB_VFP */ 99 120 121 #ifndef ARM_MULTILIB_HAS_STORE_RETURN_STATE 100 122 /* Remember INT stack pointer */ 101 123 mov r1, EXCHANGE_INT_SP … … 103 125 /* Restore exchange registers from exchange area */ 104 126 ldmia r1, EXCHANGE_LIST 127 #endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ 105 128 106 129 /* Get interrupt nest level */ … … 110 133 mov NON_VOLATILE_SCRATCH, sp 111 134 cmp r2, #0 135 #ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE 136 ldreq sp, [r0, #PER_CPU_INTERRUPT_STACK_HIGH] 137 #else 112 138 moveq sp, r1 139 #endif 113 140 114 141 /* Increment interrupt nest and thread dispatch disable level */ … … 216 243 add sp, sp, STACK_POINTER_ADJUST 217 244 245 #ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE 246 /* 247 * Restore the volatile registers, two non-volatile registers used for 248 * interrupt processing, and the link register. 249 */ 250 pop {r0-r3, STACK_POINTER_ADJUST, NON_VOLATILE_SCRATCH, r12, lr} 251 #else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ 218 252 /* Restore STACK_POINTER_ADJUST register and link register */ 219 253 pop {STACK_POINTER_ADJUST, lr} … … 246 280 /* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */ 247 281 pop {EXCHANGE_LR, EXCHANGE_SPSR} 282 #endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ 248 283 249 284 #ifdef ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE … … 275 310 276 311 /* Return from interrupt */ 312 #ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE 313 rfefd sp! 314 #else 277 315 subs pc, lr, #4 316 #endif 278 317 279 318 #ifdef RTEMS_PROFILING -
cpukit/score/cpu/arm/include/rtems/score/arm.h
r84ba194 r12a2a8e4 48 48 #define ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE 49 49 #define ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS 50 #define ARM_MULTILIB_HAS_STORE_RETURN_STATE 50 51 #endif 51 52 -
cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
r84ba194 r12a2a8e4 80 80 double d7; 81 81 #endif /* ARM_MULTILIB_VFP */ 82 #ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE 83 uint32_t r0; 84 uint32_t r1; 85 uint32_t r2; 86 uint32_t r3; 87 uint32_t r7; 88 uint32_t r9; 89 uint32_t r12; 90 uint32_t lr; 91 uint32_t return_pc; 92 uint32_t return_cpsr; 93 #else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ 82 94 uint32_t r9; 83 95 uint32_t lr; … … 90 102 uint32_t r7; 91 103 uint32_t r12; 104 #endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ 92 105 } CPU_Interrupt_frame; 93 106
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