Changeset 127634c in rtems


Ignore:
Timestamp:
Apr 17, 2014, 9:22:53 AM (6 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
d98eea0
Parents:
62fa1ea
git-author:
Ralf Kirchner <ralf.kirchner@…> (04/17/14 09:22:53)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/17/14 11:25:12)
Message:

bsp/arm: Correct L2 cache enable method

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r62fa1ea r127634c  
    12751275cache_l2c_310_enable( void )
    12761276{
    1277   volatile L2CC *l2cc     = (volatile L2CC *) BSP_ARM_L2CC_BASE;
    1278   uint32_t       cache_id = l2cc->cache_id & CACHE_L2C_310_L2CC_ID_PART_MASK;
    1279   int            ways     = 0;
    1280 
    1281 
    1282   /* Do we actually have an L2C-310 cache controller?
    1283    * Has BSP_ARM_L2CC_BASE been configured correctly? */
    1284   switch ( cache_id ) {
    1285     case CACHE_L2C_310_L2CC_ID_PART_L310:
    1286     {
    1287       const cache_l2c_310_rtl_release RTL_RELEASE =
    1288         l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    1289       /* If this assertion fails, you have a release of the
    1290        * L2C-310 cache for which the l2c_310_cache_errata_is_applicable_ ...
    1291        * methods are not yet implemented. This means you will get incorrect
    1292        * errata handling */
    1293       assert(    RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    1294               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    1295               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    1296               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    1297               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    1298               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    1299               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    1300       if ( l2cc->aux_ctrl & ( 1 << 16 ) ) {
    1301         ways = 16;
    1302       } else {
    1303         ways = 8;
     1277  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1278 
     1279  /* Only enable if L2CC is currently disabled */
     1280  if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {
     1281    uint32_t                     cache_id =
     1282      l2cc->cache_id & CACHE_L2C_310_L2CC_ID_PART_MASK;
     1283    int                          ways     = 0;
     1284
     1285    /* Do we actually have an L2C-310 cache controller?
     1286    * Has BSP_ARM_L2CC_BASE been configured correctly? */
     1287    switch ( cache_id ) {
     1288      case CACHE_L2C_310_L2CC_ID_PART_L310:
     1289      {
     1290        const cache_l2c_310_rtl_release RTL_RELEASE =
     1291          l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     1292        /* If this assertion fails, you have a release of the
     1293        * L2C-310 cache for which the l2c_310_cache_errata_is_applicable_ ...
     1294        * methods are not yet implemented. This means you will get incorrect
     1295        * errata handling */
     1296        assert(    RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
     1297                || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
     1298                || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
     1299                || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
     1300                || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
     1301                || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
     1302                || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
     1303        if ( l2cc->aux_ctrl & ( 1 << 16 ) ) {
     1304          ways = 16;
     1305        } else {
     1306          ways = 8;
     1307        }
     1308
     1309        assert( ways == CACHE_l2C_310_NUM_WAYS );
    13041310      }
    1305 
    1306       assert( ways == CACHE_l2C_310_NUM_WAYS );
     1311      break;
     1312      case CACHE_L2C_310_L2CC_ID_PART_L210:
     1313
     1314        /* Invalid case */
     1315
     1316        /* Support for this type is not implemented in this driver.
     1317        * Either support needs to get added or a seperate driver needs to get
     1318        * implemented */
     1319        assert( cache_id != CACHE_L2C_310_L2CC_ID_PART_L210 );
     1320        break;
     1321      default:
     1322
     1323        /* Unknown case */
     1324        assert( cache_id == CACHE_L2C_310_L2CC_ID_PART_L310 );
     1325        break;
    13071326    }
    1308     break;
    1309     case CACHE_L2C_310_L2CC_ID_PART_L210:
    1310 
    1311       /* Invalid case */
    1312 
    1313       /* Support for this type is not implemented in this driver.
    1314        * Either support needs to get added or a seperate driver needs to get
    1315        * implemented */
    1316       assert( cache_id != CACHE_L2C_310_L2CC_ID_PART_L210 );
    1317       break;
    1318     default:
    1319 
    1320       /* Unknown case */
    1321       assert( cache_id == CACHE_L2C_310_L2CC_ID_PART_L310 );
    1322       break;
    1323   }
    1324 
    1325   if ( ways > 0 ) {
    1326     /* Only enable if L2CC is currently disabled */   
    1327     if ( ways != 0
    1328          && ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {
    1329       rtems_interrupt_level level;
     1327
     1328    if ( ways > 0 ) {
    13301329      uint32_t              aux;
    1331 
    1332       rtems_interrupt_disable( level );
    13331330
    13341331      /* Set up the way size */
     
    13411338
    13421339      /* Level 2 configuration and control registers must not get written while
    1343        * background operations are pending */
     1340      * background operations are pending */
    13441341      while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
    13451342
     
    13631360      /* Enable the L2CC */
    13641361      l2cc->ctrl |= CACHE_L2C_310_L2CC_ENABLE_MASK;
    1365 
    1366       rtems_interrupt_enable( level );
    13671362    }
    13681363  }
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