Changeset 12718134 in rtems


Ignore:
Timestamp:
Apr 24, 2017, 1:10:41 PM (3 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
master
Children:
e6fbd26
Parents:
a9859d1
git-author:
Daniel Hellstrom <daniel@…> (04/24/17 13:10:41)
git-committer:
Daniel Hellstrom <daniel@…> (05/14/17 10:31:56)
Message:

leon, greth: EDCL and DD is disabled during reset

The EDCL and Duplex-Detection are now disabled during soft-reset
of the GRETH core.

The speed settings are preserved on boot and greth_stop() also,
this is required to keep EDCL operational when DD is set.

Location:
c/src/lib/libbsp/sparc/shared
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/include/greth.h

    ra9859d1 r12718134  
    8383#define GRETH_CTRL_RST          0x00000040 /* Reset MAC */
    8484#define GRETH_CTRL_DD           0x00001000 /* Disable EDCL Duplex Detection */
     85#define GRETH_CTRL_ED           0x00004000 /* EDCL Disable */
    8586
    8687/* Status Register */
  • c/src/lib/libbsp/sparc/shared/net/greth.c

    ra9859d1 r12718134  
    155155   int minor;
    156156   int phyaddr;  /* PHY Address configured by user (or -1 to autodetect) */
     157   unsigned int edcl_dis;
    157158
    158159   int acceptBroadcast;
     
    351352    int tmp2;
    352353    struct timespec tstart, tnow;
    353 
    354354    greth_regs *regs;
    355355
    356356    regs = sc->regs;
    357    
     357
    358358    /* Reset the controller.  */
    359359    sc->rxInterrupts = 0;
    360360    sc->rxPackets = 0;
    361361
    362     regs->ctrl = GRETH_CTRL_RST;        /* Reset ON */
     362    regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset ON */
    363363    for (i = 0; i<100 && (regs->ctrl & GRETH_CTRL_RST); i++)
    364364        ;
    365     regs->ctrl = GRETH_CTRL_DD;         /* Reset OFF. SW do PHY Init */
     365    regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset OFF. SW do PHY Init */
    366366
    367367    /* Check if mac is gbit capable*/
     
    505505    while ((read_mii(sc, phyaddr, 0)) & 0x8000) {}
    506506
    507     regs->ctrl = GRETH_CTRL_RST;        /* Reset ON */
     507    regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset ON */
    508508    for (i = 0; i < 100 && (regs->ctrl & GRETH_CTRL_RST); i++)
    509509        ;
    510     regs->ctrl = GRETH_CTRL_DD;
     510    regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis; /* Reset OFF. SW do PHY Init */
    511511
    512512    /* Initialize rx/tx descriptor table pointers. Due to alignment we
     
    585585    }
    586586    sc->next_tx_mbuf = NULL;
    587    
     587
    588588    if ( !sc->gbit_mac )
    589589        sc->max_fragsize = 1;
     
    11611161    ifp->if_flags &= ~IFF_RUNNING;
    11621162
    1163     sc->regs->ctrl = 0;                 /* RX/TX OFF */
    1164     sc->regs->ctrl = GRETH_CTRL_RST;    /* Reset ON */
    1165     sc->regs->ctrl = 0;                 /* Reset OFF */
     1163    /* RX/TX OFF */
     1164    sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED;
     1165    /* Reset ON */
     1166    sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED;
     1167    /* Reset OFF and restore link settings previously detected if any */
     1168    sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis |
     1169                     (sc->gb << 8) | (sc->sp << 7) | (sc->fd << 4);
    11661170    SPIN_UNLOCK_IRQ(&sc->devlock, flags);
    11671171
     
    14251429    struct ambapp_core *pnpinfo;
    14261430    union drvmgr_key_value *value;
     1431    unsigned int speed;
    14271432
    14281433    /* Get device information from AMBA PnP information */
     
    14351440    sc->minor = sc->dev->minor_drv;
    14361441
    1437     /* clear control register and reset NIC
     1442    /* Remember EDCL enabled/disable state before reset */
     1443    sc->edcl_dis = sc->regs->ctrl & GRETH_CTRL_ED;
     1444
     1445    /* Default is to inherit EDCL Disable bit from HW. User can force En/Dis */
     1446    value = drvmgr_dev_key_get(sc->dev, "edclDis", DRVMGR_KT_INT);
     1447    if ( value ) {
     1448        /* Force EDCL mode. Has an effect later when GRETH+PHY is initialized */
     1449        if (value->i > 0)
     1450            sc->edcl_dis = GRETH_CTRL_ED;
     1451        else
     1452            sc->edcl_dis = 0;
     1453    }
     1454
     1455    /* clear control register and reset NIC and keep current speed modes.
    14381456     * This should be done as quick as possible during startup, this is to
    14391457     * stop DMA transfers after a reboot.
    14401458     */
    1441     sc->regs->ctrl = 0;
    1442     sc->regs->ctrl = GRETH_CTRL_RST;
    1443     sc->regs->ctrl = 0;
     1459    speed = sc->regs->ctrl & (GRETH_CTRL_GB | GRETH_CTRL_SP | GRETH_CTRL_FULLD);
     1460    sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED;
     1461    sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED;
     1462    sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis | speed;
    14441463
    14451464    /* Configure driver by overriding default config with the bus resources
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