Changeset 12718134 in rtems

Timestamp:

Apr 24, 2017, 1:10:41 PM (3 years ago)

Author:

Daniel Hellstrom <daniel@…>

Branches:

master

Children:

e6fbd26

Parents:

a9859d1

git-author:

Daniel Hellstrom <daniel@…> (04/24/17 13:10:41)

git-committer:

Daniel Hellstrom <daniel@…> (05/14/17 10:31:56)

Message:

leon, greth: EDCL and DD is disabled during reset

The EDCL and Duplex-Detection are now disabled during soft-reset
of the GRETH core.

The speed settings are preserved on boot and greth_stop() also,
this is required to keep EDCL operational when DD is set.

Location:

c/src/lib/libbsp/sparc/shared

Files:

• include/greth.h (modified) (1 diff)
• net/greth.c (modified) (7 diffs)

c/src/lib/libbsp/sparc/shared/include/greth.h

@@ -83 +83 @@
 #define GRETH_CTRL_RST          0x00000040 /* Reset MAC */
 #define GRETH_CTRL_DD           0x00001000 /* Disable EDCL Duplex Detection */
+#define GRETH_CTRL_ED           0x00004000 /* EDCL Disable */
 
 /* Status Register */

c/src/lib/libbsp/sparc/shared/net/greth.c

@@ -155 +155 @@
    int minor;
    int phyaddr;  /* PHY Address configured by user (or -1 to autodetect) */
+   unsigned int edcl_dis;
 
    int acceptBroadcast;
@@ -351 +352 @@
     int tmp2;
     struct timespec tstart, tnow;
-
     greth_regs *regs;
 
     regs = sc->regs;
-    
+
     /* Reset the controller.  */
     sc->rxInterrupts = 0;
     sc->rxPackets = 0;
 
-    regs->ctrl = GRETH_CTRL_RST;        /* Reset ON */
+    regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset ON */
     for (i = 0; i<100 && (regs->ctrl & GRETH_CTRL_RST); i++)
         ;
-    regs->ctrl = GRETH_CTRL_DD;         /* Reset OFF. SW do PHY Init */
+    regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset OFF. SW do PHY Init */
 
     /* Check if mac is gbit capable*/
@@ -505 +505 @@
     while ((read_mii(sc, phyaddr, 0)) & 0x8000) {}
 
-    regs->ctrl = GRETH_CTRL_RST;        /* Reset ON */
+    regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED; /* Reset ON */
     for (i = 0; i < 100 && (regs->ctrl & GRETH_CTRL_RST); i++)
         ;
-    regs->ctrl = GRETH_CTRL_DD;
+    regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis; /* Reset OFF. SW do PHY Init */
 
     /* Initialize rx/tx descriptor table pointers. Due to alignment we 
@@ -585 +585 @@
     }
     sc->next_tx_mbuf = NULL;
-    
+
     if ( !sc->gbit_mac )
         sc->max_fragsize = 1;
@@ -1161 +1161 @@
     ifp->if_flags &= ~IFF_RUNNING;
 
-    sc->regs->ctrl = 0;                 /* RX/TX OFF */
-    sc->regs->ctrl = GRETH_CTRL_RST;    /* Reset ON */
-    sc->regs->ctrl = 0;                 /* Reset OFF */
+    /* RX/TX OFF */
+    sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED;
+    /* Reset ON */
+    sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED;
+    /* Reset OFF and restore link settings previously detected if any */
+    sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis |
+                     (sc->gb << 8) | (sc->sp << 7) | (sc->fd << 4);
     SPIN_UNLOCK_IRQ(&sc->devlock, flags);
 
@@ -1425 +1429 @@
     struct ambapp_core *pnpinfo;
     union drvmgr_key_value *value;
+    unsigned int speed;
 
     /* Get device information from AMBA PnP information */
@@ -1435 +1440 @@
     sc->minor = sc->dev->minor_drv;
 
-    /* clear control register and reset NIC 
+    /* Remember EDCL enabled/disable state before reset */
+    sc->edcl_dis = sc->regs->ctrl & GRETH_CTRL_ED;
+
+    /* Default is to inherit EDCL Disable bit from HW. User can force En/Dis */
+    value = drvmgr_dev_key_get(sc->dev, "edclDis", DRVMGR_KT_INT);
+    if ( value ) {
+        /* Force EDCL mode. Has an effect later when GRETH+PHY is initialized */
+        if (value->i > 0)
+            sc->edcl_dis = GRETH_CTRL_ED;
+        else
+            sc->edcl_dis = 0;
+    }
+
+    /* clear control register and reset NIC and keep current speed modes.
      * This should be done as quick as possible during startup, this is to
      * stop DMA transfers after a reboot.
      */
-    sc->regs->ctrl = 0;
-    sc->regs->ctrl = GRETH_CTRL_RST;
-    sc->regs->ctrl = 0;
+    speed = sc->regs->ctrl & (GRETH_CTRL_GB | GRETH_CTRL_SP | GRETH_CTRL_FULLD);
+    sc->regs->ctrl = GRETH_CTRL_DD | GRETH_CTRL_ED;
+    sc->regs->ctrl = GRETH_CTRL_RST | GRETH_CTRL_DD | GRETH_CTRL_ED;
+    sc->regs->ctrl = GRETH_CTRL_DD | sc->edcl_dis | speed;
 
     /* Configure driver by overriding default config with the bus resources