Ignore:
Timestamp:
Oct 27, 2017, 4:18:40 AM (19 months ago)
Author:
Hesham Almatary <heshamelmatary@…>
Branches:
master
Children:
8fa827c
Parents:
2126438a
git-author:
Hesham Almatary <heshamelmatary@…> (10/27/17 04:18:40)
git-committer:
Hesham Almatary <heshamelmatary@…> (10/31/17 23:10:27)
Message:

cpukit: RISC-V - make riscv32 code work for riscv64 - v2

  • Use #ifdefs for 32/64 bit code
  • Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
  • Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
  • Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109

File:
1 moved

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/rtems/score/cpu.h

    r2126438a r11ff3a9  
    6767#define CPU_BIG_ENDIAN                           FALSE
    6868#define CPU_LITTLE_ENDIAN                        TRUE
    69 #define CPU_MODES_INTERRUPT_MASK   0x00000001
     69#define CPU_MODES_INTERRUPT_MASK   0x0000000000000001
    7070
    7171/*
     
    7676
    7777typedef struct {
    78   /* riscv32 has 32 32-bit general purpose registers (x0-x31). */
    79   uint32_t x[32];
     78  /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/
     79  unsigned long x[32];
    8080
    8181  /* Special purpose registers */
    82   uint32_t mstatus;
    83   uint32_t mcause;
    84   uint32_t mepc;
     82  unsigned long mstatus;
     83  unsigned long mcause;
     84  unsigned long mepc;
    8585#ifdef RTEMS_SMP
    8686  /**
     
    139139
    140140#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
     141#if __riscv_xlen == 32
    141142#define CPU_STACK_MINIMUM_SIZE  4096
     143#else
     144#define CPU_STACK_MINIMUM_SIZE  4096 * 2
     145#endif
    142146#define CPU_ALIGNMENT 8
    143147#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
     
    153157 */
    154158
    155 static inline uint32_t riscv_interrupt_disable( void )
    156 {
    157   register uint32_t status = read_csr(mstatus);
     159static inline unsigned long riscv_interrupt_disable( void )
     160{
     161  register unsigned long status = read_csr(mstatus);
    158162  clear_csr(mstatus, MSTATUS_MIE);
    159163  return status;
    160164}
    161165
    162 static inline void riscv_interrupt_enable(uint32_t level)
     166static inline void riscv_interrupt_enable(unsigned long level)
    163167{
    164168  write_csr(mstatus, level);
     
    177181    } while(0)
    178182
    179 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
     183RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level )
    180184{
    181185  return ( level & MSTATUS_MIE ) != 0;
    182186}
    183187
    184 void _CPU_ISR_Set_level( uint32_t level );
    185 
    186 uint32_t _CPU_ISR_Get_level( void );
     188void _CPU_ISR_Set_level( unsigned long level );
     189
     190unsigned long _CPU_ISR_Get_level( void );
    187191
    188192/* end of ISR handler macros */
     
    195199  void *stack_area_begin,
    196200  size_t stack_area_size,
    197   uint32_t new_level,
     201  unsigned long new_level,
    198202  void (*entry_point)( void ),
    199203  bool is_fp,
     
    263267#endif /* ASM */
    264268
     269#if __riscv_xlen == 32
    265270#define CPU_SIZEOF_POINTER 4
     271
     272/* 32-bit load/store instructions */
     273#define LREG lw
     274#define SREG sw
     275
    266276#define CPU_EXCEPTION_FRAME_SIZE 128
     277#else /* xlen = 64 */
     278#define CPU_SIZEOF_POINTER 8
     279
     280/* 64-bit load/store instructions */
     281#define LREG ld
     282#define SREG sd
     283
     284#define CPU_EXCEPTION_FRAME_SIZE 256
     285#endif
     286
    267287#define CPU_PER_CPU_CONTROL_SIZE 0
    268288
     
    271291
    272292typedef struct {
    273   uint32_t x[32];;
     293  unsigned long x[32];;
    274294} CPU_Exception_frame;
    275295
     
    322342
    323343void _CPU_ISR_install_vector(
    324   uint32_t    vector,
     344  unsigned long    vector,
    325345  proc_ptr   new_handler,
    326346  proc_ptr   *old_handler
     
    424444 */
    425445
    426 static inline unsigned int CPU_swap_u32(
    427   unsigned int value
     446static inline uint32_t CPU_swap_u32(
     447  uint32_t value
    428448)
    429449{
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