Changeset 11ff3a9 in rtems


Ignore:
Timestamp:
Oct 27, 2017, 4:18:40 AM (18 months ago)
Author:
Hesham Almatary <heshamelmatary@…>
Branches:
master
Children:
8fa827c
Parents:
2126438a
git-author:
Hesham Almatary <heshamelmatary@…> (10/27/17 04:18:40)
git-committer:
Hesham Almatary <heshamelmatary@…> (10/31/17 23:10:27)
Message:

cpukit: RISC-V - make riscv32 code work for riscv64 - v2

  • Use #ifdefs for 32/64 bit code
  • Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
  • Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
  • Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv

Update #3109

Files:
5 edited
18 moved

Legend:

Unmodified
Added
Removed
  • aclocal/canonical-target-name.m4

    r2126438a r11ff3a9  
    1313        RTEMS_CPU=no_cpu
    1414        ;;
    15   *)
     15  riscv*-*rtems*)
     16        RTEMS_CPU=riscv
     17        ;;
     18  *)
    1619        RTEMS_CPU=`echo $target | sed 's%^\([[^-]]*\)-\(.*\)$%\1%'`
    1720        ;;
  • c/src/aclocal/rtems-cpu-subdirs.m4

    r2126438a r11ff3a9  
    2424_RTEMS_CPU_SUBDIR([or1k],[$1]);;
    2525_RTEMS_CPU_SUBDIR([powerpc],[$1]);;
    26 _RTEMS_CPU_SUBDIR([riscv32],[$1]);;
     26_RTEMS_CPU_SUBDIR([riscv],[$1]);;
    2727_RTEMS_CPU_SUBDIR([sh],[$1]);;
    2828_RTEMS_CPU_SUBDIR([sparc],[$1]);;
  • cpukit/aclocal/canonical-target-name.m4

    r2126438a r11ff3a9  
    99AC_MSG_CHECKING(rtems target cpu)
    1010case "${host}" in
     11riscv*-*-rtems*)
     12        RTEMS_CPU=riscv;;
    1113*-*-rtems*)
    1214        RTEMS_CPU="$host_cpu";;
  • cpukit/configure.ac

    r2126438a r11ff3a9  
    460460score/cpu/or1k/Makefile
    461461score/cpu/powerpc/Makefile
    462 score/cpu/riscv32/Makefile
     462score/cpu/riscv/Makefile
    463463score/cpu/sh/Makefile
    464464score/cpu/sparc/Makefile
  • cpukit/score/cpu/Makefile.am

    r2126438a r11ff3a9  
    1515DIST_SUBDIRS += or1k
    1616DIST_SUBDIRS += powerpc
    17 DIST_SUBDIRS += riscv32
     17DIST_SUBDIRS += riscv
    1818DIST_SUBDIRS += sh
    1919DIST_SUBDIRS += sparc
  • cpukit/score/cpu/riscv/cpu.c

    r2126438a r11ff3a9  
    11/*
    2  * riscv32 CPU Dependent Source
     2 * RISC-V CPU Dependent Source
    33 *
    44 * Copyright (c) 2015 University of York.
     
    6060}
    6161
    62 void _CPU_ISR_Set_level(uint32_t level)
     62void _CPU_ISR_Set_level(unsigned long level)
    6363{
    6464  /* Do nothing */
    6565}
    6666
    67 uint32_t  _CPU_ISR_Get_level( void )
     67unsigned long  _CPU_ISR_Get_level( void )
    6868{
    6969  /* Do nothing */
     
    8181
    8282void _CPU_ISR_install_vector(
    83   uint32_t    vector,
     83  unsigned long    vector,
    8484  proc_ptr    new_handler,
    8585  proc_ptr   *old_handler
  • cpukit/score/cpu/riscv/riscv-context-initialize.c

    r2126438a r11ff3a9  
    4343  void *stack_area_begin,
    4444  size_t stack_area_size,
    45   uint32_t new_level,
     45  unsigned long new_level,
    4646  void (*entry_point)( void ),
    4747  bool is_fp,
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    r2126438a r11ff3a9  
    3636.section .text, "ax"
    3737.align 4
    38 
    39 # define LREG lw
    40 # define SREG sw
    4138
    4239PUBLIC(_CPU_Context_switch)
  • cpukit/score/cpu/riscv/riscv-context-validate.S

    r2126438a r11ff3a9  
    3333.section        .text
    3434
    35 #define SREG sw
    36 #define LREG lw
    3735
    3836PUBLIC(_CPU_Context_validate)
    3937SYM(_CPU_Context_validate):
    40   addi sp, sp, -144
     38  /* RISC-V/RTEMS context has 36 registers of CPU_SIZEOF_POINTER size */
     39  addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
    4140
    4241  SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
     
    198197  LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
    199198
    200   addi sp, sp, 144
     199  addi sp, sp, 36 * CPU_SIZEOF_POINTER
    201200  ret
  • cpukit/score/cpu/riscv/riscv-exception-frame-print.c

    r2126438a r11ff3a9  
    3737
    3838  for ( i = 0; i < 32; ++i ) {
    39     printk( "x%02i = 0x%016" PRIx32 "\n", i, frame->x[i]);
     39#if __riscv_xlen == 32
     40    printk( "x%02i = 0x%032" PRIx32 "\n", i, frame->x[i]);
     41#else /* xlen == 64 */
     42    printk( "x%02i = 0x%032" PRIx64 "\n", i, frame->x[i]);
     43#endif
    4044  }
    4145}
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    r2126438a r11ff3a9  
    44 * @ingroup ScoreCPU
    55 *
    6  * @brief riscv32 exception support implementation.
     6 * @brief RISC-V exception support implementation.
    77 */
    88
     
    4242#include <rtems/score/percpu.h>
    4343
    44 # define LREG lw
    45 # define SREG sw
    46 
    4744EXTERN(bsp_start_vector_table_begin)
    4845EXTERN(_Thread_Dispatch)
     
    5350TYPE_FUNC(ISR_Handler)
    5451SYM(ISR_Handler):
    55   addi sp, sp, -144
     52  addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
    5653
    5754  SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
     
    104101  la t1, THREAD_DISPATCH_DISABLE_LEVEL
    105102
    106   LREG t2, (t0)
    107   LREG t3, (t1)
     103  lw t2, (t0)
     104  lw t3, (t1)
    108105  addi t2, t2, 1
    109106  addi t3, t3, 1
    110   SREG t2, (t0)
    111   SREG t3, (t1)
     107  sw t2, (t0)
     108  sw t3, (t1)
    112109
    113110  /* Save interrupted task stack pointer */
    114   addi t4, sp, 144
     111  addi t4, sp, 36 * CPU_SIZEOF_POINTER
    115112  SREG t4, (2 * CPU_SIZEOF_POINTER)(sp)
    116113
     
    127124  /* calculate the offset */
    128125  la   t5, bsp_start_vector_table_begin
     126#if __riscv_xlen == 32
    129127  slli t6, a0, 2
     128#else /* xlen = 64 */
     129  slli t6, a0, 3
     130#endif
    130131  add  t5, t5, t6
    131132  LREG t5, (t5)
     
    153154  la t1, THREAD_DISPATCH_DISABLE_LEVEL
    154155
    155   LREG t2, (t0)
    156   LREG t3, (t1)
     156  Lw t2, (t0)
     157  lw t3, (t1)
    157158  addi t2, t2, -1
    158159  addi t3, t3, -1
    159   SREG t2, (t0)
    160   SREG t3, (t1)
     160  sw t2, (t0)
     161  sw t3, (t1)
    161162
    162163  /* Check if _ISR_Nest_level > 0 */
     
    168169  /* Check if dispatch needed */
    169170  la   x31, DISPATCH_NEEDED
    170   LREG x31, (x31)
     171  lw x31, (x31)
    171172  beqz x31, exception_frame_restore
    172173
     
    216217
    217218  /* Unwind exception frame */
    218   addi sp, sp, 144
     219  addi sp, sp, 36 * CPU_SIZEOF_POINTER
    219220
    220221  mret
  • cpukit/score/cpu/riscv/rtems/score/cpu.h

    r2126438a r11ff3a9  
    6767#define CPU_BIG_ENDIAN                           FALSE
    6868#define CPU_LITTLE_ENDIAN                        TRUE
    69 #define CPU_MODES_INTERRUPT_MASK   0x00000001
     69#define CPU_MODES_INTERRUPT_MASK   0x0000000000000001
    7070
    7171/*
     
    7676
    7777typedef struct {
    78   /* riscv32 has 32 32-bit general purpose registers (x0-x31). */
    79   uint32_t x[32];
     78  /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/
     79  unsigned long x[32];
    8080
    8181  /* Special purpose registers */
    82   uint32_t mstatus;
    83   uint32_t mcause;
    84   uint32_t mepc;
     82  unsigned long mstatus;
     83  unsigned long mcause;
     84  unsigned long mepc;
    8585#ifdef RTEMS_SMP
    8686  /**
     
    139139
    140140#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
     141#if __riscv_xlen == 32
    141142#define CPU_STACK_MINIMUM_SIZE  4096
     143#else
     144#define CPU_STACK_MINIMUM_SIZE  4096 * 2
     145#endif
    142146#define CPU_ALIGNMENT 8
    143147#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
     
    153157 */
    154158
    155 static inline uint32_t riscv_interrupt_disable( void )
    156 {
    157   register uint32_t status = read_csr(mstatus);
     159static inline unsigned long riscv_interrupt_disable( void )
     160{
     161  register unsigned long status = read_csr(mstatus);
    158162  clear_csr(mstatus, MSTATUS_MIE);
    159163  return status;
    160164}
    161165
    162 static inline void riscv_interrupt_enable(uint32_t level)
     166static inline void riscv_interrupt_enable(unsigned long level)
    163167{
    164168  write_csr(mstatus, level);
     
    177181    } while(0)
    178182
    179 RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
     183RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level )
    180184{
    181185  return ( level & MSTATUS_MIE ) != 0;
    182186}
    183187
    184 void _CPU_ISR_Set_level( uint32_t level );
    185 
    186 uint32_t _CPU_ISR_Get_level( void );
     188void _CPU_ISR_Set_level( unsigned long level );
     189
     190unsigned long _CPU_ISR_Get_level( void );
    187191
    188192/* end of ISR handler macros */
     
    195199  void *stack_area_begin,
    196200  size_t stack_area_size,
    197   uint32_t new_level,
     201  unsigned long new_level,
    198202  void (*entry_point)( void ),
    199203  bool is_fp,
     
    263267#endif /* ASM */
    264268
     269#if __riscv_xlen == 32
    265270#define CPU_SIZEOF_POINTER 4
     271
     272/* 32-bit load/store instructions */
     273#define LREG lw
     274#define SREG sw
     275
    266276#define CPU_EXCEPTION_FRAME_SIZE 128
     277#else /* xlen = 64 */
     278#define CPU_SIZEOF_POINTER 8
     279
     280/* 64-bit load/store instructions */
     281#define LREG ld
     282#define SREG sd
     283
     284#define CPU_EXCEPTION_FRAME_SIZE 256
     285#endif
     286
    267287#define CPU_PER_CPU_CONTROL_SIZE 0
    268288
     
    271291
    272292typedef struct {
    273   uint32_t x[32];;
     293  unsigned long x[32];;
    274294} CPU_Exception_frame;
    275295
     
    322342
    323343void _CPU_ISR_install_vector(
    324   uint32_t    vector,
     344  unsigned long    vector,
    325345  proc_ptr   new_handler,
    326346  proc_ptr   *old_handler
     
    424444 */
    425445
    426 static inline unsigned int CPU_swap_u32(
    427   unsigned int value
     446static inline uint32_t CPU_swap_u32(
     447  uint32_t value
    428448)
    429449{
  • cpukit/score/cpu/riscv/rtems/score/types.h

    r2126438a r11ff3a9  
    22 * @file
    33 *
    4  * @brief riscv32 Architecture Types API
     4 * @brief RISC-V Architecture Types API
    55 */
    66
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