Changeset 10b51ae in rtems
- Timestamp:
-
07/26/13 13:46:04
(11 years ago)
- Author:
- Sebastian Huber <sebastian.huber@…>
- Branches:
- 4.11, 5, master
- Children:
- e4c9176
- Parents:
- 99970a7
- git-author:
- Sebastian Huber <sebastian.huber@…> (07/26/13 13:46:04)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (07/30/13 07:53:24)
- Message:
-
score: Critical section change in _Thread_Dispatch
If we enter _Thread_Dispatch() then _Thread_Dispatch_disable_level must
be zero. Single processor RTEMS assumes that stores of non-zero values
to _Thread_Dispatch_disable_level are observed by interrupts as non-zero values.
Move the _Thread_Dispatch_set_disable_level( 1 ) out of the first ISR
disabled critical section. In case interrupts happen between the
_Thread_Dispatch_set_disable_level( 1 ) and _ISR_Disable( level ) then
the interrupt will observe a non-zero _Thread_Dispatch_disable_level and
will not issue a _Thread_Dispatch() and we can enter the ISR disabled
section directly after interrupt processing.
This change leads to symmetry between the single processor and SMP
configuration.
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(No files)
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