Changeset 10483cba in rtems


Ignore:
Timestamp:
Nov 30, 2007, 7:55:46 PM (12 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.9, master
Children:
8da6d77d
Parents:
431bcd75
Message:

2007-11-30 Till Straumann <strauman@…>

  • irq/irq.h, irq/irq.c (removed), irq/no_pic.c (added), irq/irq_init.c, Makefile.am: The PSIM BSP (currently) has no support for an interrupt controller or interrupts other than the decrementer. Removed all definitions for PCI + ISA interrupts and all unnecessary code (leftovers from copying). Separated PIC-specific bits into 'no_pic.c' which allows us to use 'irq.c' (i.e., more code) from 'shared'.
Location:
c/src/lib/libbsp/powerpc/psim
Files:
1 added
1 deleted
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/psim/ChangeLog

    r431bcd75 r10483cba  
     12007-11-30      Till Straumann <strauman@slac.stanford.edu>
     2        * irq/irq.h, irq/irq.c (removed), irq/no_pic.c (added),
     3        irq/irq_init.c, Makefile.am: The PSIM BSP (currently)
     4        has no support for an interrupt controller or interrupts
     5        other than the decrementer. Removed all definitions for PCI + ISA
     6        interrupts and all unnecessary code (leftovers from copying).
     7        Separated PIC-specific bits into 'no_pic.c' which allows us
     8        to use 'irq.c' (i.e., more code) from 'shared'.
     9
    1102007-11-30      Till Straumann <strauman@slac.stanford.edu>
    211
  • c/src/lib/libbsp/powerpc/psim/Makefile.am

    r431bcd75 r10483cba  
    6666
    6767noinst_PROGRAMS += irq.rel
    68 irq_rel_SOURCES = irq/irq.c irq/irq_init.c ../shared/irq/irq_asm.S
     68irq_rel_SOURCES = ../shared/irq/irq.c irq/irq_init.c ../shared/irq/irq_asm.S irq/no_pic.c
    6969irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
    7070irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
  • c/src/lib/libbsp/powerpc/psim/irq/irq.h

    r431bcd75 r10483cba  
    2525#include <rtems/irq.h>
    2626
    27 /*
    28  * 8259 edge/level control definitions at VIA
    29  */
    30 #define ISA8259_M_ELCR          0x4d0
    31 #define ISA8259_S_ELCR          0x4d1
    32 
    33 #define ELCRS_INT15_LVL         0x80
    34 #define ELCRS_INT14_LVL         0x40
    35 #define ELCRS_INT13_LVL         0x20
    36 #define ELCRS_INT12_LVL         0x10
    37 #define ELCRS_INT11_LVL         0x08
    38 #define ELCRS_INT10_LVL         0x04
    39 #define ELCRS_INT9_LVL          0x02
    40 #define ELCRS_INT8_LVL          0x01
    41 #define ELCRM_INT7_LVL          0x80
    42 #define ELCRM_INT6_LVL          0x40
    43 #define ELCRM_INT5_LVL          0x20
    44 #define ELCRM_INT4_LVL          0x10
    45 #define ELCRM_INT3_LVL          0x8
    46 #define ELCRM_INT2_LVL          0x4
    47 #define ELCRM_INT1_LVL          0x2
    48 #define ELCRM_INT0_LVL          0x1
    49 
    5027#define BSP_ASM_IRQ_VECTOR_BASE 0x0
    51     /* PIC's command and mask registers */
    52 #define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
    53 #define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
    54 #define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
    55 #define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
    56 
    57     /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
    58 #define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
    59 #define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
    60 #define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
    6128
    6229#ifndef ASM
     
    6633 */
    6734
    68   /* Base vector for our ISA IRQ handlers. */
    69 #define BSP_ISA_IRQ_VECTOR_BASE         (BSP_ASM_IRQ_VECTOR_BASE)
    70   /*
    71    * ISA IRQ handler related definitions
    72    */
    73 #define BSP_ISA_IRQ_NUMBER              (16)
    74 #define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
    75 #define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER-1)
    76   /*
    77    * PCI IRQ handlers related definitions
    78    * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
    79    */
    80 #define BSP_PCI_IRQ_NUMBER              (16)
    81 #define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
    82 #define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET+BSP_PCI_IRQ_NUMBER-1)
    83   /*
    84    * PowerPc exceptions handled as interrupt where a rtems managed interrupt
    85    * handler might be connected
    86    */
    87 #define BSP_PROCESSOR_IRQ_NUMBER        (1)
    88 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
     35#define BSP_PROCESSOR_IRQ_NUMBER            (1)
     36#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (0)
    8937#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1)
    90   /* Misc vectors for OPENPIC irqs (IPI, timers)
    91    */
    92 #define BSP_MISC_IRQ_NUMBER             (8)
    93 #define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
    94 #define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET+BSP_MISC_IRQ_NUMBER-1)
     38
    9539  /*
    9640   * Summary
    9741   */
    98 #define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
    99 #define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
    100 #define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
    101     /*
    102      * Some ISA IRQ symbolic name definition
    103      */       
    104 #define BSP_ISA_PERIODIC_TIMER          (0)
     42#define BSP_IRQ_NUMBER                  (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
     43#define BSP_LOWEST_OFFSET               (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
     44#define BSP_MAX_OFFSET                  (BSP_IRQ_NUMBER - 1)
    10545
    106 #define BSP_ISA_KEYBOARD                (1)
    107 
    108 #define BSP_UART_COM2_IRQ               (3)
    109 
    110 #define BSP_UART_COM1_IRQ               (4)
    111 
    112 #define BSP_ISA_RT_TIMER1               (8)
    113  
    114 #define BSP_ISA_RT_TIMER3               (10)
    115     /*
    116      * Some PCI IRQ symbolic name definition
    117      */
    118 #define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
    119 #define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
    120     /*
    121      * Some Processor execption handled as rtems IRQ symbolic name definition
    122      */
     46  /*
     47   * Some Processor execption handled as rtems IRQ symbolic name definition
     48   */
    12349#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    12450
    125 typedef unsigned short rtems_i8259_masks;
    126 extern  volatile rtems_i8259_masks i8259s_cache;
     51/* dummy routines - there is no PIC */
     52void BSP_enable_irq_at_pic(const rtems_irq_number);
     53void BSP_disable_irq_at_pic(const rtems_irq_number);
     54int  BSP_setup_the_pic(rtems_irq_global_settings *);
    12755
    128 /*
    129  *  Some items required to make some drivers compile, even though they
    130  *  will not work with this BSP.
    131  */
    132 
    133 #define BSP_irq_enabled_at_i8259s(_name) 0
    134 
    135 #define PCI_DRAM_BASE 0
    136 #define PCI_DRAM_OFFSET 0
    137 #endif
    13856
    13957#endif
     58#endif
  • c/src/lib/libbsp/powerpc/psim/irq/irq_init.c

    r431bcd75 r10483cba  
    3232#endif
    3333
    34 
    3534/*
    3635#define SHOW_ISA_PCI_BRIDGE_SETTINGS
    3736*/
    38 
    39 typedef struct {
    40   unsigned char bus;    /* few chance the PCI/ISA bridge is not on first bus but ... */
    41   unsigned char device;
    42   unsigned char function;
    43 } pci_isa_bridge_device;
    44 
    45 pci_isa_bridge_device* via_82c586 = 0;
    4637
    4738extern unsigned int external_exception_vector_prolog_code_size[];
     
    7162static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
    7263  /*
    73    * actual rpiorities for interrupt :
    74    *    0   means that only current interrupt is masked
    75    *    255 means all other interrupts are masked
    76    */
    77   /*
    78    * ISA interrupts.
    79    * The second entry has a priority of 255 because
    80    * it is the slave pic entry and is should always remain
    81    * unmasked.
    82    */
    83   0,0,
    84   255,
    85   0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
    86   /*
    87    * PCI Interrupts
    88    */
    89   8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
    90   /*
    9164   * Processor exceptions handled as interrupts
    9265   */
    9366  0
    9467};
    95 
    96 void VIA_isa_bridge_interrupts_setup(void)
    97 {
    98   printk("VIA_isa_bridge_interrupts_setup - Shouldn't get here!\n");
    99   return;
    100 }
    10168
    10269  /*
     
    166133#endif
    167134}
    168 
Note: See TracChangeset for help on using the changeset viewer.