Index: c/src/exec/score/cpu/powerpc/ChangeLog
===================================================================
--- c/src/exec/score/cpu/powerpc/ChangeLog	(revision bd9265df54aa02136c70dbaf5091aa338ed62205)
+++ c/src/exec/score/cpu/powerpc/ChangeLog	(revision 0fe89f6a5f7d01bad86fba75c5215865bcc70241)
@@ -1,2 +1,6 @@
+2002-05-01	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
+
+	* rtems/score/ppc.h: Remove PPC_DEBUG_MODEL.
+
 2001-05-14	Till Straumann <strauman@slac.stanford.edu>
 
Index: c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
===================================================================
--- c/src/exec/score/cpu/powerpc/rtems/score/ppc.h	(revision bd9265df54aa02136c70dbaf5091aa338ed62205)
+++ c/src/exec/score/cpu/powerpc/rtems/score/ppc.h	(revision 0fe89f6a5f7d01bad86fba75c5215865bcc70241)
@@ -65,5 +65,4 @@
  *  unless specifically set by the model definition:
  *
- *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
  *    + PPC_INTERRUPT_MAX        - 16
  *    + PPC_CACHE_ALIGNMENT      - 32
@@ -77,16 +76,4 @@
  
 /*
- *  Define the debugging assistance models found in the PPC family.
- *
- *  Standard:         single step and branch trace
- *  Single Step Only: single step only
- *  IBM 4xx:          debug exception
- */
-
-#define PPC_DEBUG_MODEL_STANDARD         1
-#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
-#define PPC_DEBUG_MODEL_IBM4xx           3
-
-/*
  *  Define the low power mode models
  *
@@ -126,5 +113,4 @@
 #define PPC_D_CACHE		1024
 
-#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
 #define PPC_HAS_EXCEPTION_PREFIX 0
 #define PPC_HAS_EVPR             1
@@ -169,6 +155,4 @@
 #define PPC_I_CACHE		0
 #define PPC_D_CACHE		32768
-
-#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
 
 #elif defined(ppc602)
@@ -371,13 +355,4 @@
 #ifndef PPC_ASM
 #define PPC_ASM PPC_ASM_ELF
-#endif
-
-/*
- *  Use the default debug scheme defined in the architectural specification
- *  if another model has not been specified.
- */
-
-#ifndef PPC_DEBUG_MODEL
-#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
 #endif
 
@@ -732,25 +707,4 @@
 #endif
 
-/*
- *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
- *  Environments" and the manuals for various PPC models.
- */
-
-#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
-#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
-#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
-#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
-#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
-#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
-#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
-#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
-#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
-#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
-#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
-#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
-#else
-#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
-#endif
-
 #define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
 #define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
Index: cpukit/score/cpu/powerpc/ChangeLog
===================================================================
--- cpukit/score/cpu/powerpc/ChangeLog	(revision bd9265df54aa02136c70dbaf5091aa338ed62205)
+++ cpukit/score/cpu/powerpc/ChangeLog	(revision 0fe89f6a5f7d01bad86fba75c5215865bcc70241)
@@ -1,2 +1,6 @@
+2002-05-01	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
+
+	* rtems/score/ppc.h: Remove PPC_DEBUG_MODEL.
+
 2001-05-14	Till Straumann <strauman@slac.stanford.edu>
 
Index: cpukit/score/cpu/powerpc/rtems/score/ppc.h
===================================================================
--- cpukit/score/cpu/powerpc/rtems/score/ppc.h	(revision bd9265df54aa02136c70dbaf5091aa338ed62205)
+++ cpukit/score/cpu/powerpc/rtems/score/ppc.h	(revision 0fe89f6a5f7d01bad86fba75c5215865bcc70241)
@@ -65,5 +65,4 @@
  *  unless specifically set by the model definition:
  *
- *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
  *    + PPC_INTERRUPT_MAX        - 16
  *    + PPC_CACHE_ALIGNMENT      - 32
@@ -77,16 +76,4 @@
  
 /*
- *  Define the debugging assistance models found in the PPC family.
- *
- *  Standard:         single step and branch trace
- *  Single Step Only: single step only
- *  IBM 4xx:          debug exception
- */
-
-#define PPC_DEBUG_MODEL_STANDARD         1
-#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
-#define PPC_DEBUG_MODEL_IBM4xx           3
-
-/*
  *  Define the low power mode models
  *
@@ -126,5 +113,4 @@
 #define PPC_D_CACHE		1024
 
-#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
 #define PPC_HAS_EXCEPTION_PREFIX 0
 #define PPC_HAS_EVPR             1
@@ -169,6 +155,4 @@
 #define PPC_I_CACHE		0
 #define PPC_D_CACHE		32768
-
-#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
 
 #elif defined(ppc602)
@@ -371,13 +355,4 @@
 #ifndef PPC_ASM
 #define PPC_ASM PPC_ASM_ELF
-#endif
-
-/*
- *  Use the default debug scheme defined in the architectural specification
- *  if another model has not been specified.
- */
-
-#ifndef PPC_DEBUG_MODEL
-#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
 #endif
 
@@ -732,25 +707,4 @@
 #endif
 
-/*
- *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
- *  Environments" and the manuals for various PPC models.
- */
-
-#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
-#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
-#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
-#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
-#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
-#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
-#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
-#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
-#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
-#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
-#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
-#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
-#else
-#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
-#endif
-
 #define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
 #define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
