Changeset 0fdc099 in rtems


Ignore:
Timestamp:
Apr 16, 2004, 9:51:30 PM (17 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
714f06c
Parents:
3906b3ea
Message:

Remove stray white spaces.

Location:
c/src/lib/libbsp/sh
Files:
36 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sh/gensh1/include/bsp.h

    r3906b3ea r0fdc099  
    1111 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1212 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    13  * 
     13 *
    1414 *
    1515 *  COPYRIGHT (c) 1998.
     
    107107extern void *CPU_Interrupt_stack_high ;
    108108
    109  
     109
    110110/* miscellaneous stuff assumed to exist */
    111111
     
    126126  { console_initialize, console_open, console_close, \
    127127      console_read, console_write, console_control }
    128  
     128
    129129/*
    130130 * NOTE: Use the standard Clock driver entry
  • c/src/lib/libbsp/sh/gensh1/include/coverhd.h

    r3906b3ea r0fdc099  
    1616 *
    1717 *
    18  * These are the figures tmoverhd.exe reported with egcs-980205 -O3 
     18 * These are the figures tmoverhd.exe reported with egcs-980205 -O3
    1919 * on a Diesner OktagonSH/Amos-2.1 board with SH7032/20MHz
    2020 *
     
    2828 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    2929 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    30  * 
     30 *
    3131 *
    3232 *  COPYRIGHT (c) 1998.
  • c/src/lib/libbsp/sh/gensh1/start/start.S

    r3906b3ea r0fdc099  
    5454        ldc     r0,vbr
    5555
    56         ! call the mainline     
     56        ! call the mainline
    5757        mov #0,r4               ! argc
    5858        mov.l main_k,r0
     
    7070        .align 2
    7171stack_k:
    72         .long   SYM(stack)     
     72        .long   SYM(stack)
    7373edata_k:
    7474        .long   SYM(edata)
  • c/src/lib/libbsp/sh/gensh1/startup/bspclean.c

    r3906b3ea r0fdc099  
    1818 *
    1919 *  You should have received a copy of the GNU General Public License
    20  *  along with this program; If not, write to the Free Software Foundation, 
    21  *  675 Mass Ave, Cambridge, MA 02139, USA. 
    22  * 
     20 *  along with this program; If not, write to the Free Software Foundation,
     21 *  675 Mass Ave, Cambridge, MA 02139, USA.
     22 *
    2323 *
    2424 *  COPYRIGHT (c) 1998.
  • c/src/lib/libbsp/sh/gensh1/startup/bspstart.c

    r3906b3ea r0fdc099  
    3030#include <rtems/libio.h>
    3131#include <rtems/libcsupport.h>
    32  
     32
    3333/*
    3434 *  The original table from the application and our copy of it with
     
    4747 *  Use the shared implementations of the following routines
    4848 */
    49  
     49
    5050void bsp_postdriver_hook(void);
    5151void bsp_libc_init( void *, uint32_t, int );
     
    6363 *
    6464 */
    65  
     65
    6666void bsp_pretasking_hook(void)
    6767{
    6868    bsp_libc_init(&HeapStart, (char *)&HeapEnd - (char *)&HeapStart, 0);
    69  
     69
    7070#ifdef RTEMS_DEBUG
    7171    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
     
    8282{
    8383  /*
    84      For real boards you need to setup the hardware 
     84     For real boards you need to setup the hardware
    8585     and need to copy the vector table from rom to ram.
    8686
    87      Depending on the board this can either be done from inside the rom 
     87     Depending on the board this can either be done from inside the rom
    8888     startup code, rtems startup code or here.
    8989   */
    90    
     90
    9191  /*
    9292   *  Allocate the memory for the RTEMS Work Space.  This can come from
     
    104104
    105105  BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ;
    106   BSP_Configuration.work_space_size  = 
    107     (uint32_t) &WorkSpaceEnd - 
     106  BSP_Configuration.work_space_size  =
     107    (uint32_t) &WorkSpaceEnd -
    108108    (uint32_t) &WorkSpaceStart ;
    109  
     109
    110110  /*
    111111   *  initialize the CPU table for this BSP
     
    116116  _CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high ;
    117117
    118   Cpu_table.interrupt_stack_size = 
     118  Cpu_table.interrupt_stack_size =
    119119    (uint32_t) (&CPU_Interrupt_stack_high) -
    120120    (uint32_t) (&CPU_Interrupt_stack_low) ;
     
    124124  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    125125  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    126  
     126
    127127#if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE )
    128128  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
  • c/src/lib/libbsp/sh/gensh2/console/config.c

    r3906b3ea r0fdc099  
    1 /* 
     1/*
    22 * This file contains the TTY driver table. The implementation is
    33 * based on libchip/serial drivers, but it uses internal SHx SCI so
     
    2626
    2727
    28 /* 
     28/*
    2929 * Function set for interrupt enabled termios console
    3030 */
     
    4242};
    4343
    44 /* 
     44/*
    4545 * Function set for polled termios console
    4646 */
     
    8282    { 0 }
    8383};
    84    
     84
    8585
    8686console_tbl     Console_Port_Tbl[] = {
  • c/src/lib/libbsp/sh/gensh2/include/bsp.h

    r3906b3ea r0fdc099  
    1111 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1212 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    13  * 
     13 *
    1414 *
    1515 *  COPYRIGHT (c) 1998.
     
    124124extern void *CPU_Interrupt_stack_high ;
    125125
    126  
     126
    127127/* miscellaneous stuff assumed to exist */
    128128
  • c/src/lib/libbsp/sh/gensh2/include/coverhd.h

    r3906b3ea r0fdc099  
    1616 *
    1717 *
    18  * These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4 
     18 * These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4
    1919 * on a Hitachi SH7045F Evaluation Board with SH7045F at 29 MHz
    2020 *
     
    2828 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    2929 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    30  * 
     30 *
    3131 *  The license and distribution terms for this file may be
    3232 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libbsp/sh/gensh2/start/start.S

    r3906b3ea r0fdc099  
    1414 *  100 Pinnacle Way, Suite 140
    1515 *  Norcross, GA 30071 U.S.A.
    16  * 
     16 *
    1717 *
    1818 *  This modified file may be copied and distributed in accordance
     
    7676        mov.l   @r0, r1 ! Shadow vect tbl addr
    7777        stc             vbr, r2 ! Original vect tbl addr
    78         and             #0, r0 
     78        and             #0, r0
    7979        mov             r0, r4  ! 0 in r4 and r0
    8080
     
    136136#endif /* ! STANDALONE_EVB */
    137137
    138         ! call the mainline     
     138        ! call the mainline
    139139        mov #0,r4               ! argc
    140140        mov.l main_k,r0
     
    158158        .align 2
    159159stack_k:
    160         .long   SYM(stack)     
     160        .long   SYM(stack)
    161161edata_k:
    162162        .long   SYM(edata)
  • c/src/lib/libbsp/sh/gensh2/startup/bspclean.c

    r3906b3ea r0fdc099  
    1818 *
    1919 *  You should have received a copy of the GNU General Public License
    20  *  along with this program; If not, write to the Free Software Foundation, 
    21  *  675 Mass Ave, Cambridge, MA 02139, USA. 
    22  * 
     20 *  along with this program; If not, write to the Free Software Foundation,
     21 *  675 Mass Ave, Cambridge, MA 02139, USA.
     22 *
    2323 *
    2424 *  COPYRIGHT (c) 1998.
  • c/src/lib/libbsp/sh/gensh2/startup/bspstart.c

    r3906b3ea r0fdc099  
    3030#include <rtems/libio.h>
    3131#include <rtems/libcsupport.h>
    32  
     32
    3333/*
    3434 *  The original table from the application and our copy of it with
     
    4949 *  Use the shared implementations of the following routines
    5050 */
    51  
     51
    5252void bsp_postdriver_hook(void);
    5353void bsp_libc_init( void *, uint32_t, int );
     
    6565 *
    6666 */
    67  
     67
    6868void bsp_pretasking_hook(void)
    6969{
    7070    bsp_libc_init(&HeapStart, (char *)&HeapEnd - (char *)&HeapStart, 0);
    71  
     71
    7272#ifdef RTEMS_DEBUG
    7373    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
     
    8484{
    8585  /*
    86      For real boards you need to setup the hardware 
     86     For real boards you need to setup the hardware
    8787     and need to copy the vector table from rom to ram.
    8888
    89      Depending on the board this can ether be done from inside the rom 
     89     Depending on the board this can ether be done from inside the rom
    9090     startup code, rtems startup code or here.
    9191   */
     
    111111
    112112  BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ;
    113   BSP_Configuration.work_space_size  = 
     113  BSP_Configuration.work_space_size  =
    114114    &WorkSpaceEnd - &WorkSpaceStart ;
    115  
     115
    116116  /*
    117117   *  initialize the CPU table for this BSP
     
    123123
    124124  /* This isn't used anywhere */
    125   Cpu_table.interrupt_stack_size = 
     125  Cpu_table.interrupt_stack_size =
    126126    &CPU_Interrupt_stack_high - &CPU_Interrupt_stack_low ;
    127127#endif
  • c/src/lib/libbsp/sh/gensh2/startup/hw_init.c

    r3906b3ea r0fdc099  
    2828 *  100 Pinnacle Way, Suite 140
    2929 *  Norcross, GA 30071 U.S.A.
    30  * 
     30 *
    3131 *
    3232 *  This file may be copied and distributed in accordance
     
    7575
    7676/*  to be called from 'bspstart.c' */
    77 void bsp_hw_init (void) 
     77void bsp_hw_init (void)
    7878{
    7979  uint16_t   temp16;
     
    8484
    8585  /* FIXME: replace 'magic numbers' */
    86        
     86
    8787  write16(0x5000, PFC_PACRH);  /* Pin function controller - WRHH, WRHL */
    8888  write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */
  • c/src/lib/libbsp/sh/gensh4/console/console.c

    r3906b3ea r0fdc099  
    160160            minor+1,                /* channel */
    161161            (console_mode == CONSOLE_MODE_INT));
    162    
     162
    163163    if (sc == RTEMS_SUCCESSFUL)
    164164        sc = sh4uart_reset(&sh4_uarts[minor]);
    165    
     165
    166166    return sc;
    167167}
     
    183183    if (console_mode != CONSOLE_MODE_IPL)
    184184    /* working from gdb we should not disable port operations */
    185         return sh4uart_disable(&sh4_uarts[minor], 
     185        return sh4uart_disable(&sh4_uarts[minor],
    186186                !(boot_mode == SH4_BOOT_MODE_IPL));
    187187    else
     
    201201console_reserve_resources(rtems_configuration_table *configuration)
    202202{
    203     if ((console_mode != CONSOLE_MODE_RAW) && 
     203    if ((console_mode != CONSOLE_MODE_RAW) &&
    204204            (console_mode != CONSOLE_MODE_IPL))
    205205        rtems_termios_reserve_resources (configuration, 2);
     
    241241                    (console_mode != CONSOLE_MODE_IPL))
    242242        rtems_termios_initialize ();
    243    
     243
    244244    /*
    245245     * Register the devices
     
    273273
    274274        return sc;
    275     }                       
     275    }
    276276
    277277    return RTEMS_SUCCESSFUL;
     
    356356    else
    357357        return RTEMS_SUCCESSFUL;
    358 }   
     358}
    359359
    360360/* console_read --
     
    433433            int count = argp->count;
    434434            int i;
    435            
     435
    436436            for (i = 0; i < count; i++)
    437437            {
  • c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c

    r3906b3ea r0fdc099  
    4040    /* Explicitly turn off the MMU */
    4141    write32(0, SH7750_MMUCR);
    42    
     42
    4343    /* Disable instruction and operand caches */
    4444    write32(0, SH7750_CCR);
    45    
     45
    4646    /* Setup Clock Generator */
    47     /* 
     47    /*
    4848     * Input clock frequency is 16 MHz, MD0=1,
    4949     * CPU clock frequency already selected to 96MHz.
     
    5858    write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 |
    5959            SH7750_WTCSR_KEY, SH7750_WTCSR);
    60    
     60
    6161    /* Turn PLL1 on */
    6262    write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
     
    7272    write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
    7373    write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR);
    74    
     74
    7575    /* Bus State Controller Initialization */
    7676    /*
     
    9494        /* Area 5,6 programmed as a SRAM interface (not PCMCIA) */,
    9595        SH7750_BCR1);
    96    
     96
    9797    write16(
    9898        (SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) |  /* These bits is read-only
     
    106106        SH7750_BCR2_PORTEN,                         /* Use D32-D51 as a port */
    107107        SH7750_BCR2);
    108    
     108
    109109    write32(
    110110        (0 << SH7750_WCR1_DMAIW_S) |  /* 0 required for SDRAM RAS down mode */
     
    126126        (SH7750_WCR2_WS15   << SH7750_WCR2_A3W_S) | /*Area 3 not used*/
    127127        (SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */
    128         (SH7750_WCR2_WS15   << SH7750_WCR2_A1W_S) | /* Area 1 (GDC) 
     128        (SH7750_WCR2_WS15   << SH7750_WCR2_A1W_S) | /* Area 1 (GDC)
    129129                                                       requirements not known*/
    130         (SH7750_WCR2_WS6    << SH7750_WCR2_A0W_S) | /* 4 wait states required 
     130        (SH7750_WCR2_WS6    << SH7750_WCR2_A0W_S) | /* 4 wait states required
    131131                                                       at 48MHz for 70ns mem.,
    132132                                                       set closest greater */
     
    172172    /* Clear refresh timer counter */
    173173    write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
    174    
     174
    175175    /* Time between auto-refresh commands is 15.6 microseconds; refresh
    176176       timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore
    177177       program the refresh timer divider to 187 */
    178     write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR); 
    179    
     178    write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR);
     179
    180180    /* Clear refresh counter */
    181181    write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
    182    
     182
    183183    /* Select refresh counter base frequency as bus frequency/4 = 12 MHz */
    184184    write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR);
     
    186186    /* Initialize Memory Control Register; disable refresh */
    187187    write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR);
    188    
     188
    189189    /* SDRAM power-up initialization require 100 microseconds delay after
    190190       stable power and clock fed; 100 microseconds corresponds to 7 refresh
     
    194194    /* Clear refresh timer counter */
    195195    write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
    196    
     196
    197197    /* Clear refresh counter */
    198198    write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
    199    
     199
    200200    /* Execute Precharge All command */
    201201    write32(0, SH7750_SDRAM_MODE_A2_32BIT(0));
     
    211211       therefore burst length is 8 (32 / 4) */
    212212    write8(0,SH7750_SDRAM_MODE_A2_32BIT(
    213         SDRAM_MODE_BL_8 | 
    214         SDRAM_MODE_BT_SEQ |    /* Only sequential burst mode supported 
     213        SDRAM_MODE_BL_8 |
     214        SDRAM_MODE_BT_SEQ |    /* Only sequential burst mode supported
    215215                                  in SH7750 */
    216216        SDRAM_MODE_CL_2 |      /* CAS latency is 2 */
     
    218218    );
    219219    /* Bus State Controller initialized now */
    220    
     220
    221221    /* Disable DMA controller */
    222222    write32(0, SH7750_DMAOR);
    223    
     223
    224224    /* I/O port setup */
    225225    /* Configure all port bits as output - to fasciliate debugging */
    226226    write32(
    227         SH7750_PCTRA_PBOUT(0)  | SH7750_PCTRA_PBOUT(1) | 
     227        SH7750_PCTRA_PBOUT(0)  | SH7750_PCTRA_PBOUT(1) |
    228228        SH7750_PCTRA_PBOUT(2)  | SH7750_PCTRA_PBOUT(3) |
    229         SH7750_PCTRA_PBOUT(4)  | SH7750_PCTRA_PBOUT(5) | 
     229        SH7750_PCTRA_PBOUT(4)  | SH7750_PCTRA_PBOUT(5) |
    230230        SH7750_PCTRA_PBOUT(6)  | SH7750_PCTRA_PBOUT(7) |
    231         SH7750_PCTRA_PBOUT(8)  | SH7750_PCTRA_PBOUT(9) | 
     231        SH7750_PCTRA_PBOUT(8)  | SH7750_PCTRA_PBOUT(9) |
    232232        SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) |
    233         SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) | 
     233        SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) |
    234234        SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15),
    235235        SH7750_PCTRA);
     
    241241    write32(0, SH7750_PDTRA);
    242242    write32(0, SH7750_PDTRB);
    243    
     243
    244244    /* Interrupt Controller Initialization */
    245245    write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent
     
    255255        (0 << SH7750_IPRB_WDT_S) |
    256256        (0 << SH7750_IPRB_REF_S) |
    257         (0 << SH7750_IPRB_SCI1_S), 
     257        (0 << SH7750_IPRB_SCI1_S),
    258258        SH7750_IPRB);
    259259    write16(
     
    266266}
    267267
    268 /* 
     268/*
    269269 * cache_on --
    270  *      Enable instruction and operand caches 
     270 *      Enable instruction and operand caches
    271271 */
    272272void bsp_cache_on(void)
     
    275275    {
    276276        case SH4_BOOT_MODE_FLASH:
    277             write32(SH7750_CCR_ICI | SH7750_CCR_ICE | 
    278                     SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE, 
     277            write32(SH7750_CCR_ICI | SH7750_CCR_ICE |
     278                    SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE,
    279279                    SH7750_CCR);
    280280            break;
  • c/src/lib/libbsp/sh/gensh4/include/bsp.h

    r3906b3ea r0fdc099  
    1515 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1616 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    17  * 
     17 *
    1818 *
    1919 *  COPYRIGHT (c) 1998-2001.
     
    141141#define SH4_BOOT_MODE_FLASH 0
    142142#define SH4_BOOT_MODE_IPL   1
    143  
     143
    144144/* miscellaneous stuff assumed to exist */
    145145
     
    160160  { console_initialize, console_open, console_close, \
    161161      console_read, console_write, console_control }
    162  
     162
    163163/*
    164164 * NOTE: Use the standard Clock driver entry
  • c/src/lib/libbsp/sh/gensh4/include/coverhd.h

    r3906b3ea r0fdc099  
    1616 *
    1717 *
    18  * These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4 
     18 * These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4
    1919 * on a Hitachi SH7045F Evaluation Board with SH7045F at 29 MHz
    2020 *
     
    2828 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    2929 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    30  * 
     30 *
    3131 *  The license and distribution terms for this file may be
    3232 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libbsp/sh/gensh4/include/sdram.h

    r3906b3ea r0fdc099  
    99 * found in the file LICENSE in this distribution or at
    1010 *  http://www.rtems.com/license/LICENSE.
    11  * 
     11 *
    1212 * @(#) $Id$
    1313 */
  • c/src/lib/libbsp/sh/gensh4/start/start.S

    r3906b3ea r0fdc099  
    2020 *  100 Pinnacle Way, Suite 140
    2121 *  Norcross, GA 30071 U.S.A.
    22  * 
     22 *
    2323 *
    2424 *  This modified file may be copied and distributed in accordance
     
    7575        neg     r9, r9
    7676        add     #1, r9  ! r9 == boot_mode
    77        
     77
    7878        ! what is in boot_mode?
    7979        cmp/pl  r9      ! r9 > 0  ->  T = 1
     
    8585#if defined(START_HW_INIT)      /* from $RTEMS_BSP.cfg */
    8686        ! Initialize minimal hardware
    87         ! to run hw_init we need to calculate its address 
     87        ! to run hw_init we need to calculate its address
    8888        ! as it is before data coping
    8989        mov.l   hw_init_k, r0
     
    173173
    174174
    175         ! call the mainline     
     175        ! call the mainline
    176176        mov #0,r4               ! argc
    177177        mov.l main_k,r0
     
    214214        .long   SYM(_VBR_Saved)
    215215stack_k:
    216         .long   SYM(stack)     
     216        .long   SYM(stack)
    217217__bss_start_k:
    218218        .long   __bss_start
  • c/src/lib/libbsp/sh/gensh4/startup/bspstart.c

    r3906b3ea r0fdc099  
    2727#include <bsp.h>
    2828#include <rtems/libio.h>
    29  
     29
    3030#include <rtems/libcsupport.h>
    31  
     31
    3232#include <string.h>
    33  
     33
    3434/*
    3535 *  The original table from the application and our copy of it with
     
    5050 *  Use the shared implementations of the following routines
    5151 */
    52  
     52
    5353void bsp_postdriver_hook(void);
    5454void bsp_libc_init( void *, uint32_t, int );
     
    6666 *
    6767 */
    68  
     68
    6969void bsp_pretasking_hook(void)
    7070{
    7171    bsp_libc_init(&HeapStart, (char *)&HeapEnd - (char *)&HeapStart, 0);
    72  
     72
    7373#ifdef RTEMS_DEBUG
    7474    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
     
    8585{
    8686  /*
    87      For real boards you need to setup the hardware 
     87     For real boards you need to setup the hardware
    8888     and need to copy the vector table from rom to ram.
    8989
    90      Depending on the board this can ether be done from inside the rom 
     90     Depending on the board this can ether be done from inside the rom
    9191     startup code, rtems startup code or here.
    9292   */
     
    112112
    113113  BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ;
    114   BSP_Configuration.work_space_size  = 
    115     (uint32_t) &WorkSpaceEnd - 
     114  BSP_Configuration.work_space_size  =
     115    (uint32_t) &WorkSpaceEnd -
    116116    (uint32_t) &WorkSpaceStart ;
    117  
     117
    118118  /*
    119119   *  initialize the CPU table for this BSP
     
    125125
    126126  /* This isn't used anywhere */
    127   Cpu_table.interrupt_stack_size = 
     127  Cpu_table.interrupt_stack_size =
    128128    (uint32_t) (&CPU_Interrupt_stack_high) -
    129129    (uint32_t) (&CPU_Interrupt_stack_low) ;
  • c/src/lib/libbsp/sh/shared/console.c

    r3906b3ea r0fdc099  
    22 * /dev/console for Hitachi SH 703X
    33 *
    4  * The SH doesn't have a designated console device. Therefore we "alias" 
    5  * another device as /dev/console and revector all calls to /dev/console 
     4 * The SH doesn't have a designated console device. Therefore we "alias"
     5 * another device as /dev/console and revector all calls to /dev/console
    66 * to this device.
    77 *
    8  * This approach is similar to installing a sym-link from one device to 
    9  * another device. If rtems once will support sym-links for devices files, 
     8 * This approach is similar to installing a sym-link from one device to
     9 * another device. If rtems once will support sym-links for devices files,
    1010 * this implementation could be dropped.
    1111 *
     
    1717 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1818 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    19  * 
     19 *
    2020 *
    2121 *  COPYRIGHT (c) 1998.
     
    5858{
    5959  rtems_device_driver status;
    60  
     60
    6161  status = rtems_io_register_name(
    6262    "/dev/console",
     
    9090    arg );
    9191}
    92  
     92
    9393/*
    9494 *  Close entry point
     
    122122
    123123/*
    124  * write bytes to the serial port. Stdout and stderr are the same. 
     124 * write bytes to the serial port. Stdout and stderr are the same.
    125125 */
    126126
  • c/src/lib/libbsp/sh/shared/setvec.c

    r3906b3ea r0fdc099  
    22 *
    33 *  NOTE: This function is considered OBSOLETE and may vanish soon.
    4  *      Calls to set_vector should be replaced by calls to 
     4 *      Calls to set_vector should be replaced by calls to
    55 *      rtems_interrupt_catch or _CPU_ISR_install_raw_handler.
    66 *
  • c/src/lib/libbsp/sh/shsim/gdbsci/gdbsci.c

    r3906b3ea r0fdc099  
    3434#include <sh/sci.h>
    3535
    36 /* 
    37  * gdb assumes area 5/char access (base address & 0x0500000), 
     36/*
     37 * gdb assumes area 5/char access (base address & 0x0500000),
    3838 * the RTEMS's sh7045 code however defaults to area 5/int/short/char access
    3939 * [Very likely a bug in the sh7045 code, RC.]
    4040 */
    41  
     41
    4242#define GDBSCI_BASE 0x05ffffff
    4343
     
    5959 * NOTE: Only device 1 is valid for the simulator
    6060 */
    61  
     61
    6262#define SH_GDBSCI_MINOR_DEVICES       2
    6363
     
    9292  uint8_t       smr;
    9393  uint8_t       brr;
    94  
     94
    9595  if ( c_cflag & CBAUD )
    9696  {
     
    9898      return -1 ;
    9999  }
    100                    
     100
    101101  if ( c_cflag & CSIZE )
    102102  {
     
    123123  else
    124124    smr &= ~SCI_ODD_PARITY;
    125    
     125
    126126  write8( smr, sci_dev->addr + SCI_SMR );
    127127  write8( brr, sci_dev->addr + SCI_BRR );
    128  
     128
    129129  return 0 ;
    130130}
    131131#endif
    132132
    133 static void _sci_init( 
     133static void _sci_init(
    134134  rtems_device_minor_number minor )
    135135{
     
    137137  uint16_t      temp16 ;
    138138
    139   /* Pin function controller initialisation for asynchronous mode */ 
     139  /* Pin function controller initialisation for asynchronous mode */
    140140  if( minor == 0)
    141141    {
     
    144144      temp16 |= (PB_TXD0 | PB_RXD0);
    145145      write16( temp16, PFC_PBCR1);
    146     } 
     146    }
    147147  else
    148148    {
     
    174174{
    175175  struct scidev_t *scidev = &sci_device[minor] ;
    176 #if NOT_SUPPORTED_BY_GDB               
     176#if NOT_SUPPORTED_BY_GDB
    177177  int8_t           ssr ;
    178178
     
    182182  write8(buf,scidev->addr+SCI_TDR);
    183183
    184 #if NOT_SUPPORTED_BY_GDB               
     184#if NOT_SUPPORTED_BY_GDB
    185185  ssr = inb(scidev->addr+SCI_SSR);
    186186  ssr &= ~SCI_TDRE ;
    187187  write8(ssr,scidev->addr+SCI_SSR);
    188188#endif
    189 } 
     189}
    190190
    191191static int _sci_rx_polled (
     
    193193{
    194194  struct scidev_t *scidev = &sci_device[minor] ;
    195        
     195
    196196  unsigned char c;
    197197#if NOT_SUPPORTED_BY_GDB
     
    204204  if ( !(ssr & SCI_RDRF) )
    205205    return -1;
    206 #endif         
     206#endif
    207207  c = read8(scidev->addr + SCI_RDR) ;
    208 #if NOT_SUPPORTED_BY_GDB 
     208#if NOT_SUPPORTED_BY_GDB
    209209  write8(ssr & ~SCI_RDRF,scidev->addr + SCI_SSR);
    210210#endif
     
    223223  rtems_device_driver status ;
    224224  rtems_device_minor_number     i;
    225  
     225
    226226  /*
    227227   * register all possible devices.
     
    240240
    241241  /* default hardware setup */
    242  
     242
    243243  return RTEMS_SUCCESSFUL;
    244244}
     
    262262     return RTEMS_INVALID_NUMBER;
    263263   }
    264  
     264
    265265 /* device already opened */
    266266  if ( sci_device[minor].opened > 0 )
     
    269269    return RTEMS_SUCCESSFUL ;
    270270  }
    271  
     271
    272272  _sci_init( minor );
    273273
     
    292292/* FIXME: Should be one bit delay */
    293293    CPU_delay(50000); /* microseconds */
    294    
     294
    295295    temp8 |= SCI_RE | SCI_TE;
    296296    write8(temp8, sci_device[minor].addr + SCI_SCR);    /* Enable clock output */
    297   } 
     297  }
    298298#endif
    299299
     
    302302  return RTEMS_SUCCESSFUL ;
    303303}
    304  
     304
    305305/*
    306306 *  Close entry point
     
    319319
    320320  sci_device[minor].opened-- ;
    321    
     321
    322322  return RTEMS_SUCCESSFUL ;
    323323}
     
    334334{
    335335  int count = 0;
    336  
     336
    337337  rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg;
    338338  char * buffer = rw_args->buffer;
  • c/src/lib/libbsp/sh/shsim/include/bsp.h

    r3906b3ea r0fdc099  
    1111 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1212 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    13  * 
     13 *
    1414 *  COPYRIGHT (c) 2001.
    1515 *  On-Line Applications Research Corporation (OAR).
     
    7979 *  Simple spin delay in microsecond units for device drivers.
    8080 *  This is very dependent on the clock speed of the target.
    81  * 
     81 *
    8282 * FIXME: Not applicable with gdb's simulator
    83  * Kept for sourcecode compatibility with other sh-BSPs 
     83 * Kept for sourcecode compatibility with other sh-BSPs
    8484 */
    8585#define rtems_bsp_delay( microseconds ) CPU_delay(microseconds)
     
    9898extern void *CPU_Interrupt_stack_high ;
    9999
    100  
     100
    101101/* miscellaneous stuff assumed to exist */
    102102
     
    117117  { console_initialize, console_open, console_close, \
    118118      console_read, console_write, console_control }
    119  
     119
    120120/*
    121121 * NOTE: Use the standard Clock driver entry
  • c/src/lib/libbsp/sh/shsim/include/gdbsci.h

    r3906b3ea r0fdc099  
    99 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1010 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    11  * 
     11 *
    1212 *  $Id$
    1313 */
     
    2121
    2222/*
    23  */ 
     23 */
    2424
    2525#define DEVGDBSCI_DRIVER_TABLE_ENTRY \
  • c/src/lib/libbsp/sh/shsim/start/start.S

    r3906b3ea r0fdc099  
    5454        ldc     r0,vbr
    5555
    56         ! call the mainline     
     56        ! call the mainline
    5757        mov #0,r4               ! argc
    5858        mov.l main_k,r0
     
    7070        .align 2
    7171stack_k:
    72         .long   SYM(stack)     
     72        .long   SYM(stack)
    7373edata_k:
    7474        .long   SYM(edata)
  • c/src/lib/libbsp/sh/shsim/startup/bspstart.c

    r3906b3ea r0fdc099  
    4444 *  Use the shared implementations of the following routines
    4545 */
    46  
     46
    4747void bsp_postdriver_hook(void);
    4848void bsp_libc_init( void *, uint32_t, int );
     
    6060 *
    6161 */
    62  
     62
    6363void bsp_pretasking_hook(void)
    6464{
    6565    bsp_libc_init(&HeapStart, (char *)&HeapEnd - (char *)&HeapStart, 0);
    66  
     66
    6767#ifdef RTEMS_DEBUG
    6868    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
     
    7979{
    8080  /*
    81      For real boards you need to setup the hardware 
     81     For real boards you need to setup the hardware
    8282     and need to copy the vector table from rom to ram.
    8383
    84      Depending on the board this can either be done from inside the rom 
     84     Depending on the board this can either be done from inside the rom
    8585     startup code, rtems startup code or here.
    8686   */
    87    
     87
    8888  /*
    8989   *  Allocate the memory for the RTEMS Work Space.  This can come from
     
    101101
    102102  BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ;
    103   BSP_Configuration.work_space_size  = 
    104     (uint32_t) &WorkSpaceEnd - 
     103  BSP_Configuration.work_space_size  =
     104    (uint32_t) &WorkSpaceEnd -
    105105    (uint32_t) &WorkSpaceStart ;
    106  
     106
    107107  /*
    108108   *  initialize the CPU table for this BSP
     
    113113  _CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high ;
    114114
    115   Cpu_table.interrupt_stack_size = 
     115  Cpu_table.interrupt_stack_size =
    116116    (uint32_t) (&CPU_Interrupt_stack_high) -
    117117    (uint32_t) (&CPU_Interrupt_stack_low) ;
     
    121121  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    122122  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    123  
     123
    124124#if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE )
    125125  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
  • c/src/lib/libbsp/sh/shsim/trap34/console-io.c

    r3906b3ea r0fdc099  
    33 *  for the simulators stdin/out.
    44 *
    5  *  Logic based on newlib-1.8.2/newlib/libc/sys/sh/syscalls.c 
     5 *  Logic based on newlib-1.8.2/newlib/libc/sys/sh/syscalls.c
    66 *
    77 *  COPYRIGHT (c) 1989-2000.
     
    5757
    5858/*
    59  *  console_inbyte_nonblocking 
     59 *  console_inbyte_nonblocking
    6060 *
    6161 *  This routine polls for a character.
  • c/src/lib/libbsp/sh/shsim/trap34/console-support.S

    r3906b3ea r0fdc099  
    1515        rts
    1616        nop
    17          
     17
    1818        .align  2
    1919perrno:
  • c/src/lib/libbsp/sh/simsh4/clock/ckinit.c

    r3906b3ea r0fdc099  
    3030 * These are set by clock driver during its init
    3131 */
    32  
     32
    3333rtems_device_major_number rtems_clock_major = ~0;
    3434rtems_device_minor_number rtems_clock_minor;
     
    4040{
    4141    asm volatile ("\tmov %0,r0\n"
    42                   "\ttrapa\t#4\n" 
    43                   : 
     42                  "\ttrapa\t#4\n"
     43                  :
    4444                  : "r" (period)
    4545                  : "r0" );
     
    104104    {
    105105        rtems_isr_entry  old_isr;
    106         period = Cpu_table.clicks_per_second / 
     106        period = Cpu_table.clicks_per_second /
    107107                 BSP_Configuration.ticks_per_timeslice;
    108        
     108
    109109        /* Configure timer interrupts */
    110110        set_clock_period(period);
    111        
     111
    112112        /* Register the interrupt handler */
    113113        rtems_interrupt_catch(clock_isr, CLOCK_VECTOR, &old_isr);
    114        
     114
    115115        /* Register the driver exit procedure so we can shutdown */
    116116        atexit(Clock_exit);
     
    138138{
    139139    Install_clock (Clock_isr);
    140  
     140
    141141    /* Make major/minor avail to others such as shared memory driver */
    142142    rtems_clock_major = major;
    143143    rtems_clock_minor = minor;
    144  
     144
    145145    return RTEMS_SUCCESSFUL;
    146146}
    147  
     147
    148148
    149149/* Clock_control --
     
    175175         * to do this, it will just be this simple...
    176176         */
    177         if (args->command == rtems_build_name('I', 'S', 'R', ' ')) 
     177        if (args->command == rtems_build_name('I', 'S', 'R', ' '))
    178178        {
    179179            Clock_isr(CLOCK_VECTOR);
  • c/src/lib/libbsp/sh/simsh4/console/console.c

    r3906b3ea r0fdc099  
    165165        return RTEMS_INVALID_NUMBER; /* Single console supported */
    166166    }
    167    
     167
    168168    return RTEMS_SUCCESSFUL;
    169169}
     
    252252 *     RTEMS error code
    253253 */
    254 rtems_device_driver 
    255 console_open(rtems_device_major_number major, 
     254rtems_device_driver
     255console_open(rtems_device_major_number major,
    256256             rtems_device_minor_number minor,
    257257             void *arg)
     
    282282        case CONSOLE_MODE_RAW:
    283283            return RTEMS_SUCCESSFUL;
    284            
     284
    285285        case CONSOLE_MODE_INT:
    286286            return rtems_termios_open(major, minor, arg, &intr_callbacks);
    287            
     287
    288288        case CONSOLE_MODE_POLL:
    289289            return rtems_termios_open(major, minor, arg, &poll_callbacks);
     
    306306 *     RTEMS error code
    307307 */
    308 rtems_device_driver 
     308rtems_device_driver
    309309console_close(rtems_device_major_number major,
    310310              rtems_device_minor_number minor,
     
    416416                rtems_device_minor_number minor,
    417417                void *arg)
    418 { 
     418{
    419419    if (console_mode != CONSOLE_MODE_RAW)
    420420    {
  • c/src/lib/libbsp/sh/simsh4/include/bsp.h

    r3906b3ea r0fdc099  
    1616 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1717 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    18  * 
     18 *
    1919 *
    2020 *  COPYRIGHT (c) 1998-2001.
     
    117117extern void *CPU_Interrupt_stack_high ;
    118118
    119  
     119
    120120/* miscellaneous stuff assumed to exist */
    121121
     
    138138  { ramdisk_initialize, ramdisk_open, ramdisk_close, \
    139139        ramdisk_read, ramdisk_write, ramdisk_control }
    140      
    141  
     140
     141
    142142/*
    143143 * NOTE: Use the standard Clock driver entry
  • c/src/lib/libbsp/sh/simsh4/include/coverhd.h

    r3906b3ea r0fdc099  
    1919 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    2020 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    21  * 
     21 *
    2222 *  The license and distribution terms for this file may be
    2323 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libbsp/sh/simsh4/start/start.S

    r3906b3ea r0fdc099  
    2020 *  100 Pinnacle Way, Suite 140
    2121 *  Norcross, GA 30071 U.S.A.
    22  * 
     22 *
    2323 *
    2424 *  This modified file may be copied and distributed in accordance
     
    8282        lds     r0,fpscr
    8383
    84         ! call the mainline     
     84        ! call the mainline
    8585        mov #0,r4               ! argc
    8686        mov.l main_k,r0
     
    108108        rts
    109109        nop
    110        
     110
    111111!       .align  2
    112112!perrno:
     
    123123
    124124stack_k:
    125         .long   SYM(stack)     
     125        .long   SYM(stack)
    126126edata_k:
    127127        .long   SYM(edata)
  • c/src/lib/libbsp/sh/simsh4/startup/bspstart.c

    r3906b3ea r0fdc099  
    2727#include <bsp.h>
    2828#include <rtems/libio.h>
    29  
     29
    3030#include <rtems/libcsupport.h>
    31  
     31
    3232#include <string.h>
    33  
     33
    3434/*
    3535 *  The original table from the application and our copy of it with
     
    5050 *  Use the shared implementations of the following routines
    5151 */
    52  
     52
    5353void bsp_postdriver_hook(void);
    5454void bsp_libc_init( void *, uint32_t, int );
     
    6666 *
    6767 */
    68  
     68
    6969void bsp_pretasking_hook(void)
    7070{
    7171    bsp_libc_init(&HeapStart, (char *)&HeapEnd - (char *)&HeapStart, 0);
    72  
     72
    7373#ifdef RTEMS_DEBUG
    7474    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
     
    8585{
    8686  /*
    87      For real boards you need to setup the hardware 
     87     For real boards you need to setup the hardware
    8888     and need to copy the vector table from rom to ram.
    8989
    90      Depending on the board this can ether be done from inside the rom 
     90     Depending on the board this can ether be done from inside the rom
    9191     startup code, rtems startup code or here.
    9292   */
     
    112112
    113113  BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ;
    114   BSP_Configuration.work_space_size  = 
    115     (uint32_t) &WorkSpaceEnd - 
     114  BSP_Configuration.work_space_size  =
     115    (uint32_t) &WorkSpaceEnd -
    116116    (uint32_t) &WorkSpaceStart ;
    117  
     117
    118118  /*
    119119   *  initialize the CPU table for this BSP
     
    125125
    126126  /* This isn't used anywhere */
    127   Cpu_table.interrupt_stack_size = 
     127  Cpu_table.interrupt_stack_size =
    128128    (uint32_t) (&CPU_Interrupt_stack_high) -
    129129    (uint32_t) (&CPU_Interrupt_stack_low) ;
  • c/src/lib/libbsp/sh/simsh4/startup/hw_init.c

    r3906b3ea r0fdc099  
    5353 *     none
    5454 */
    55 void bsp_hw_init (void) 
     55void bsp_hw_init (void)
    5656{
    5757}
  • c/src/lib/libbsp/sh/simsh4/timer/timer.c

    r3906b3ea r0fdc099  
    1414 *
    1515 *  http://www.rtems.com/license/LICENSE.
    16  * 
     16 *
    1717 *  $Id$
    1818 */
Note: See TracChangeset for help on using the changeset viewer.