Changeset 0f62af0e in rtems


Ignore:
Timestamp:
09/30/21 21:33:48 (20 months ago)
Author:
Hesham ALMatary <heshamelmatary@…>
Branches:
master
Children:
d03776e
Parents:
edf8b49e
git-author:
Hesham ALMatary <heshamelmatary@…> (09/30/21 21:33:48)
git-committer:
Joel Sherrill <joel@…> (10/13/21 19:45:37)
Message:

bsps: Add MicroBlaze? FPGA BSP

Files:
9 added
4 edited

Legend:

Unmodified
Added
Removed

  • cpukit/score/cpu/microblaze/cpu.c

    redf8b49e r0f62af0e  
    11/*
    2  *  MicroBlaze CPU Dependent Source
    3  *
     2 *  Copyright (c) 2015, Hesham Almatary
    43 *  COPYRIGHT (c) 1989-2011.
    54 *  On-Line Applications Research Corporation (OAR).
    65 *
    7  *  The license and distribution terms for this file may be
    8  *  found in the file LICENSE in this distribution or at
    9  *  http://www.rtems.com/license/LICENSE.
    10  *
    11  *  $Id: cpu.c,v 1.24 2010/03/27 15:02:26 joel Exp $
     6 * Redistribution and use in source and binary forms, with or without
     7 * modification, are permitted provided that the following conditions
     8 * are met:
     9 * 1. Redistributions of source code must retain the above copyright
     10 *    notice, this list of conditions and the following disclaimer.
     11 * 2. Redistributions in binary form must reproduce the above copyright
     12 *   notice, this list of conditions and the following disclaimer in the
     13 *   documentation and/or other materials provided with the distribution.
     14 *
     15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25 * POSSIBILITY OF SUCH DAMAGE.
    1226 */
    1327
    … …  
    4357}
    4458
     59void _CPU_Context_Initialize(
     60  Context_Control *context,
     61  void *stack_area_begin,
     62  size_t stack_area_size,
     63  uint32_t new_level,
     64  void (*entry_point)( void ),
     65  bool is_fp,
     66  void *tls_area
     67)
     68{
     69  uint32_t stack = ((uint32_t) stack_area_begin);
     70  uint32_t stack_high = stack + stack_area_size;
     71
     72  memset(context, 0, sizeof(*context));
     73
     74  context->r[0] = stack_high;
     75  context->r[3] = (uint32_t) entry_point;
     76}
     77
    4578/*PAGE
    4679 *

  • cpukit/score/cpu/microblaze/rtems/asm.h

    redf8b49e r0f62af0e  
    2020 *  of the file is noted.  This file is:
    2121 *
     22 *  Copyright (c) 2015, Hesham Almatary
    2223 *  COPYRIGHT (c) 1994-2006.
    2324 *  On-Line Applications Research Corporation (OAR).
    … …  
    3738#endif
    3839#include <rtems/score/cpuopts.h>
    39 #include <rtems/score/no_cpu.h>
    4040
    4141#ifndef __USER_LABEL_PREFIX__

  • cpukit/score/cpu/microblaze/rtems/score/cpu.h

    redf8b49e r0f62af0e  
     1/*
     2 *  Copyright (c) 2015, Hesham Almatary
     3 *  COPYRIGHT (c) 1989-2008.
     4 *  On-Line Applications Research Corporation (OAR).
     5 *
     6 * Redistribution and use in source and binary forms, with or without
     7 * modification, are permitted provided that the following conditions
     8 * are met:
     9 * 1. Redistributions of source code must retain the above copyright
     10 *    notice, this list of conditions and the following disclaimer.
     11 * 2. Redistributions in binary form must reproduce the above copyright
     12 *   notice, this list of conditions and the following disclaimer in the
     13 *   documentation and/or other materials provided with the distribution.
     14 *
     15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25 * POSSIBILITY OF SUCH DAMAGE.
     26 */
     27
    128/**
    229 * @file rtems/score/cpu.h
    … …  
    1845 *    says "Port Specific Information:".  When porting to RTEMS,
    1946 *    add CPU family specific information in this section
    20  */
    21 
    22 /*
    23  *  COPYRIGHT (c) 1989-2008.
    24  *  On-Line Applications Research Corporation (OAR).
    25  *
    26  *  The license and distribution terms for this file may be
    27  *  found in the file LICENSE in this distribution or at
    28  *  http://www.rtems.com/license/LICENSE.
    29  *
    30  *  $Id: cpu.h,v 1.35 2010/10/21 22:14:20 joel Exp $
    3147 */
    3248
    … …  
    465481 */
    466482typedef struct {
    467     /** This field is a hint that a port will have a number of integer
    468      *  registers that need to be saved at a context switch.
    469      */
    470     uint32_t   some_integer_register;
    471     /** This field is a hint that a port will have a number of system
    472      *  registers that need to be saved at a context switch.
    473      */
    474     uint32_t   some_system_register;
    475 
    476     /** This field is a hint that a port will have a register that
    477      *  is the stack pointer.
    478      */
    479     uint32_t   stack_pointer;
     483    uint32_t r[32];
    480484} Context_Control;
    481485
    … …  
    490494 */
    491495#define _CPU_Context_Get_SP( _context ) \
    492   (_context)->stack_pointer
     496  (_context)->r[0]
    493497
    494498/**
    … …  
    800804/* end of ISR handler macros */
    801805
    802 /* Context handler macros */
    803 
    804 /**
    805  *  @ingroup CPUContext
    806  *  Initialize the context to a state suitable for starting a
    807  *  task after a context restore operation.  Generally, this
    808  *  involves:
    809  *
    810  *     - setting a starting address
    811  *     - preparing the stack
    812  *     - preparing the stack and frame pointers
    813  *     - setting the proper interrupt level in the context
    814  *     - initializing the floating point context
    815  *
    816  *  This routine generally does not set any unnecessary register
    817  *  in the context.  The state of the "general data" registers is
    818  *  undefined at task start time.
    819  *
    820  *  @param[in] _the_context is the context structure to be initialized
    821  *  @param[in] _stack_base is the lowest physical address of this task's stack
    822  *  @param[in] _size is the size of this task's stack
    823  *  @param[in] _isr is the interrupt disable level
    824  *  @param[in] _entry_point is the thread's entry point.  This is
    825  *         always @a _Thread_Handler
    826  *  @param[in] _is_fp is TRUE if the thread is to be a floating
    827  *        point thread.  This is typically only used on CPUs where the
    828  *        FPU may be easily disabled by software such as on the SPARC
    829  *        where the PSR contains an enable FPU bit.
    830  *
    831  *  Port Specific Information:
    832  *
    833  *  XXX document implementation including references if appropriate
    834  */
    835 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    836                                  _isr, _entry_point, _is_fp ) \
    837   { \
    838   }
     806/**
     807 * @brief Initializes the CPU context.
     808 *
     809 * The following steps are performed:
     810 *  - setting a starting address
     811 *  - preparing the stack
     812 *  - preparing the stack and frame pointers
     813 *  - setting the proper interrupt level in the context
     814 *
     815 * @param[in] context points to the context area
     816 * @param[in] stack_area_begin is the low address of the allocated stack area
     817 * @param[in] stack_area_size is the size of the stack area in bytes
     818 * @param[in] new_level is the interrupt level for the task
     819 * @param[in] entry_point is the task's entry point
     820 * @param[in] is_fp is set to @c true if the task is a floating point task
     821 * @param[in] tls_area is the thread-local storage (TLS) area
     822 */
     823void _CPU_Context_Initialize(
     824  Context_Control *context,
     825  void *stack_area_begin,
     826  size_t stack_area_size,
     827  uint32_t new_level,
     828  void (*entry_point)( void ),
     829  bool is_fp,
     830  void *tls_area
     831);
    839832
    840833/**
    … …  
    917910 *  XXX document implementation including references if appropriate
    918911 */
    919 #define _CPU_Fatal_halt( _error ) \
    920   { \
    921   }
     912#define _CPU_Fatal_halt(_source, _error ) \
     913        printk("Fatal Error %d.%d Halted\n",_source, _error); \
     914        for(;;)
    922915
    923916/* end of Fatal Error manager macros */
    … …  
    10601053#endif
    10611054
     1055#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE
     1056#define CPU_TIMESTAMP_USE_INT64 TRUE
     1057#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
     1058
     1059typedef struct {
     1060/* There is no CPU specific per-CPU state */
     1061} CPU_Per_CPU_control;
     1062
     1063#define CPU_SIZEOF_POINTER 4
     1064#define CPU_PER_CPU_CONTROL_SIZE 0
     1065
     1066typedef struct {
     1067  uint32_t r[32];
     1068} CPU_Exception_frame;
     1069
    10621070/* end of Priority handler macros */
    10631071
    … …  
    12571265  (((value&0xff) << 8) | ((value >> 8)&0xff))
    12581266
     1267typedef uint32_t CPU_Counter_ticks;
     1268
     1269CPU_Counter_ticks _CPU_Counter_read( void );
     1270
     1271CPU_Counter_ticks _CPU_Counter_difference(
     1272  CPU_Counter_ticks second,
     1273  CPU_Counter_ticks first
     1274);
     1275
    12591276#ifdef __cplusplus
    12601277}

  • cpukit/score/cpu/microblaze/rtems/score/microblaze.h

    redf8b49e r0f62af0e  
     1/*
     2 *  Copyright (c) 2015, Hesham Almatary
     3 *  COPYRIGHT (c) 1989-2008.
     4 *  On-Line Applications Research Corporation (OAR).
     5 *
     6 * Redistribution and use in source and binary forms, with or without
     7 * modification, are permitted provided that the following conditions
     8 * are met:
     9 * 1. Redistributions of source code must retain the above copyright
     10 *    notice, this list of conditions and the following disclaimer.
     11 * 2. Redistributions in binary form must reproduce the above copyright
     12 *   notice, this list of conditions and the following disclaimer in the
     13 *   documentation and/or other materials provided with the distribution.
     14 *
     15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25 * POSSIBILITY OF SUCH DAMAGE.
     26 */
     27
    128/*
    229 *  This file sets up basic CPU dependency settings based on
    … …  
    532 *  is specified to the NO CPU port.
    633 *
    7  *  COPYRIGHT (c) 1989-2011.
    8  *  On-Line Applications Research Corporation (OAR).
    9  *
    10  *  The license and distribution terms for this file may be
    11  *  found in the file LICENSE in this distribution or at
    12  *  http://www.rtems.com/license/LICENSE.
    13  *
    1434 *  $Id: no_cpu.h,v 1.9 2009/12/02 09:48:25 ralf Exp $
    1535 *
    1636 */
     37
    1738
    1839#ifndef _RTEMS_SCORE_NO_CPU_H
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