Changeset 0eef948f in rtems
- Timestamp:
- 06/08/01 13:29:13 (22 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 622a429
- Parents:
- b7f5447b
- Location:
- c/src/lib/libbsp/powerpc/mbx8xx
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
rb7f5447b r0eef948f 1 2000-06-08 Eric Valette <valette@crf.canon.fr> 2 3 * console/console.c, include/commproc.h, startup/start.S: 4 The printk/printf did not work when loaded by EPPCBUG. They did 5 work when loaded with the BDM debugger. I suspected EPPBUG 6 made some nasty things like patching Communication processor 7 microcode... Anyway, the attached patch: 8 1) Enables to have printk nearly immediately after boot, 9 2) Make printf work automagically (I do not know why except I make a 10 different initialization for printk that should be overwritten by 11 console init later ?) 12 13 I let the default to be using EPPCBUG embedded firmware to boot and 14 using this printk early enabler code (LOADED_BY_EPPCBUG and 15 EARLY_CONSOLE) are on. 16 1 17 2001-05-10 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 18 -
c/src/lib/libbsp/powerpc/mbx8xx/console/console.c
rb7f5447b r0eef948f 90 90 91 91 static void _BSP_null_char( char c ) {return;} 92 static void serial_putchar(const char c); 92 93 93 94 BSP_output_char_function_type BSP_output_char = _BSP_null_char; … … 519 520 }; 520 521 521 522 #define EARLY_CONSOLE 523 #ifdef EARLY_CONSOLE 524 525 #define MBX_CSR1 ((volatile unsigned char *)0xfa100000) 526 #define CSR1_COMEN (unsigned char)0x02 527 #define PROFF_CONS PROFF_SMC1 528 #define CPM_CR_CH_CONS CPM_CR_CH_SMC1 529 #define SMC_INDEX 0 530 531 #include <bsp/commproc.h> 532 533 static cpm8xx_t *cpmp = (cpm8xx_t *)&(((immap_t *)IMAP_ADDR)->im_cpm); 534 535 void 536 serial_init() 537 { 538 volatile smc_t *sp; 539 volatile smc_uart_t *up; 540 volatile cbd_t *tbdf, *rbdf; 541 volatile cpm8xx_t *cp; 542 unsigned int dpaddr, memaddr; 543 bd_t *bd; 544 545 bd = eppcbugInfo; 546 547 cp = cpmp; 548 sp = (smc_t*)&(cp->cp_smc[SMC_INDEX]); 549 up = (smc_uart_t *)&cp->cp_dparam[PROFF_CONS]; 550 551 /* Disable transmitter/receiver. 552 */ 553 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); 554 555 if (*MBX_CSR1 & CSR1_COMEN) { 556 /* COM1 is enabled. Initialize SMC1 and use it for 557 * the console port. 558 */ 559 560 /* Enable SDMA. 561 */ 562 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sdcr = 1; 563 564 /* Use Port B for SMCs instead of other functions. 565 */ 566 cp->cp_pbpar |= 0x00000cc0; 567 cp->cp_pbdir &= ~0x00000cc0; 568 cp->cp_pbodr &= ~0x00000cc0; 569 570 /* Allocate space for two buffer descriptors in the DP ram. 571 * For now, this address seems OK, but it may have to 572 * change with newer versions of the firmware. 573 */ 574 dpaddr = 0x0800; 575 576 /* Grab a few bytes from the top of memory. EPPC-Bug isn't 577 * running any more, so we can do this. 578 */ 579 memaddr = (bd->bi_memsize - 32) & ~15; 580 581 /* Set the physical address of the host memory buffers in 582 * the buffer descriptors. 583 */ 584 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; 585 rbdf->cbd_bufaddr = memaddr; 586 rbdf->cbd_sc = 0; 587 tbdf = rbdf + 1; 588 tbdf->cbd_bufaddr = memaddr+4; 589 tbdf->cbd_sc = 0; 590 591 /* Set up the uart parameters in the parameter ram. 592 */ 593 up->smc_rbase = dpaddr; 594 up->smc_tbase = dpaddr+sizeof(cbd_t); 595 up->smc_rfcr = SMC_EB; 596 up->smc_tfcr = SMC_EB; 597 598 /* Set UART mode, 8 bit, no parity, one stop. 599 * Enable receive and transmit. 600 */ 601 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; 602 603 /* Mask all interrupts and remove anything pending. 604 */ 605 sp->smc_smcm = 0; 606 sp->smc_smce = 0xff; 607 608 /* Set up the baud rate generator. 609 * See 8xx_io/commproc.c for details. 610 */ 611 cp->cp_simode = 0x10000000; 612 cp->cp_brgc1 = 613 ((((bd->bi_intfreq * 1000000)/16) / 9600) << 1) | CPM_BRG_EN; 614 615 /* Enable SMC1 for console output. 616 */ 617 *MBX_CSR1 &= ~CSR1_COMEN; 618 } 619 else { 620 /* SMCx is used as console port. 621 */ 622 tbdf = (cbd_t *)&cp->cp_dpmem[up->smc_tbase]; 623 rbdf = (cbd_t *)&cp->cp_dpmem[up->smc_rbase]; 624 625 /* Issue a stop transmit, and wait for it. 626 */ 627 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_CONS, 628 CPM_CR_STOP_TX) | CPM_CR_FLG; 629 while (cp->cp_cpcr & CPM_CR_FLG); 630 } 631 632 /* Make the first buffer the only buffer. 633 */ 634 tbdf->cbd_sc |= BD_SC_WRAP; 635 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; 636 637 /* Single character receive. 638 */ 639 up->smc_mrblr = 1; 640 up->smc_maxidl = 0; 641 642 /* Initialize Tx/Rx parameters. 643 */ 644 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_CONS, CPM_CR_INIT_TRX) | CPM_CR_FLG; 645 while (cp->cp_cpcr & CPM_CR_FLG); 646 647 /* Enable transmitter/receiver. 648 */ 649 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; 650 BSP_output_char = serial_putchar; 651 } 652 653 void 654 serial_putchar(const char c) 655 { 656 volatile cbd_t *tbdf; 657 volatile char *buf; 658 volatile smc_uart_t *up; 659 660 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; 661 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; 662 663 /* Wait for last character to go. 664 */ 665 buf = (char *)tbdf->cbd_bufaddr; 666 while (tbdf->cbd_sc & BD_SC_READY); 667 668 *buf = c; 669 tbdf->cbd_datlen = 1; 670 tbdf->cbd_sc |= BD_SC_READY; 671 } 672 673 char 674 serial_getc() 675 { 676 volatile cbd_t *rbdf; 677 volatile char *buf; 678 volatile smc_uart_t *up; 679 char c; 680 681 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; 682 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; 683 684 /* Wait for character to show up. 685 */ 686 buf = (char *)rbdf->cbd_bufaddr; 687 while (rbdf->cbd_sc & BD_SC_EMPTY); 688 c = *buf; 689 rbdf->cbd_sc |= BD_SC_EMPTY; 690 691 return(c); 692 } 693 694 int 695 serial_tstc() 696 { 697 volatile cbd_t *rbdf; 698 volatile smc_uart_t *up; 699 700 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; 701 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; 702 703 return(!(rbdf->cbd_sc & BD_SC_EMPTY)); 704 } 705 706 #endif 522 707 /* 523 708 *************** -
c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h
rb7f5447b r0eef948f 23 23 /* CPM Command register. 24 24 */ 25 #define CPM_CR_RST ((u short)0x8000)26 #define CPM_CR_OPCODE ((u short)0x0f00)27 #define CPM_CR_CHAN ((u short)0x00f0)28 #define CPM_CR_FLG ((u short)0x0001)25 #define CPM_CR_RST ((unsigned short)0x8000) 26 #define CPM_CR_OPCODE ((unsigned short)0x0f00) 27 #define CPM_CR_CHAN ((unsigned short)0x00f0) 28 #define CPM_CR_FLG ((unsigned short)0x0001) 29 29 30 30 /* Some commands (there are more...later) 31 31 */ 32 #define CPM_CR_INIT_TRX ((u short)0x0000)33 #define CPM_CR_INIT_RX ((u short)0x0001)34 #define CPM_CR_INIT_TX ((u short)0x0002)35 #define CPM_CR_STOP_TX ((u short)0x0004)36 #define CPM_CR_RESTART_TX ((u short)0x0006)37 #define CPM_CR_SET_GADDR ((u short)0x0008)32 #define CPM_CR_INIT_TRX ((unsigned short)0x0000) 33 #define CPM_CR_INIT_RX ((unsigned short)0x0001) 34 #define CPM_CR_INIT_TX ((unsigned short)0x0002) 35 #define CPM_CR_STOP_TX ((unsigned short)0x0004) 36 #define CPM_CR_RESTART_TX ((unsigned short)0x0006) 37 #define CPM_CR_SET_GADDR ((unsigned short)0x0008) 38 38 39 39 /* Channel numbers. 40 40 */ 41 #define CPM_CR_CH_SCC1 ((u short)0x0000)42 #define CPM_CR_CH_I2C ((u short)0x0001) /* I2C and IDMA1 */43 #define CPM_CR_CH_SCC2 ((u short)0x0004)44 #define CPM_CR_CH_SPI ((u short)0x0005) /* SPI / IDMA2 / Timers */45 #define CPM_CR_CH_SCC3 ((u short)0x0008)46 #define CPM_CR_CH_SMC1 ((u short)0x0009) /* SMC1 / DSP1 */47 #define CPM_CR_CH_SCC4 ((u short)0x000c)48 #define CPM_CR_CH_SMC2 ((u short)0x000d) /* SMC2 / DSP2 */41 #define CPM_CR_CH_SCC1 ((unsigned short)0x0000) 42 #define CPM_CR_CH_I2C ((unsigned short)0x0001) /* I2C and IDMA1 */ 43 #define CPM_CR_CH_SCC2 ((unsigned short)0x0004) 44 #define CPM_CR_CH_SPI ((unsigned short)0x0005) /* SPI / IDMA2 / Timers */ 45 #define CPM_CR_CH_SCC3 ((unsigned short)0x0008) 46 #define CPM_CR_CH_SMC1 ((unsigned short)0x0009) /* SMC1 / DSP1 */ 47 #define CPM_CR_CH_SCC4 ((unsigned short)0x000c) 48 #define CPM_CR_CH_SMC2 ((unsigned short)0x000d) /* SMC2 / DSP2 */ 49 49 50 50 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) … … 55 55 * Currently the first 512 and last 256 bytes are used for microcode. 56 56 */ 57 #define CPM_DATAONLY_BASE ((u int)0x0800)58 #define CPM_DATAONLY_SIZE ((u int)0x0700)59 #define CPM_DP_NOSPACE ((u int)0x7fffffff)57 #define CPM_DATAONLY_BASE ((unsigned int)0x0800) 58 #define CPM_DATAONLY_SIZE ((unsigned int)0x0700) 59 #define CPM_DP_NOSPACE ((unsigned int)0x7fffffff) 60 60 61 61 /* Export the base address of the communication processor registers … … 63 63 */ 64 64 extern cpm8xx_t *cpmp; /* Pointer to comm processor */ 65 u int m8xx_cpm_dpalloc(uint size);66 u int m8xx_cpm_hostalloc(uint size);67 void m8xx_cpm_setbrg(uint brg, uint rate);65 unsigned int m8xx_cpm_dpalloc(unsigned int size); 66 unsigned int m8xx_cpm_hostalloc(unsigned int size); 67 void m8xx_cpm_setbrg(unsigned int brg, unsigned int rate); 68 68 69 69 /* Buffer descriptors used by many of the CPM protocols. 70 70 */ 71 71 typedef struct cpm_buf_desc { 72 u short cbd_sc; /* Status and Control */73 u short cbd_datlen; /* Data length in buffer */74 u int cbd_bufaddr; /* Buffer address in host memory */72 unsigned short cbd_sc; /* Status and Control */ 73 unsigned short cbd_datlen; /* Data length in buffer */ 74 unsigned int cbd_bufaddr; /* Buffer address in host memory */ 75 75 } cbd_t; 76 76 77 #define BD_SC_EMPTY ((u short)0x8000) /* Recieve is empty */78 #define BD_SC_READY ((u short)0x8000) /* Transmit is ready */79 #define BD_SC_WRAP ((u short)0x2000) /* Last buffer descriptor */80 #define BD_SC_INTRPT ((u short)0x1000) /* Interrupt on change */81 #define BD_SC_CM ((u short)0x0200) /* Continous mode */82 #define BD_SC_ID ((u short)0x0100) /* Rec'd too many idles */83 #define BD_SC_P ((u short)0x0100) /* xmt preamble */84 #define BD_SC_BR ((u short)0x0020) /* Break received */85 #define BD_SC_FR ((u short)0x0010) /* Framing error */86 #define BD_SC_PR ((u short)0x0008) /* Parity error */87 #define BD_SC_OV ((u short)0x0002) /* Overrun */88 #define BD_SC_CD ((u short)0x0001) /* ?? */77 #define BD_SC_EMPTY ((unsigned short)0x8000) /* Recieve is empty */ 78 #define BD_SC_READY ((unsigned short)0x8000) /* Transmit is ready */ 79 #define BD_SC_WRAP ((unsigned short)0x2000) /* Last buffer descriptor */ 80 #define BD_SC_INTRPT ((unsigned short)0x1000) /* Interrupt on change */ 81 #define BD_SC_CM ((unsigned short)0x0200) /* Continous mode */ 82 #define BD_SC_ID ((unsigned short)0x0100) /* Rec'd too many idles */ 83 #define BD_SC_P ((unsigned short)0x0100) /* xmt preamble */ 84 #define BD_SC_BR ((unsigned short)0x0020) /* Break received */ 85 #define BD_SC_FR ((unsigned short)0x0010) /* Framing error */ 86 #define BD_SC_PR ((unsigned short)0x0008) /* Parity error */ 87 #define BD_SC_OV ((unsigned short)0x0002) /* Overrun */ 88 #define BD_SC_CD ((unsigned short)0x0001) /* ?? */ 89 89 90 90 /* Parameter RAM offsets. 91 91 */ 92 #define PROFF_SCC1 ((u int)0x0000)93 #define PROFF_SCC2 ((u int)0x0100)94 #define PROFF_SCC3 ((u int)0x0200)95 #define PROFF_SMC1 ((u int)0x0280)96 #define PROFF_SCC4 ((u int)0x0300)97 #define PROFF_SMC2 ((u int)0x0380)92 #define PROFF_SCC1 ((unsigned int)0x0000) 93 #define PROFF_SCC2 ((unsigned int)0x0100) 94 #define PROFF_SCC3 ((unsigned int)0x0200) 95 #define PROFF_SMC1 ((unsigned int)0x0280) 96 #define PROFF_SCC4 ((unsigned int)0x0300) 97 #define PROFF_SMC2 ((unsigned int)0x0380) 98 98 99 99 /* Define enough so I can at least use the serial port as a UART. 100 100 */ 101 101 typedef struct smc_uart { 102 u short smc_rbase; /* Rx Buffer descriptor base address */103 u short smc_tbase; /* Tx Buffer descriptor base address */104 u _char smc_rfcr; /* Rx function code */105 u _char smc_tfcr; /* Tx function code */106 u short smc_mrblr; /* Max receive buffer length */107 u int smc_rstate; /* Internal */108 u int smc_idp; /* Internal */109 u short smc_rbptr; /* Internal */110 u short smc_ibc; /* Internal */111 u int smc_rxtmp; /* Internal */112 u int smc_tstate; /* Internal */113 u int smc_tdp; /* Internal */114 u short smc_tbptr; /* Internal */115 u short smc_tbc; /* Internal */116 u int smc_txtmp; /* Internal */117 u short smc_maxidl; /* Maximum idle characters */118 u short smc_tmpidl; /* Temporary idle counter */119 u short smc_brklen; /* Last received break length */120 u short smc_brkec; /* rcv'd break condition counter */121 u short smc_brkcr; /* xmt break count register */122 u short smc_rmask; /* Temporary bit mask */102 unsigned short smc_rbase; /* Rx Buffer descriptor base address */ 103 unsigned short smc_tbase; /* Tx Buffer descriptor base address */ 104 unsigned char smc_rfcr; /* Rx function code */ 105 unsigned char smc_tfcr; /* Tx function code */ 106 unsigned short smc_mrblr; /* Max receive buffer length */ 107 unsigned int smc_rstate; /* Internal */ 108 unsigned int smc_idp; /* Internal */ 109 unsigned short smc_rbptr; /* Internal */ 110 unsigned short smc_ibc; /* Internal */ 111 unsigned int smc_rxtmp; /* Internal */ 112 unsigned int smc_tstate; /* Internal */ 113 unsigned int smc_tdp; /* Internal */ 114 unsigned short smc_tbptr; /* Internal */ 115 unsigned short smc_tbc; /* Internal */ 116 unsigned int smc_txtmp; /* Internal */ 117 unsigned short smc_maxidl; /* Maximum idle characters */ 118 unsigned short smc_tmpidl; /* Temporary idle counter */ 119 unsigned short smc_brklen; /* Last received break length */ 120 unsigned short smc_brkec; /* rcv'd break condition counter */ 121 unsigned short smc_brkcr; /* xmt break count register */ 122 unsigned short smc_rmask; /* Temporary bit mask */ 123 123 } smc_uart_t; 124 124 125 125 /* Function code bits. 126 126 */ 127 #define SMC_EB ((u _char)0x10) /* Set big endian byte order */127 #define SMC_EB ((unsigned char)0x10) /* Set big endian byte order */ 128 128 129 129 /* SMC uart mode register. 130 130 */ 131 #define SMCMR_REN ((u short)0x0001)132 #define SMCMR_TEN ((u short)0x0002)133 #define SMCMR_DM ((u short)0x000c)134 #define SMCMR_SM_GCI ((u short)0x0000)135 #define SMCMR_SM_UART ((u short)0x0020)136 #define SMCMR_SM_TRANS ((u short)0x0030)137 #define SMCMR_SM_MASK ((u short)0x0030)138 #define SMCMR_PM_EVEN ((u short)0x0100) /* Even parity, else odd */139 #define SMCMR_PEN ((u short)0x0200) /* Parity enable */140 #define SMCMR_SL ((u short)0x0400) /* Two stops, else one */141 #define SMCR_CLEN_MASK ((u short)0x7800) /* Character length */131 #define SMCMR_REN ((unsigned short)0x0001) 132 #define SMCMR_TEN ((unsigned short)0x0002) 133 #define SMCMR_DM ((unsigned short)0x000c) 134 #define SMCMR_SM_GCI ((unsigned short)0x0000) 135 #define SMCMR_SM_UART ((unsigned short)0x0020) 136 #define SMCMR_SM_TRANS ((unsigned short)0x0030) 137 #define SMCMR_SM_MASK ((unsigned short)0x0030) 138 #define SMCMR_PM_EVEN ((unsigned short)0x0100) /* Even parity, else odd */ 139 #define SMCMR_PEN ((unsigned short)0x0200) /* Parity enable */ 140 #define SMCMR_SL ((unsigned short)0x0400) /* Two stops, else one */ 141 #define SMCR_CLEN_MASK ((unsigned short)0x7800) /* Character length */ 142 142 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 143 143 … … 151 151 /* Baud rate generators. 152 152 */ 153 #define CPM_BRG_RST ((u int)0x00020000)154 #define CPM_BRG_EN ((u int)0x00010000)155 #define CPM_BRG_EXTC_INT ((u int)0x00000000)156 #define CPM_BRG_EXTC_CLK2 ((u int)0x00004000)157 #define CPM_BRG_EXTC_CLK6 ((u int)0x00008000)158 #define CPM_BRG_ATB ((u int)0x00002000)159 #define CPM_BRG_CD_MASK ((u int)0x00001ffe)160 #define CPM_BRG_DIV16 ((u int)0x00000001)153 #define CPM_BRG_RST ((unsigned int)0x00020000) 154 #define CPM_BRG_EN ((unsigned int)0x00010000) 155 #define CPM_BRG_EXTC_INT ((unsigned int)0x00000000) 156 #define CPM_BRG_EXTC_CLK2 ((unsigned int)0x00004000) 157 #define CPM_BRG_EXTC_CLK6 ((unsigned int)0x00008000) 158 #define CPM_BRG_ATB ((unsigned int)0x00002000) 159 #define CPM_BRG_CD_MASK ((unsigned int)0x00001ffe) 160 #define CPM_BRG_DIV16 ((unsigned int)0x00000001) 161 161 162 162 /* SCCs. 163 163 */ 164 #define SCC_GSMRH_IRP ((u int)0x00040000)165 #define SCC_GSMRH_GDE ((u int)0x00010000)166 #define SCC_GSMRH_TCRC_CCITT ((u int)0x00008000)167 #define SCC_GSMRH_TCRC_BISYNC ((u int)0x00004000)168 #define SCC_GSMRH_TCRC_HDLC ((u int)0x00000000)169 #define SCC_GSMRH_REVD ((u int)0x00002000)170 #define SCC_GSMRH_TRX ((u int)0x00001000)171 #define SCC_GSMRH_TTX ((u int)0x00000800)172 #define SCC_GSMRH_CDP ((u int)0x00000400)173 #define SCC_GSMRH_CTSP ((u int)0x00000200)174 #define SCC_GSMRH_CDS ((u int)0x00000100)175 #define SCC_GSMRH_CTSS ((u int)0x00000080)176 #define SCC_GSMRH_TFL ((u int)0x00000040)177 #define SCC_GSMRH_RFW ((u int)0x00000020)178 #define SCC_GSMRH_TXSY ((u int)0x00000010)179 #define SCC_GSMRH_SYNL16 ((u int)0x0000000c)180 #define SCC_GSMRH_SYNL8 ((u int)0x00000008)181 #define SCC_GSMRH_SYNL4 ((u int)0x00000004)182 #define SCC_GSMRH_RTSM ((u int)0x00000002)183 #define SCC_GSMRH_RSYN ((u int)0x00000001)184 185 #define SCC_GSMRL_SIR ((u int)0x80000000) /* SCC2 only */186 #define SCC_GSMRL_EDGE_NONE ((u int)0x60000000)187 #define SCC_GSMRL_EDGE_NEG ((u int)0x40000000)188 #define SCC_GSMRL_EDGE_POS ((u int)0x20000000)189 #define SCC_GSMRL_EDGE_BOTH ((u int)0x00000000)190 #define SCC_GSMRL_TCI ((u int)0x10000000)191 #define SCC_GSMRL_TSNC_3 ((u int)0x0c000000)192 #define SCC_GSMRL_TSNC_4 ((u int)0x08000000)193 #define SCC_GSMRL_TSNC_14 ((u int)0x04000000)194 #define SCC_GSMRL_TSNC_INF ((u int)0x00000000)195 #define SCC_GSMRL_RINV ((u int)0x02000000)196 #define SCC_GSMRL_TINV ((u int)0x01000000)197 #define SCC_GSMRL_TPL_128 ((u int)0x00c00000)198 #define SCC_GSMRL_TPL_64 ((u int)0x00a00000)199 #define SCC_GSMRL_TPL_48 ((u int)0x00800000)200 #define SCC_GSMRL_TPL_32 ((u int)0x00600000)201 #define SCC_GSMRL_TPL_16 ((u int)0x00400000)202 #define SCC_GSMRL_TPL_8 ((u int)0x00200000)203 #define SCC_GSMRL_TPL_NONE ((u int)0x00000000)204 #define SCC_GSMRL_TPP_ALL1 ((u int)0x00180000)205 #define SCC_GSMRL_TPP_01 ((u int)0x00100000)206 #define SCC_GSMRL_TPP_10 ((u int)0x00080000)207 #define SCC_GSMRL_TPP_ZEROS ((u int)0x00000000)208 #define SCC_GSMRL_TEND ((u int)0x00040000)209 #define SCC_GSMRL_TDCR_32 ((u int)0x00030000)210 #define SCC_GSMRL_TDCR_16 ((u int)0x00020000)211 #define SCC_GSMRL_TDCR_8 ((u int)0x00010000)212 #define SCC_GSMRL_TDCR_1 ((u int)0x00000000)213 #define SCC_GSMRL_RDCR_32 ((u int)0x0000c000)214 #define SCC_GSMRL_RDCR_16 ((u int)0x00008000)215 #define SCC_GSMRL_RDCR_8 ((u int)0x00004000)216 #define SCC_GSMRL_RDCR_1 ((u int)0x00000000)217 #define SCC_GSMRL_RENC_DFMAN ((u int)0x00003000)218 #define SCC_GSMRL_RENC_MANCH ((u int)0x00002000)219 #define SCC_GSMRL_RENC_FM0 ((u int)0x00001000)220 #define SCC_GSMRL_RENC_NRZI ((u int)0x00000800)221 #define SCC_GSMRL_RENC_NRZ ((u int)0x00000000)222 #define SCC_GSMRL_TENC_DFMAN ((u int)0x00000600)223 #define SCC_GSMRL_TENC_MANCH ((u int)0x00000400)224 #define SCC_GSMRL_TENC_FM0 ((u int)0x00000200)225 #define SCC_GSMRL_TENC_NRZI ((u int)0x00000100)226 #define SCC_GSMRL_TENC_NRZ ((u int)0x00000000)227 #define SCC_GSMRL_DIAG_LE ((u int)0x000000c0) /* Loop and echo */228 #define SCC_GSMRL_DIAG_ECHO ((u int)0x00000080)229 #define SCC_GSMRL_DIAG_LOOP ((u int)0x00000040)230 #define SCC_GSMRL_DIAG_NORM ((u int)0x00000000)231 #define SCC_GSMRL_ENR ((u int)0x00000020)232 #define SCC_GSMRL_ENT ((u int)0x00000010)233 #define SCC_GSMRL_MODE_ENET ((u int)0x0000000c)234 #define SCC_GSMRL_MODE_DDCMP ((u int)0x00000009)235 #define SCC_GSMRL_MODE_BISYNC ((u int)0x00000008)236 #define SCC_GSMRL_MODE_V14 ((u int)0x00000007)237 #define SCC_GSMRL_MODE_AHDLC ((u int)0x00000006)238 #define SCC_GSMRL_MODE_PROFIBUS ((u int)0x00000005)239 #define SCC_GSMRL_MODE_UART ((u int)0x00000004)240 #define SCC_GSMRL_MODE_SS7 ((u int)0x00000003)241 #define SCC_GSMRL_MODE_ATALK ((u int)0x00000002)242 #define SCC_GSMRL_MODE_HDLC ((u int)0x00000000)243 244 #define SCC_TODR_TOD ((u short)0x8000)164 #define SCC_GSMRH_IRP ((unsigned int)0x00040000) 165 #define SCC_GSMRH_GDE ((unsigned int)0x00010000) 166 #define SCC_GSMRH_TCRC_CCITT ((unsigned int)0x00008000) 167 #define SCC_GSMRH_TCRC_BISYNC ((unsigned int)0x00004000) 168 #define SCC_GSMRH_TCRC_HDLC ((unsigned int)0x00000000) 169 #define SCC_GSMRH_REVD ((unsigned int)0x00002000) 170 #define SCC_GSMRH_TRX ((unsigned int)0x00001000) 171 #define SCC_GSMRH_TTX ((unsigned int)0x00000800) 172 #define SCC_GSMRH_CDP ((unsigned int)0x00000400) 173 #define SCC_GSMRH_CTSP ((unsigned int)0x00000200) 174 #define SCC_GSMRH_CDS ((unsigned int)0x00000100) 175 #define SCC_GSMRH_CTSS ((unsigned int)0x00000080) 176 #define SCC_GSMRH_TFL ((unsigned int)0x00000040) 177 #define SCC_GSMRH_RFW ((unsigned int)0x00000020) 178 #define SCC_GSMRH_TXSY ((unsigned int)0x00000010) 179 #define SCC_GSMRH_SYNL16 ((unsigned int)0x0000000c) 180 #define SCC_GSMRH_SYNL8 ((unsigned int)0x00000008) 181 #define SCC_GSMRH_SYNL4 ((unsigned int)0x00000004) 182 #define SCC_GSMRH_RTSM ((unsigned int)0x00000002) 183 #define SCC_GSMRH_RSYN ((unsigned int)0x00000001) 184 185 #define SCC_GSMRL_SIR ((unsigned int)0x80000000) /* SCC2 only */ 186 #define SCC_GSMRL_EDGE_NONE ((unsigned int)0x60000000) 187 #define SCC_GSMRL_EDGE_NEG ((unsigned int)0x40000000) 188 #define SCC_GSMRL_EDGE_POS ((unsigned int)0x20000000) 189 #define SCC_GSMRL_EDGE_BOTH ((unsigned int)0x00000000) 190 #define SCC_GSMRL_TCI ((unsigned int)0x10000000) 191 #define SCC_GSMRL_TSNC_3 ((unsigned int)0x0c000000) 192 #define SCC_GSMRL_TSNC_4 ((unsigned int)0x08000000) 193 #define SCC_GSMRL_TSNC_14 ((unsigned int)0x04000000) 194 #define SCC_GSMRL_TSNC_INF ((unsigned int)0x00000000) 195 #define SCC_GSMRL_RINV ((unsigned int)0x02000000) 196 #define SCC_GSMRL_TINV ((unsigned int)0x01000000) 197 #define SCC_GSMRL_TPL_128 ((unsigned int)0x00c00000) 198 #define SCC_GSMRL_TPL_64 ((unsigned int)0x00a00000) 199 #define SCC_GSMRL_TPL_48 ((unsigned int)0x00800000) 200 #define SCC_GSMRL_TPL_32 ((unsigned int)0x00600000) 201 #define SCC_GSMRL_TPL_16 ((unsigned int)0x00400000) 202 #define SCC_GSMRL_TPL_8 ((unsigned int)0x00200000) 203 #define SCC_GSMRL_TPL_NONE ((unsigned int)0x00000000) 204 #define SCC_GSMRL_TPP_ALL1 ((unsigned int)0x00180000) 205 #define SCC_GSMRL_TPP_01 ((unsigned int)0x00100000) 206 #define SCC_GSMRL_TPP_10 ((unsigned int)0x00080000) 207 #define SCC_GSMRL_TPP_ZEROS ((unsigned int)0x00000000) 208 #define SCC_GSMRL_TEND ((unsigned int)0x00040000) 209 #define SCC_GSMRL_TDCR_32 ((unsigned int)0x00030000) 210 #define SCC_GSMRL_TDCR_16 ((unsigned int)0x00020000) 211 #define SCC_GSMRL_TDCR_8 ((unsigned int)0x00010000) 212 #define SCC_GSMRL_TDCR_1 ((unsigned int)0x00000000) 213 #define SCC_GSMRL_RDCR_32 ((unsigned int)0x0000c000) 214 #define SCC_GSMRL_RDCR_16 ((unsigned int)0x00008000) 215 #define SCC_GSMRL_RDCR_8 ((unsigned int)0x00004000) 216 #define SCC_GSMRL_RDCR_1 ((unsigned int)0x00000000) 217 #define SCC_GSMRL_RENC_DFMAN ((unsigned int)0x00003000) 218 #define SCC_GSMRL_RENC_MANCH ((unsigned int)0x00002000) 219 #define SCC_GSMRL_RENC_FM0 ((unsigned int)0x00001000) 220 #define SCC_GSMRL_RENC_NRZI ((unsigned int)0x00000800) 221 #define SCC_GSMRL_RENC_NRZ ((unsigned int)0x00000000) 222 #define SCC_GSMRL_TENC_DFMAN ((unsigned int)0x00000600) 223 #define SCC_GSMRL_TENC_MANCH ((unsigned int)0x00000400) 224 #define SCC_GSMRL_TENC_FM0 ((unsigned int)0x00000200) 225 #define SCC_GSMRL_TENC_NRZI ((unsigned int)0x00000100) 226 #define SCC_GSMRL_TENC_NRZ ((unsigned int)0x00000000) 227 #define SCC_GSMRL_DIAG_LE ((unsigned int)0x000000c0) /* Loop and echo */ 228 #define SCC_GSMRL_DIAG_ECHO ((unsigned int)0x00000080) 229 #define SCC_GSMRL_DIAG_LOOP ((unsigned int)0x00000040) 230 #define SCC_GSMRL_DIAG_NORM ((unsigned int)0x00000000) 231 #define SCC_GSMRL_ENR ((unsigned int)0x00000020) 232 #define SCC_GSMRL_ENT ((unsigned int)0x00000010) 233 #define SCC_GSMRL_MODE_ENET ((unsigned int)0x0000000c) 234 #define SCC_GSMRL_MODE_DDCMP ((unsigned int)0x00000009) 235 #define SCC_GSMRL_MODE_BISYNC ((unsigned int)0x00000008) 236 #define SCC_GSMRL_MODE_V14 ((unsigned int)0x00000007) 237 #define SCC_GSMRL_MODE_AHDLC ((unsigned int)0x00000006) 238 #define SCC_GSMRL_MODE_PROFIBUS ((unsigned int)0x00000005) 239 #define SCC_GSMRL_MODE_UART ((unsigned int)0x00000004) 240 #define SCC_GSMRL_MODE_SS7 ((unsigned int)0x00000003) 241 #define SCC_GSMRL_MODE_ATALK ((unsigned int)0x00000002) 242 #define SCC_GSMRL_MODE_HDLC ((unsigned int)0x00000000) 243 244 #define SCC_TODR_TOD ((unsigned short)0x8000) 245 245 246 246 /* SCC Event and Mask register. … … 252 252 253 253 typedef struct scc_param { 254 u short scc_rbase; /* Rx Buffer descriptor base address */255 u short scc_tbase; /* Tx Buffer descriptor base address */256 u _char scc_rfcr; /* Rx function code */257 u _char scc_tfcr; /* Tx function code */258 u short scc_mrblr; /* Max receive buffer length */259 u int scc_rstate; /* Internal */260 u int scc_idp; /* Internal */261 u short scc_rbptr; /* Internal */262 u short scc_ibc; /* Internal */263 u int scc_rxtmp; /* Internal */264 u int scc_tstate; /* Internal */265 u int scc_tdp; /* Internal */266 u short scc_tbptr; /* Internal */267 u short scc_tbc; /* Internal */268 u int scc_txtmp; /* Internal */269 u int scc_rcrc; /* Internal */270 u int scc_tcrc; /* Internal */254 unsigned short scc_rbase; /* Rx Buffer descriptor base address */ 255 unsigned short scc_tbase; /* Tx Buffer descriptor base address */ 256 unsigned char scc_rfcr; /* Rx function code */ 257 unsigned char scc_tfcr; /* Tx function code */ 258 unsigned short scc_mrblr; /* Max receive buffer length */ 259 unsigned int scc_rstate; /* Internal */ 260 unsigned int scc_idp; /* Internal */ 261 unsigned short scc_rbptr; /* Internal */ 262 unsigned short scc_ibc; /* Internal */ 263 unsigned int scc_rxtmp; /* Internal */ 264 unsigned int scc_tstate; /* Internal */ 265 unsigned int scc_tdp; /* Internal */ 266 unsigned short scc_tbptr; /* Internal */ 267 unsigned short scc_tbc; /* Internal */ 268 unsigned int scc_txtmp; /* Internal */ 269 unsigned int scc_rcrc; /* Internal */ 270 unsigned int scc_tcrc; /* Internal */ 271 271 } sccp_t; 272 272 273 273 /* Function code bits. 274 274 */ 275 #define SCC_EB ((u _char)0x10) /* Set big endian byte order */275 #define SCC_EB ((unsigned char)0x10) /* Set big endian byte order */ 276 276 277 277 /* CPM Ethernet through SCC1. … … 279 279 typedef struct scc_enet { 280 280 sccp_t sen_genscc; 281 u int sen_cpres; /* Preset CRC */282 u int sen_cmask; /* Constant mask for CRC */283 u int sen_crcec; /* CRC Error counter */284 u int sen_alec; /* alignment error counter */285 u int sen_disfc; /* discard frame counter */286 u short sen_pads; /* Tx short frame pad character */287 u short sen_retlim; /* Retry limit threshold */288 u short sen_retcnt; /* Retry limit counter */289 u short sen_maxflr; /* maximum frame length register */290 u short sen_minflr; /* minimum frame length register */291 u short sen_maxd1; /* maximum DMA1 length */292 u short sen_maxd2; /* maximum DMA2 length */293 u short sen_maxd; /* Rx max DMA */294 u short sen_dmacnt; /* Rx DMA counter */295 u short sen_maxb; /* Max BD byte count */296 u short sen_gaddr1; /* Group address filter */297 u short sen_gaddr2;298 u short sen_gaddr3;299 u short sen_gaddr4;300 u int sen_tbuf0data0; /* Save area 0 - current frame */301 u int sen_tbuf0data1; /* Save area 1 - current frame */302 u int sen_tbuf0rba; /* Internal */303 u int sen_tbuf0crc; /* Internal */304 u short sen_tbuf0bcnt; /* Internal */305 u short sen_paddrh; /* physical address (MSB) */306 u short sen_paddrm;307 u short sen_paddrl; /* physical address (LSB) */308 u short sen_pper; /* persistence */309 u short sen_rfbdptr; /* Rx first BD pointer */310 u short sen_tfbdptr; /* Tx first BD pointer */311 u short sen_tlbdptr; /* Tx last BD pointer */312 u int sen_tbuf1data0; /* Save area 0 - current frame */313 u int sen_tbuf1data1; /* Save area 1 - current frame */314 u int sen_tbuf1rba; /* Internal */315 u int sen_tbuf1crc; /* Internal */316 u short sen_tbuf1bcnt; /* Internal */317 u short sen_txlen; /* Tx Frame length counter */318 u short sen_iaddr1; /* Individual address filter */319 u short sen_iaddr2;320 u short sen_iaddr3;321 u short sen_iaddr4;322 u short sen_boffcnt; /* Backoff counter */281 unsigned int sen_cpres; /* Preset CRC */ 282 unsigned int sen_cmask; /* Constant mask for CRC */ 283 unsigned int sen_crcec; /* CRC Error counter */ 284 unsigned int sen_alec; /* alignment error counter */ 285 unsigned int sen_disfc; /* discard frame counter */ 286 unsigned short sen_pads; /* Tx short frame pad character */ 287 unsigned short sen_retlim; /* Retry limit threshold */ 288 unsigned short sen_retcnt; /* Retry limit counter */ 289 unsigned short sen_maxflr; /* maximum frame length register */ 290 unsigned short sen_minflr; /* minimum frame length register */ 291 unsigned short sen_maxd1; /* maximum DMA1 length */ 292 unsigned short sen_maxd2; /* maximum DMA2 length */ 293 unsigned short sen_maxd; /* Rx max DMA */ 294 unsigned short sen_dmacnt; /* Rx DMA counter */ 295 unsigned short sen_maxb; /* Max BD byte count */ 296 unsigned short sen_gaddr1; /* Group address filter */ 297 unsigned short sen_gaddr2; 298 unsigned short sen_gaddr3; 299 unsigned short sen_gaddr4; 300 unsigned int sen_tbuf0data0; /* Save area 0 - current frame */ 301 unsigned int sen_tbuf0data1; /* Save area 1 - current frame */ 302 unsigned int sen_tbuf0rba; /* Internal */ 303 unsigned int sen_tbuf0crc; /* Internal */ 304 unsigned short sen_tbuf0bcnt; /* Internal */ 305 unsigned short sen_paddrh; /* physical address (MSB) */ 306 unsigned short sen_paddrm; 307 unsigned short sen_paddrl; /* physical address (LSB) */ 308 unsigned short sen_pper; /* persistence */ 309 unsigned short sen_rfbdptr; /* Rx first BD pointer */ 310 unsigned short sen_tfbdptr; /* Tx first BD pointer */ 311 unsigned short sen_tlbdptr; /* Tx last BD pointer */ 312 unsigned int sen_tbuf1data0; /* Save area 0 - current frame */ 313 unsigned int sen_tbuf1data1; /* Save area 1 - current frame */ 314 unsigned int sen_tbuf1rba; /* Internal */ 315 unsigned int sen_tbuf1crc; /* Internal */ 316 unsigned short sen_tbuf1bcnt; /* Internal */ 317 unsigned short sen_txlen; /* Tx Frame length counter */ 318 unsigned short sen_iaddr1; /* Individual address filter */ 319 unsigned short sen_iaddr2; 320 unsigned short sen_iaddr3; 321 unsigned short sen_iaddr4; 322 unsigned short sen_boffcnt; /* Backoff counter */ 323 323 324 324 /* NOTE: Some versions of the manual have the following items 325 325 * incorrectly documented. Below is the proper order. 326 326 */ 327 u short sen_taddrh; /* temp address (MSB) */328 u short sen_taddrm;329 u short sen_taddrl; /* temp address (LSB) */327 unsigned short sen_taddrh; /* temp address (MSB) */ 328 unsigned short sen_taddrm; 329 unsigned short sen_taddrl; /* temp address (LSB) */ 330 330 } scc_enet_t; 331 331 … … 336 336 * clock pins. 337 337 */ 338 #define PA_ENET_RXD ((u short)0x0001)339 #define PA_ENET_TXD ((u short)0x0002)340 #define PA_ENET_TCLK ((u short)0x0200)341 #define PA_ENET_RCLK ((u short)0x0800)342 #define PC_ENET_TENA ((u short)0x0001)343 #define PC_ENET_CLSN ((u short)0x0010)344 #define PC_ENET_RENA ((u short)0x0020)338 #define PA_ENET_RXD ((unsigned short)0x0001) 339 #define PA_ENET_TXD ((unsigned short)0x0002) 340 #define PA_ENET_TCLK ((unsigned short)0x0200) 341 #define PA_ENET_RCLK ((unsigned short)0x0800) 342 #define PC_ENET_TENA ((unsigned short)0x0001) 343 #define PC_ENET_CLSN ((unsigned short)0x0010) 344 #define PC_ENET_RENA ((unsigned short)0x0020) 345 345 346 346 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 347 347 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 348 348 */ 349 #define SICR_ENET_MASK ((u int)0x000000ff)350 #define SICR_ENET_CLKRT ((u int)0x0000003d)349 #define SICR_ENET_MASK ((unsigned int)0x000000ff) 350 #define SICR_ENET_CLKRT ((unsigned int)0x0000003d) 351 351 352 352 /* SCC Event register as used by Ethernet. 353 353 */ 354 #define SCCE_ENET_GRA ((u short)0x0080) /* Graceful stop complete */355 #define SCCE_ENET_TXE ((u short)0x0010) /* Transmit Error */356 #define SCCE_ENET_RXF ((u short)0x0008) /* Full frame received */357 #define SCCE_ENET_BSY ((u short)0x0004) /* All incoming buffers full */358 #define SCCE_ENET_TXB ((u short)0x0002) /* A buffer was transmitted */359 #define SCCE_ENET_RXB ((u short)0x0001) /* A buffer was received */354 #define SCCE_ENET_GRA ((unsigned short)0x0080) /* Graceful stop complete */ 355 #define SCCE_ENET_TXE ((unsigned short)0x0010) /* Transmit Error */ 356 #define SCCE_ENET_RXF ((unsigned short)0x0008) /* Full frame received */ 357 #define SCCE_ENET_BSY ((unsigned short)0x0004) /* All incoming buffers full */ 358 #define SCCE_ENET_TXB ((unsigned short)0x0002) /* A buffer was transmitted */ 359 #define SCCE_ENET_RXB ((unsigned short)0x0001) /* A buffer was received */ 360 360 361 361 /* SCC Mode Register (PMSR) as used by Ethernet. 362 362 */ 363 #define SCC_PMSR_HBC ((u short)0x8000) /* Enable heartbeat */364 #define SCC_PMSR_FC ((u short)0x4000) /* Force collision */365 #define SCC_PMSR_RSH ((u short)0x2000) /* Receive short frames */366 #define SCC_PMSR_IAM ((u short)0x1000) /* Check individual hash */367 #define SCC_PMSR_ENCRC ((u short)0x0800) /* Ethernet CRC mode */368 #define SCC_PMSR_PRO ((u short)0x0200) /* Promiscuous mode */369 #define SCC_PMSR_BRO ((u short)0x0100) /* Catch broadcast pkts */370 #define SCC_PMSR_SBT ((u short)0x0080) /* Special backoff timer */371 #define SCC_PMSR_LPB ((u short)0x0040) /* Set Loopback mode */372 #define SCC_PMSR_SIP ((u short)0x0020) /* Sample Input Pins */373 #define SCC_PMSR_LCW ((u short)0x0010) /* Late collision window */374 #define SCC_PMSR_NIB22 ((u short)0x000a) /* Start frame search */375 #define SCC_PMSR_FDE ((u short)0x0001) /* Full duplex enable */363 #define SCC_PMSR_HBC ((unsigned short)0x8000) /* Enable heartbeat */ 364 #define SCC_PMSR_FC ((unsigned short)0x4000) /* Force collision */ 365 #define SCC_PMSR_RSH ((unsigned short)0x2000) /* Receive short frames */ 366 #define SCC_PMSR_IAM ((unsigned short)0x1000) /* Check individual hash */ 367 #define SCC_PMSR_ENCRC ((unsigned short)0x0800) /* Ethernet CRC mode */ 368 #define SCC_PMSR_PRO ((unsigned short)0x0200) /* Promiscuous mode */ 369 #define SCC_PMSR_BRO ((unsigned short)0x0100) /* Catch broadcast pkts */ 370 #define SCC_PMSR_SBT ((unsigned short)0x0080) /* Special backoff timer */ 371 #define SCC_PMSR_LPB ((unsigned short)0x0040) /* Set Loopback mode */ 372 #define SCC_PMSR_SIP ((unsigned short)0x0020) /* Sample Input Pins */ 373 #define SCC_PMSR_LCW ((unsigned short)0x0010) /* Late collision window */ 374 #define SCC_PMSR_NIB22 ((unsigned short)0x000a) /* Start frame search */ 375 #define SCC_PMSR_FDE ((unsigned short)0x0001) /* Full duplex enable */ 376 376 377 377 /* Buffer descriptor control/status used by Ethernet receive. 378 378 */ 379 #define BD_ENET_RX_EMPTY ((u short)0x8000)380 #define BD_ENET_RX_WRAP ((u short)0x2000)381 #define BD_ENET_RX_INTR ((u short)0x1000)382 #define BD_ENET_RX_LAST ((u short)0x0800)383 #define BD_ENET_RX_FIRST ((u short)0x0400)384 #define BD_ENET_RX_MISS ((u short)0x0100)385 #define BD_ENET_RX_LG ((u short)0x0020)386 #define BD_ENET_RX_NO ((u short)0x0010)387 #define BD_ENET_RX_SH ((u short)0x0008)388 #define BD_ENET_RX_CR ((u short)0x0004)389 #define BD_ENET_RX_OV ((u short)0x0002)390 #define BD_ENET_RX_CL ((u short)0x0001)391 #define BD_ENET_RX_STATS ((u short)0x013f) /* All status bits */379 #define BD_ENET_RX_EMPTY ((unsigned short)0x8000) 380 #define BD_ENET_RX_WRAP ((unsigned short)0x2000) 381 #define BD_ENET_RX_INTR ((unsigned short)0x1000) 382 #define BD_ENET_RX_LAST ((unsigned short)0x0800) 383 #define BD_ENET_RX_FIRST ((unsigned short)0x0400) 384 #define BD_ENET_RX_MISS ((unsigned short)0x0100) 385 #define BD_ENET_RX_LG ((unsigned short)0x0020) 386 #define BD_ENET_RX_NO ((unsigned short)0x0010) 387 #define BD_ENET_RX_SH ((unsigned short)0x0008) 388 #define BD_ENET_RX_CR ((unsigned short)0x0004) 389 #define BD_ENET_RX_OV ((unsigned short)0x0002) 390 #define BD_ENET_RX_CL ((unsigned short)0x0001) 391 #define BD_ENET_RX_STATS ((unsigned short)0x013f) /* All status bits */ 392 392 393 393 /* Buffer descriptor control/status used by Ethernet transmit. 394 394 */ 395 #define BD_ENET_TX_READY ((u short)0x8000)396 #define BD_ENET_TX_PAD ((u short)0x4000)397 #define BD_ENET_TX_WRAP ((u short)0x2000)398 #define BD_ENET_TX_INTR ((u short)0x1000)399 #define BD_ENET_TX_LAST ((u short)0x0800)400 #define BD_ENET_TX_TC ((u short)0x0400)401 #define BD_ENET_TX_DEF ((u short)0x0200)402 #define BD_ENET_TX_HB ((u short)0x0100)403 #define BD_ENET_TX_LC ((u short)0x0080)404 #define BD_ENET_TX_RL ((u short)0x0040)405 #define BD_ENET_TX_RCMASK ((u short)0x003c)406 #define BD_ENET_TX_UN ((u short)0x0002)407 #define BD_ENET_TX_CSL ((u short)0x0001)408 #define BD_ENET_TX_STATS ((u short)0x03ff) /* All status bits */395 #define BD_ENET_TX_READY ((unsigned short)0x8000) 396 #define BD_ENET_TX_PAD ((unsigned short)0x4000) 397 #define BD_ENET_TX_WRAP ((unsigned short)0x2000) 398 #define BD_ENET_TX_INTR ((unsigned short)0x1000) 399 #define BD_ENET_TX_LAST ((unsigned short)0x0800) 400 #define BD_ENET_TX_TC ((unsigned short)0x0400) 401 #define BD_ENET_TX_DEF ((unsigned short)0x0200) 402 #define BD_ENET_TX_HB ((unsigned short)0x0100) 403 #define BD_ENET_TX_LC ((unsigned short)0x0080) 404 #define BD_ENET_TX_RL ((unsigned short)0x0040) 405 #define BD_ENET_TX_RCMASK ((unsigned short)0x003c) 406 #define BD_ENET_TX_UN ((unsigned short)0x0002) 407 #define BD_ENET_TX_CSL ((unsigned short)0x0001) 408 #define BD_ENET_TX_STATS ((unsigned short)0x03ff) /* All status bits */ 409 409 410 410 /* SCC as UART … … 412 412 typedef struct scc_uart { 413 413 sccp_t scc_genscc; 414 u int scc_res1; /* Reserved */415 u int scc_res2; /* Reserved */416 u short scc_maxidl; /* Maximum idle chars */417 u short scc_idlc; /* temp idle counter */418 u short scc_brkcr; /* Break count register */419 u short scc_parec; /* receive parity error counter */420 u short scc_frmec; /* receive framing error counter */421 u short scc_nosec; /* receive noise counter */422 u short scc_brkec; /* receive break condition counter */423 u short scc_brkln; /* last received break length */424 u short scc_uaddr1; /* UART address character 1 */425 u short scc_uaddr2; /* UART address character 2 */426 u short scc_rtemp; /* Temp storage */427 u short scc_toseq; /* Transmit out of sequence char */428 u short scc_char1; /* control character 1 */429 u short scc_char2; /* control character 2 */430 u short scc_char3; /* control character 3 */431 u short scc_char4; /* control character 4 */432 u short scc_char5; /* control character 5 */433 u short scc_char6; /* control character 6 */434 u short scc_char7; /* control character 7 */435 u short scc_char8; /* control character 8 */436 u short scc_rccm; /* receive control character mask */437 u short scc_rccr; /* receive control character register */438 u short scc_rlbc; /* receive last break character */414 unsigned int scc_res1; /* Reserved */ 415 unsigned int scc_res2; /* Reserved */ 416 unsigned short scc_maxidl; /* Maximum idle chars */ 417 unsigned short scc_idlc; /* temp idle counter */ 418 unsigned short scc_brkcr; /* Break count register */ 419 unsigned short scc_parec; /* receive parity error counter */ 420 unsigned short scc_frmec; /* receive framing error counter */ 421 unsigned short scc_nosec; /* receive noise counter */ 422 unsigned short scc_brkec; /* receive break condition counter */ 423 unsigned short scc_brkln; /* last received break length */ 424 unsigned short scc_uaddr1; /* UART address character 1 */ 425 unsigned short scc_uaddr2; /* UART address character 2 */ 426 unsigned short scc_rtemp; /* Temp storage */ 427 unsigned short scc_toseq; /* Transmit out of sequence char */ 428 unsigned short scc_char1; /* control character 1 */ 429 unsigned short scc_char2; /* control character 2 */ 430 unsigned short scc_char3; /* control character 3 */ 431 unsigned short scc_char4; /* control character 4 */ 432 unsigned short scc_char5; /* control character 5 */ 433 unsigned short scc_char6; /* control character 6 */ 434 unsigned short scc_char7; /* control character 7 */ 435 unsigned short scc_char8; /* control character 8 */ 436 unsigned short scc_rccm; /* receive control character mask */ 437 unsigned short scc_rccr; /* receive control character register */ 438 unsigned short scc_rlbc; /* receive last break character */ 439 439 } scc_uart_t; 440 440 441 441 /* SCC Event and Mask registers when it is used as a UART. 442 442 */ 443 #define UART_SCCM_GLR ((u short)0x1000)444 #define UART_SCCM_GLT ((u short)0x0800)445 #define UART_SCCM_AB ((u short)0x0200)446 #define UART_SCCM_IDL ((u short)0x0100)447 #define UART_SCCM_GRA ((u short)0x0080)448 #define UART_SCCM_BRKE ((u short)0x0040)449 #define UART_SCCM_BRKS ((u short)0x0020)450 #define UART_SCCM_CCR ((u short)0x0008)451 #define UART_SCCM_BSY ((u short)0x0004)452 #define UART_SCCM_TX ((u short)0x0002)453 #define UART_SCCM_RX ((u short)0x0001)443 #define UART_SCCM_GLR ((unsigned short)0x1000) 444 #define UART_SCCM_GLT ((unsigned short)0x0800) 445 #define UART_SCCM_AB ((unsigned short)0x0200) 446 #define UART_SCCM_IDL ((unsigned short)0x0100) 447 #define UART_SCCM_GRA ((unsigned short)0x0080) 448 #define UART_SCCM_BRKE ((unsigned short)0x0040) 449 #define UART_SCCM_BRKS ((unsigned short)0x0020) 450 #define UART_SCCM_CCR ((unsigned short)0x0008) 451 #define UART_SCCM_BSY ((unsigned short)0x0004) 452 #define UART_SCCM_TX ((unsigned short)0x0002) 453 #define UART_SCCM_RX ((unsigned short)0x0001) 454 454 455 455 /* The SCC PMSR when used as a UART. 456 456 */ 457 #define SCU_PMSR_FLC ((u short)0x8000)458 #define SCU_PMSR_SL ((u short)0x4000)459 #define SCU_PMSR_CL ((u short)0x3000)460 #define SCU_PMSR_UM ((u short)0x0c00)461 #define SCU_PMSR_FRZ ((u short)0x0200)462 #define SCU_PMSR_RZS ((u short)0x0100)463 #define SCU_PMSR_SYN ((u short)0x0080)464 #define SCU_PMSR_DRT ((u short)0x0040)465 #define SCU_PMSR_PEN ((u short)0x0010)466 #define SCU_PMSR_RPM ((u short)0x000c)467 #define SCU_PMSR_REVP ((u short)0x0008)468 #define SCU_PMSR_TPM ((u short)0x0003)469 #define SCU_PMSR_TEVP ((u short)0x0003)457 #define SCU_PMSR_FLC ((unsigned short)0x8000) 458 #define SCU_PMSR_SL ((unsigned short)0x4000) 459 #define SCU_PMSR_CL ((unsigned short)0x3000) 460 #define SCU_PMSR_UM ((unsigned short)0x0c00) 461 #define SCU_PMSR_FRZ ((unsigned short)0x0200) 462 #define SCU_PMSR_RZS ((unsigned short)0x0100) 463 #define SCU_PMSR_SYN ((unsigned short)0x0080) 464 #define SCU_PMSR_DRT ((unsigned short)0x0040) 465 #define SCU_PMSR_PEN ((unsigned short)0x0010) 466 #define SCU_PMSR_RPM ((unsigned short)0x000c) 467 #define SCU_PMSR_REVP ((unsigned short)0x0008) 468 #define SCU_PMSR_TPM ((unsigned short)0x0003) 469 #define SCU_PMSR_TEVP ((unsigned short)0x0003) 470 470 471 471 /* CPM Transparent mode SCC. … … 473 473 typedef struct scc_trans { 474 474 sccp_t st_genscc; 475 u int st_cpres; /* Preset CRC */476 u int st_cmask; /* Constant mask for CRC */475 unsigned int st_cpres; /* Preset CRC */ 476 unsigned int st_cmask; /* Constant mask for CRC */ 477 477 } scc_trans_t; 478 478 … … 485 485 */ 486 486 #define CPMVEC_NR 32 487 #define CPMVEC_PIO_PC15 ((u short)0x1f)488 #define CPMVEC_SCC1 ((u short)0x1e)489 #define CPMVEC_SCC2 ((u short)0x1d)490 #define CPMVEC_SCC3 ((u short)0x1c)491 #define CPMVEC_SCC4 ((u short)0x1b)492 #define CPMVEC_PIO_PC14 ((u short)0x1a)493 #define CPMVEC_TIMER1 ((u short)0x19)494 #define CPMVEC_PIO_PC13 ((u short)0x18)495 #define CPMVEC_PIO_PC12 ((u short)0x17)496 #define CPMVEC_SDMA_CB_ERR ((u short)0x16)497 #define CPMVEC_IDMA1 ((u short)0x15)498 #define CPMVEC_IDMA2 ((u short)0x14)499 #define CPMVEC_TIMER2 ((u short)0x12)500 #define CPMVEC_RISCTIMER ((u short)0x11)501 #define CPMVEC_I2C ((u short)0x10)502 #define CPMVEC_PIO_PC11 ((u short)0x0f)503 #define CPMVEC_PIO_PC10 ((u short)0x0e)504 #define CPMVEC_TIMER3 ((u short)0x0c)505 #define CPMVEC_PIO_PC9 ((u short)0x0b)506 #define CPMVEC_PIO_PC8 ((u short)0x0a)507 #define CPMVEC_PIO_PC7 ((u short)0x09)508 #define CPMVEC_TIMER4 ((u short)0x07)509 #define CPMVEC_PIO_PC6 ((u short)0x06)510 #define CPMVEC_SPI ((u short)0x05)511 #define CPMVEC_SMC1 ((u short)0x04)512 #define CPMVEC_SMC2 ((u short)0x03)513 #define CPMVEC_PIO_PC5 ((u short)0x02)514 #define CPMVEC_PIO_PC4 ((u short)0x01)515 #define CPMVEC_ERROR ((u short)0x00)487 #define CPMVEC_PIO_PC15 ((unsigned short)0x1f) 488 #define CPMVEC_SCC1 ((unsigned short)0x1e) 489 #define CPMVEC_SCC2 ((unsigned short)0x1d) 490 #define CPMVEC_SCC3 ((unsigned short)0x1c) 491 #define CPMVEC_SCC4 ((unsigned short)0x1b) 492 #define CPMVEC_PIO_PC14 ((unsigned short)0x1a) 493 #define CPMVEC_TIMER1 ((unsigned short)0x19) 494 #define CPMVEC_PIO_PC13 ((unsigned short)0x18) 495 #define CPMVEC_PIO_PC12 ((unsigned short)0x17) 496 #define CPMVEC_SDMA_CB_ERR ((unsigned short)0x16) 497 #define CPMVEC_IDMA1 ((unsigned short)0x15) 498 #define CPMVEC_IDMA2 ((unsigned short)0x14) 499 #define CPMVEC_TIMER2 ((unsigned short)0x12) 500 #define CPMVEC_RISCTIMER ((unsigned short)0x11) 501 #define CPMVEC_I2C ((unsigned short)0x10) 502 #define CPMVEC_PIO_PC11 ((unsigned short)0x0f) 503 #define CPMVEC_PIO_PC10 ((unsigned short)0x0e) 504 #define CPMVEC_TIMER3 ((unsigned short)0x0c) 505 #define CPMVEC_PIO_PC9 ((unsigned short)0x0b) 506 #define CPMVEC_PIO_PC8 ((unsigned short)0x0a) 507 #define CPMVEC_PIO_PC7 ((unsigned short)0x09) 508 #define CPMVEC_TIMER4 ((unsigned short)0x07) 509 #define CPMVEC_PIO_PC6 ((unsigned short)0x06) 510 #define CPMVEC_SPI ((unsigned short)0x05) 511 #define CPMVEC_SMC1 ((unsigned short)0x04) 512 #define CPMVEC_SMC2 ((unsigned short)0x03) 513 #define CPMVEC_PIO_PC5 ((unsigned short)0x02) 514 #define CPMVEC_PIO_PC4 ((unsigned short)0x01) 515 #define CPMVEC_ERROR ((unsigned short)0x00) 516 516 517 517 extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); … … 519 519 /* CPM interrupt configuration vector. 520 520 */ 521 #define CICR_SCD_SCC4 ((u int)0x00c00000) /* SCC4 @ SCCd */522 #define CICR_SCC_SCC3 ((u int)0x00200000) /* SCC3 @ SCCc */523 #define CICR_SCB_SCC2 ((u int)0x00040000) /* SCC2 @ SCCb */524 #define CICR_SCA_SCC1 ((u int)0x00000000) /* SCC1 @ SCCa */525 #define CICR_IRL_MASK ((u int)0x0000e000) /* Core interrrupt */526 #define CICR_HP_MASK ((u int)0x00001f00) /* Hi-pri int. */527 #define CICR_IEN ((u int)0x00000080) /* Int. enable */528 #define CICR_SPS ((u int)0x00000001) /* SCC Spread */521 #define CICR_SCD_SCC4 ((unsigned int)0x00c00000) /* SCC4 @ SCCd */ 522 #define CICR_SCC_SCC3 ((unsigned int)0x00200000) /* SCC3 @ SCCc */ 523 #define CICR_SCB_SCC2 ((unsigned int)0x00040000) /* SCC2 @ SCCb */ 524 #define CICR_SCA_SCC1 ((unsigned int)0x00000000) /* SCC1 @ SCCa */ 525 #define CICR_IRL_MASK ((unsigned int)0x0000e000) /* Core interrrupt */ 526 #define CICR_HP_MASK ((unsigned int)0x00001f00) /* Hi-pri int. */ 527 #define CICR_IEN ((unsigned int)0x00000080) /* Int. enable */ 528 #define CICR_SPS ((unsigned int)0x00000001) /* SCC Spread */ 529 529 #endif /* __CPM_8XX__ */ -
c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
rb7f5447b r0eef948f 243 243 * #define LOADED_BY_EPPCBUG 244 244 */ 245 #define LOADED_BY_EPPCBUG 246 #define EARLY_CONSOLE 245 247 /* 246 248 * Initialization code … … 276 278 bl bssclr 277 279 nop 278 280 #if defined(EARLY_CONSOLE) && defined(LOADED_BY_EPPCBUG) 281 EXTERN_PROC (serial_init) 282 bl PROC (serial_init) 283 #endif 279 284 lis r5,environ@ha 280 285 la r5,environ@l(r5) /* environp */
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