Changeset 0ed348f in rtems


Ignore:
Timestamp:
Dec 2, 2005, 8:45:57 PM (14 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
39941915
Parents:
d8ada5b
Message:

2005-12-02 Till Straumann <strauman@…>

  • shared/irq/irq_init.c, shared/openpic/openpic.h shared/openpic/openpic.c: The 8240's EPIC has a 'serial' mode of operation for multiplexing 16 interrupt lines. This introduces a pipeline delay which can cause spurious interrupts unless ending the interrupt cycle (EOI) is delayed accordingly.
Location:
c/src/lib/libbsp/powerpc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ChangeLog

    rd8ada5b r0ed348f  
     12005-12-02      Till Straumann <strauman@slac.stanford.edu>
     2        * shared/irq/irq_init.c, shared/openpic/openpic.h
     3        shared/openpic/openpic.c: The 8240's EPIC has a 'serial'
     4        mode of operation for multiplexing 16 interrupt lines.
     5        This introduces a pipeline delay which can cause
     6        spurious interrupts unless ending the interrupt cycle
     7        (EOI) is delayed accordingly.
     8
    192005-12-01      Till Straumann <strauman@slac.stanford.edu>
    210        * shared/vectors/vectors.h, shared/vectors/vectors.S,
  • c/src/lib/libbsp/powerpc/shared/irq/irq_init.c

    rd8ada5b r0ed348f  
    271271#endif
    272272  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
     273  /* Speed up the serial interface; if it is too slow then we might get spurious
     274   * interrupts:
     275   * After an ISR clears the interrupt condition at the source/device, the wire
     276   * remains asserted during the propagation delay introduced by the serial interface
     277   * (something really stupid). If the ISR returns while the wire is not released
     278   * yet, then a spurious interrupt happens.
     279   * The book says we should be careful if the serial clock is > 33MHz.
     280   * Empirically, it seems that running it at 33MHz is fast enough. Otherwise,
     281   * we should introduce a delay in openpic_eoi().
     282   * The maximal delay are 16 (serial) clock cycles. If the divisor is 8
     283   * [power-up default] then the lag is 2us [66MHz SDRAM clock; I assume this
     284   * is equal to the bus frequency].
     285   * FIXME: This should probably be a 8240-specific piece in 'openpic.c'
     286   */
     287  {
     288  uint32_t eicr_val, ratio;
     289    /* On the 8240 this is the EICR register */
     290    eicr_val = in_le32( &OpenPIC->Global.Global_Configuration1 ) & ~(7<<28);
     291    if ( (1<<27) & eicr_val ) {
     292      /* serial interface mode enabled */
     293
     294      /* round to nearest integer:
     295       *   round(Bus_freq/33000000) = floor( 2*(Bus_freq/33e6) + 1 ) / 2
     296       */
     297      ratio   = BSP_bus_frequency / 16500000 + 1;
     298      ratio >>= 2; /* EICR value is half actual divisor */
     299      if ( 0==ratio )
     300        ratio = 1;
     301      out_le32(&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28));
     302      /*  Delay in TB cycles (assuming TB runs at 1/4 of the bus frequency) */
     303      openpic_set_eoi_delay( 16 * (2*ratio) / 4 );
     304    }
     305  }
    273306#else
    274307#ifdef TRACE_IRQ_INIT 
  • c/src/lib/libbsp/powerpc/shared/openpic/openpic.c

    rd8ada5b r0ed348f  
    3939static unsigned int NumProcessors;
    4040static unsigned int NumSources;
     41
     42#if defined(mpc8240) || defined(mpc8245)
     43static unsigned int openpic_eoi_delay = 0;
     44#endif
    4145
    4246    /*
     
    313317{
    314318    check_arg_cpu(cpu);
     319#if defined(mpc8240) || defined(mpc8245)
     320    if ( openpic_eoi_delay )
     321        rtems_bsp_delay_in_bus_cycles(openpic_eoi_delay);
     322#endif
    315323    openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
    316324}
     325
     326#if defined(mpc8240) || defined(mpc8245)
     327void openpic_set_eoi_delay(unsigned tb_cycles)
     328{
     329    openpic_eoi_delay = tb_cycles;
     330}
     331#endif
    317332
    318333    /*
  • c/src/lib/libbsp/powerpc/shared/openpic/openpic.h

    rd8ada5b r0ed348f  
    4444#if defined(mpc8240) || defined(mpc8245)
    4545#define OPENPIC_MAX_SOURCES    (2048 - 16)
     46/* If the BSP uses the serial interrupt mode / 'multiplexer' then
     47 * EOI must be delayed by at least 16 SRAM_CLK cycles to avoid
     48 * spurious interrupts.
     49 * It is the BSP's responsibility to set up an appropriate delay
     50 * (in timebase-clock cycles) at init time.
     51 */
     52extern void openpic_set_eoi_delay(unsigned tb_cycles);
    4653#else
    4754#define OPENPIC_MAX_SOURCES     2048
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