Changeset 0ea3293 in rtems


Ignore:
Timestamp:
03/01/02 16:21:52 (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
cd6bec6
Parents:
bd1ecb0
Message:

2002-02-27 Greg Menke <gregory.menke@…>

  • start/start.S: Added kseg1 test to enable cache flush code
  • bsp_specs: Added -qnostartfile to disable including bsp's start.o
  • startup/bspstart.c: Made clear_cache actually work, tweaked cpu init to only turn on whats needed.
  • startup/gdb-support.c: Added calls to uart 2 for gdb stub I/O and a handy init function.
Location:
c/src/lib/libbsp/mips/genmongoosev
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • c/src/lib/libbsp/mips/genmongoosev/ChangeLog

    rbd1ecb0 r0ea3293  
    1 2001-02-27      Joel Sherrill <joel@OARcorp.com>
     12002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
    22
    3         * startup/Makefile.am: Added rtems-stub-glue.c to C_FILES.
     3        * start/start.S: Added kseg1 test to enable cache flush code
     4        * bsp_specs: Added -qnostartfile to disable including bsp's start.o
     5        * startup/bspstart.c: Made clear_cache actually work, tweaked cpu
     6        init to only turn on whats needed.
     7        * startup/gdb-support.c: Added calls to uart 2 for gdb stub I/O and
     8        a handy init function.
    49
    5102002-02-08      Joel Sherrill <joel@OARcorp.com>

  • c/src/lib/libbsp/mips/genmongoosev/README

    rbd1ecb0 r0ea3293  
    4545
    4646The default output of an RTEMS link is an image linked to run from
    47 80020000, but has had its LMA shifted up to BFC40000.  It is suitable
    48 for copying to S3 records or can be burned to ROMs in whatever manner
    49 the user desires.
     470x80020000.  It is suitable for copying to S3 records or can be burned
     48to ROMs in whatever manner the user desires.  If you want to locate the
     49image into ROM at some other address, use mips-rtems-objcopy to shift
     50the LMA.
    5051
    5152Operation
    … …  
    6869Before relocating the RTEMS image, the bsp startup routine attempts to
    6970configure the processor into a rational state.  During this process,
    70 status characters are emitted at 19200N81 baud on UART port 0.
     71status characters are emitted at 19200N81 on UART port 0.
     72
     73The default link script simply places the image at 0x8002000 with
     74LMA=VMA, which is conviently located in RAM on our board.  You should
     75probably consider creating your own linkcmds, putting things where you
     76want and supply it as above. 
     77
     78The Mongoose V has a somewhat restricted cache configuration model; you
     79can only flush it if the code which does so executes within noncached
     80memory, in our case, code in kseg1.  If you do so from elsewhere the
     81code will appear to lock up, this is caused by the cache clearing
     82routine making the instruction fetch always return 0, or nop- leaving
     83the processor in an endless loop.  The default start.S code detects if
     84its booting from outside kseg1, it which case it disables the cache
     85flush code.  This means you cannot flush the cache with the bsp's
     86functions if you boot your program from outside kseg1.  A more subtle
     87issue is the bsp keeps a pointer to the location in kseg1 where the
     88bsp's cache flush code resides.  This is advantageous because you can
     89relocate the system anywhere and still control the cache, but might
     90cause trouble if the boot image becomes inaccessible.  If this is
     91possible, you should probably consider rolling your own cache control &
     92disabling the bsp's.
     93
     94As stated above, if you boot from outside kseg1, the bsp disables the
     95cache flush routines.  This is not desirable in the long run because the
     96Mongoose V remote debugger stub assumes it can flush caches when exiting
     97an exception so it might not be able to update code/data properly,
     98though it should still nominally function.  However, if you're not using
     99the remote debugger & don't care about flushing caches, then everything
     100should run just fine.
     101
     102Our approach has to been locate ROM in kseg1, link the code for VMA in
     103RAM and relocate the LMA up into kseg1 ROM.  Since the start.S code is
     104position-independent, it will relocate the entire app down to the VMA
     105region before starting things up with everything in its proper place.
     106The cache clear code runs before relocation, so executes from ROM &
     107things work.
     108
     109You can prevent including the default start.S by adding;
     110
     111-qnostartfile
     112
     113to the link command line in addition to the "nolinkcmds" options above.
     114Be sure to supply your replacement start.o.
     115
    71116
    72117
    … …  
    85130
    86131
    87 Status
    88 ======
     132Debugging
     133=========
    89134
     135After getting Joel's initial port of the gdb stub to the Mongoose bsp, I
     136worked up & tested this stub on our R3000 board.  It seems to work OK.
     137Our MIPS has 2 serial ports, the first being dedicated to the console, I
     138chose to arrange the 2nd one for the remote gdb protocol.  While this
     139solution is somewhat specific to our board & bsp, I think the technique
     140is quite generalizable.
     141
     142The following is a code snippet to be included in the user program;
     143
     144/***********************************************/
     145
     146extern int mg5rdbgOpenGDBuart(int);
     147extern void mg5rdbgCloseGDBuart(void);
     148
     149
     150void setupgdb(void)
     151{
     152   printf("Configuring remote GDB stub...\n");
     153
     154   /* initialize remote gdb support */
     155   if( mg5rdbgOpenGDBuart(-1) != RTEMS_SUCCESSFUL )
     156   {
     157      printf("Remote GDB stub is disabled.\n\n");
     158   }
     159}
     160
     161/***********************************************/
     162
     163It allows the program to decide if it wants gdb to be ready to pick up
     164exceptions or not.  The 2 extern functions are located in the MongooseV
     165bsp inside gdb-support.c.  They configure & initialize the 2nd serial
     166port & invoke the vector initialization routine located in cpu_asm.
     167Note, we call directly down into the MongooseV UART driver- its quite
     168unfriendly to TERMIO.  I chose this approach because I wanted to
     169minimize dependence on the I/O subsystems because they might be in a
     170state just short of collapsing if the program had done something bad to
     171cause the exception.
     172
     173If user code leaves the 2nd port alone, then things will work out OK.
     174
     175Greg Menke
     1762/27/2002
     177
     178============================================================================
     179

  • c/src/lib/libbsp/mips/genmongoosev/bsp_specs

    rbd1ecb0 r0ea3293  
    1616*startfile:
    1717%{!qrtems: %(old_startfile)} %{qrtems: \
    18 %{!qrtems_debug: start.o%s} \
    19 %{qrtems_debug: start_g.o%s}}
     18%{!qnostartfile: %{!qrtems_debug: start.o%s} \
     19                 %{qrtems_debug: start_g.o%s}}}
    2020
    2121*link:

  • c/src/lib/libbsp/mips/genmongoosev/start/start.S

    rbd1ecb0 r0ea3293  
    4949
    5050
    51 #ifdef HACKED_PMON
    52    #define PMON_UTIL_ROUTINES      0xbfc00200
    53    #define UTIL_WARMSTART_VECTOR   21*4
    54    #define UTIL_CPUINIT_VECTOR     22*4
    55    #define UTIL_CONFIGUART_VECTOR  23*4
    56    #define UTIL_PUTCHROM_VECTOR    24*4
    57 #endif
    58 
    59 
    6051/*
    6152** defined by linkcmds, pointing to the start of the relocation target
    … …  
    8576_start:
    8677   .set    noreorder
    87    move    k1,ra       /* save ra so we can optionally return to caller */
    8878   $LF1 = . + 8
    8979
    … …  
    132122   nop
    133123
     124
     125
     126   /*
     127   ** Print 'b'.  Show that we started.
     128   */
     129   move   t2,a1
     130   and    t2,0xffff0000
     131   li     a0,'b'
     132   la     t0,putch_rom
     133   and    t0,0x0000ffff
     134   or     t0,t2
     135   jal    t0
     136   nop
     137       
     138
     139                       
     140               
     141
     142   li   k0,0
     143   li   k1,0
     144       
     145   move t1,a1
     146   nop
     147   li   t2,0xa0000000   /* lower limit of kseg1 */
     148   li   t3,0xbfffffff   /* upper limit of kseg1 */
     149
     150   subu t0,t1,t2
     151   srl  t0,31           /* shift high bit down to bit 0 */
     152   bnez t0,1f           /* booting from below kseg1 */
     153       
     154   subu t0,t3,t1
     155   srl  t0,31           /* shift high bit down to bit 0 */
     156   bnez t0,1f           /* booting from above kseg1 */
     157
     158               
     159       
    134160   /*
    135161   ** Call IcacheFlush. Masking used to call EEPROM address of IcacheFlush.  Label is RAM label.
    … …  
    140166   and    t0,0x0000ffff
    141167   or     t0,t2
     168   move   k0,t0         /* save cache flush in-prom address */
    142169   jal    t0
    143170   nop
    … …  
    178205   and    t0,0x0000ffff
    179206   or     t0,t2
    180    jal    t0
    181    nop
    182 
    183 
     207   move   k1,t0         /* save cache flush in-prom address */
     208   jal    t0
     209   nop
     210
     211
     2121:     
    184213   /*
    185214   ** Print ' RTEMS  b'.  Show that we are booting.
    … …  
    278307   and    t0,0x0000ffff
    279308   or     t0,t2
    280    jal    t0
    281    nop
    282 
    283    la  a3, _edata
     309   jal    t0
     310   nop
     311
     312   la           a3, _edata
    284313relocate:
    285    lw  t0, (a1)            /* load from EEPROM */
    286    addu    a1, 4
    287    sw      t0, (a2)        /* store to RAM */
    288    addu    a2, 4
    289    bne a2, a3, relocate    /* copied all the way to edata? */
     314   lw           t0, (a1)            /* load from EEPROM */
     315   addu         a1, 4
     316   sw           t0, (a2)            /* store to RAM */
     317   addu         a2, 4
     318   bne          a2, a3, relocate    /* copied all the way to edata? */
    290319   nop
    291320
    … …  
    318347   ** Print 'S'.  Already in RAM no need to reference EEPROM address.
    319348   */
    320    li a0,'S'
    321    jal putch_rom
    322    nop
    323 
    324    la  gp, _gp         /* set the global data pointer */
     349   li   a0,'S'
     350   jal  putch_rom
     351   nop
     352
     353   la   gp, _gp                 /* set the global data pointer */
    325354   .end _start_in_ram
    326355
    … …  
    342371   nop
    343372
    344    la v0, _fbss
    345    la v1, _end
     373   la           v0, _fbss
     374   la           v1, _end
    3463753:
    347    sw zero,0(v0)
    348    bltu v0,v1,3b
    349    addiu v0,v0,4               /* executed in delay slot */
     376   sw           zero,0(v0)
     377   bltu         v0,v1,3b
     378   addiu        v0,v0,4               /* executed in delay slot */
    350379
    351380   la  t0, _stack_init         /* initialize stack so we */
    … …  
    369398   ** Print 'Z'.  Finished zeroing bss.
    370399   */
    371    li a0,'Z'
    372    jal putch_rom
     400   li   a0,'Z'
     401   jal  putch_rom
    373402   nop
    374403
    … …  
    388417   ** Print 'i'.  Starting to initialize RTEMS.
    389418   */
    390    li a0, 'i'
    391    jal putch_rom
    392    nop
    393 
    394    move    a0,zero         /* set argc to 0 */
    395    jal boot_card           /* call the program start function */
     419   li           a0, 'i'
     420   jal          putch_rom
     421   nop
     422
     423
     424   /*
     425   ** Save the boot-time addresses of the I & D cache flush routines.
     426   ** Note, if we're running from RAM, we cannot manipulate the cache
     427   ** so we just disable the cache flush functions.
     428   */
     429   la           a0,_promIcache
     430   sw           k0,0(a0)
     431   nop
     432       
     433   la           a0,_promDcache
     434   sw           k1,0(a0)
     435   nop
     436
     437   move         a0,zero         /* set argc to 0 */
     438   jal          boot_card           /* call the program start function */
    396439   nop
    397440
    … …  
    749792
    750793
     794
     795
     796
     797       
     798
     799
     800       
     801/**********************************************************************
     802**
     803** Keep the boot-time address of the I & D cache reset code for
     804** later on.  If we need to clear the I/D caches, we <must> run from
     805** non-cached memory.  This means the relocated versions are useless,
     806** thankfully they are quite small.
     807*/
     808       
     809_promIcache:    .word 0
     810_promDcache:    .word 0
     811
     812               
     813
     814        .globl promCopyIcacheFlush
     815        .ent promCopyIcacheFlush
     816        .set noreorder
     817promCopyIcacheFlush:   
     818        move    a0,ra
     819       
     820        la      t1,_promIcache
     821        lw      t0,0(t1)
     822        nop
     823        beqz    t0,1f
     824       
     825        jal     t0
     826        nop
     827
     8281:      j       a0
     829        nop
     830        .set reorder
     831        .end promCopyIcacheFlush
     832       
     833
     834       
     835        .globl promCopyDcacheFlush
     836        .ent promCopyDcacheFlush
     837        .set noreorder
     838promCopyDcacheFlush:   
     839        move    a0,ra
     840       
     841        la      t1,_promDcache
     842        lw      t0,0(t1)
     843        nop
     844        beqz    t0,1f
     845       
     846        jal     t0
     847        nop
     848
     8491:      j       a0
     850        nop
     851        .set reorder
     852        .end promCopyDcacheFlush
     853                       
     854       
     855               
     856
     857       
    751858/*******************************************************************************
    752859** Function Name:   IcacheFlush
    … …  
    754861*/
    755862
    756      .globl IcacheFlush
    757863     .ent IcacheFlush
     864     .set noreorder
    758865IcacheFlush:
    759866
    … …  
    763870     li        t0, M_BIU
    764871     lw        t1, 0(t0)
    765 
    766      .set noreorder
    767872
    768873     # Isolate I cache
    … …  
    779884icache_write:
    780885     sw        zero, 0(t8)          /* Store zero to memory addres in t8 */
    781      addu      t8, 4                /* Increment t8 addres by 4 */
     886     addu      t8, 4                /* Increment t8 address by 4 */
    782887     bltu      t8, t9, icache_write /* check to see if we are done */
    783888     nop
    … …  
    799904*/
    800905
    801      .globl DcacheFlush
     906
    802907     .ent DcacheFlush
     908     .set noreorder
    803909DcacheFlush:
    804910
    805911     # isolate icache
    806      .set noreorder
    807912     mfc0      t3,C0_SR
    808913     nop

  • c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c

    rbd1ecb0 r0ea3293  
    2525#include <rtems/libcsupport.h>
    2626#include <libcpu/mongoose-v.h>
     27
    2728
    2829
    … …  
    8889void bsp_start( void )
    8990{
    90   extern int WorkspaceBase;
    91   extern void mips_install_isr_entries();
     91   extern void _sys_exit(int);
     92   extern int WorkspaceBase;
     93   extern void mips_install_isr_entries();
     94   extern void mips_gdb_stub_install(void);
     95   
     96   /* Configure Number of Register Caches */
    9297
    93   /* Configure Number of Register Caches */
     98   Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
     99   Cpu_table.postdriver_hook = bsp_postdriver_hook;
     100   Cpu_table.interrupt_stack_size = 4096;
    94101
    95   Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
    96   Cpu_table.postdriver_hook = bsp_postdriver_hook;
    97   Cpu_table.interrupt_stack_size = 4096;
     102   /* HACK -- tied to value linkcmds */
     103   if ( BSP_Configuration.work_space_size > (4096*1024) )
     104      _sys_exit( 1 );
    98105
    99   /* HACK -- tied to value linkcmds */
    100   if ( BSP_Configuration.work_space_size > (4096*1024) )
    101      _sys_exit( 1 );
     106   BSP_Configuration.work_space_start = (void *) &WorkspaceBase;
    102107
    103   BSP_Configuration.work_space_start = (void *) &WorkspaceBase;
     108   /* mask off any interrupts */
     109   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 );
    104110
    105   /* mask off any interrupts */
    106   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 );
     111   /* reset the config register & clear any pending peripheral interrupts */
     112   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 );
     113   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, MONGOOSEV_UART_CMD_RESET_BOTH_PORTS );
     114   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 );
    107115
    108   MONGOOSEV_WRITE( MONGOOSEV_WATCHDOG, 0xA0 );
     116   /* reset both timers */
     117   MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff );
     118   MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
    109119
    110   /* reset the config register & clear any pending peripheral interrupts */
    111   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 );
    112   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, MONGOOSEV_UART_CMD_RESET_BOTH_PORTS );
    113   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_COMMAND_REGISTER, 0 );
     120   MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff );
     121   MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
    114122
    115   /* reset both timers */
    116   MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff );
    117   MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER1_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
     123   /* clear any pending interrupts */
     124   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, 0xffffffff );
    118125
    119   MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER, 0xffffffff );
    120   MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
     126   /* clear any writable bits in the cause register */
     127   mips_set_cause( 0 );
    121128
    122   /* clear any pending interrupts */
    123   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, 0xffffffff );
     129   /* set interrupt mask, but globally off. */
    124130
    125   /* clear any writable bits in the cause register */
    126   mips_set_cause( 0 );
     131   /*
     132   **  Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit  9 | Bit  8 |
     133   **  periph | unused |  FPU   | unused | timer2 | timer1 | swint1 | swint2 |
     134   **  extern |        |        |        |        |        |        |        |
     135   **
     136   **    1        0        1        0        0        1        0        0
     137   **
     138   **    0x8C00   Enable only internal Mongoose V timers.
     139   **    0xA400   Enable Peripherial ints, FPU and timer1
     140   **    0x0400   Timer1 only
     141   */
    127142
    128   /* set interrupt mask, but globally off. */
     143   /* mips_set_sr( (SR_CU0 | SR_CU1 | 0xA400) ); */
    129144
    130   /*
    131   **  Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit  9 | Bit  8 |
    132   **  periph | unused |  FPU   | unused | timer2 | timer1 | swint1 | swint2 |
    133   **  extern |        |        |        |        |        |        |        |
    134   **
    135   **    1        0        1        0        0        1        0        0
    136   **
    137   **    0x8C00   Enable only internal Mongoose V timers.
    138   **    0xA400   Enable Peripherial ints, FPU and timer1
    139   */
     145   /* to start up, only enable coprocessor 0 & timer int. per-task
     146   ** processor settings will be applied as they are created, this
     147   ** is just to configure the processor for startup
     148   */
     149   mips_set_sr( (SR_CU0 | 0x400) );
    140150
    141   mips_set_sr( (SR_CU0 | SR_CU1 | 0xA400) );
    142 
    143   mips_install_isr_entries();
     151   mips_install_isr_entries();
    144152}
    145153
    146154
    147 void clear_cache( void *address, size_t n )
     155
     156
     157void clear_cache( void )
    148158{
     159   extern void promCopyIcacheFlush(void);       /* from start.S */
     160   extern void promCopyDcacheFlush(void);
     161
     162   promCopyIcacheFlush();
     163   promCopyDcacheFlush();
    149164}
    150165
    151 /* Structure filled in by get_mem_info.  Only the size field is
    152    actually used (to clear bss), so the others aren't even filled in.  */
     166
     167
     168
     169/*
     170 
     171//Structure filled in by get_mem_info.
     172
    153173
    154174struct s_mem
    … …  
    160180
    161181
    162 
    163182extern unsigned32 _RamSize;
    164183
    … …  
    166185{
    167186   mem->size = (unsigned32)&_RamSize;
     187   mem->icsize = MONGOOSEV_IC_SIZE;
     188   mem->dcsize = MONGOOSEV_DC_SIZE;
    168189}
    169190
     191*/
     192

  • c/src/lib/libbsp/mips/genmongoosev/startup/gdb-support.c

    rbd1ecb0 r0ea3293  
    1414#include <rtems.h>
    1515#include <rtems/bspIo.h>
     16#include <libcpu/mongoose-v.h>
     17
     18#include <rtems/libio.h>
     19
     20
     21
     22/*
     23
     24We're going to call right down into the uart driver because we're
     25operating within an exception.  if things are broken because something
     26bad happened, this may be our last chance to debug before RTEMS goes
     27mad, so we won't rely on the I/O subsystem to be operating.  This is a
     28little messy, but at least we're not talking right to the hardware.
     29
     30*/
     31
     32extern int mg5uart_set_attributes(int minor,const struct termios *t);
     33extern int mg5uart_open(int major,int minor, void *arg);
     34extern int mg5uart_close(int major,int minor, void *arg);
     35extern void mg5uart_write_polled(int minor, char c );
     36extern int mg5uart_inbyte_nonblocking_polled(int minor);
     37
     38
     39extern void mips_gdb_stub_install(void);
     40
     41
     42static int debugUartEnabled = 0;
     43
     44
     45
     46int mg5rdbgOpenGDBuart(int breakoninit)
     47{
     48   struct termios t;
     49   memset(&t,0,sizeof(struct termios));
     50
     51   if( mg5uart_open(0,1,NULL) != RTEMS_SUCCESSFUL )
     52   {
     53      printf("gdbstub: Failed to open UART port 2\n");
     54      return -1;
     55   }
     56
     57   t.c_cflag |= B19200;
     58   t.c_cflag |= CS8;
     59   if( mg5uart_set_attributes(1,&t) != 0 )
     60   {
     61      printf("gdbstub: Failed to configure UART 2 for 19200N82\n");
     62      return -1;
     63   }
     64
     65   debugUartEnabled  = -1;
     66
     67   /* set up vectoring for gdb */
     68   mips_gdb_stub_install();
     69
     70   printf("gdbstub: Remote GDB stub listening on UART 2 at 19200N82\n");
     71
     72   if( breakoninit )
     73   {
     74      /*
     75         break to gdb.  We'll wait there for the operator to get their gdb
     76         going, then they can 'continue' or do whatever.
     77      */
     78      mips_break(0);
     79   }
     80
     81   printf("gdbstub: User code running\n");
     82
     83   return RTEMS_SUCCESSFUL;
     84}
     85
     86
     87void mg5rdbgCloseGDBuart(void)
     88{
     89   mg5uart_close(0,1,NULL);
     90   debugUartEnabled  = 0;
     91}
     92
     93
    1694
    1795
    1896char getDebugChar (void)
    1997{
    20   return 0;
     98   if( debugUartEnabled )
     99   {
     100      int rv;
     101
     102      while( (rv = mg5uart_inbyte_nonblocking_polled(1)) < 0 );
     103      return (char)rv;
     104   }
     105
     106   return 0;
    21107}
     108
    22109
    23110void putDebugChar (char c)
    24111{
    25   /* big hack */
    26   printk( "%c" );
     112   if( debugUartEnabled )
     113      return mg5uart_write_polled(1,c);
    27114}
    28115

  • c/src/lib/libbsp/mips/genmongoosev/startup/linkcmds

    rbd1ecb0 r0ea3293  
    2222MEMORY
    2323{
    24    romstore : ORIGIN = 0xbfc40000, LENGTH = 4M
    2524   ram      : ORIGIN = 0x80020000, LENGTH = 4M
    2625}
    … …  
    4342      PROVIDE (__runtime_reloc_stop = .);
    4443      *(.fini)
    45     } >ram  AT>romstore
     44      *(.gcc_except_table)
     45    } >ram 
    4646
    4747  .ctors    :
    … …  
    6767    KEEP (*(SORT(.ctors.*)))
    6868    KEEP (*(.ctors))
    69   } >ram  AT>romstore
     69  } >ram 
    7070
    7171  .dtors    :
    … …  
    7878    etext  =  .;
    7979    _etext  =  .;
    80   } >ram  AT>romstore
     80  } >ram 
    8181
    82 /*    . = .; */
     82
    8383
    8484  .rdata :
    … …  
    8888    *(.rodata.*)
    8989    *(.gnu.linkonce.r*)
    90   } >ram  AT>romstore
     90  } >ram 
    9191
    9292  .data :
    … …  
    9797    *(.data.*)
    9898    *(.gnu.linkonce.d*)
    99   } >ram  AT>romstore
     99  } >ram 
    100100
    101101
    … …  
    107107    __global = _gp;
    108108    *(.lit8)
    109   } >ram  AT>romstore
     109  } >ram 
    110110
    111111  .lit4 :
    112112  {
    113113    *(.lit4)
    114   } >ram  AT>romstore
     114  } >ram 
    115115
    116116  .sdata :   
    … …  
    119119    *(.sdata.*)
    120120    *(.gnu.linkonce.s*)
    121   } >ram  AT>romstore
     121  } >ram 
    122122
    123123  .sbss :
    124124  {
    125   . = ALIGN(4);
    126125   edata  =  .;
    127126   _edata  =  .;
    … …  
    129128    *(.sbss)
    130129    *(.scommon)
    131   } >ram  AT>romstore
     130  } >ram 
    132131
    133132
    … …  
    149148    end = .;
    150149    _end = .;
    151   } >ram  AT>romstore
     150  } >ram 
    152151
    153152
    … …  
    159158
    160159  /* DWARF 1 */
    161   .debug          0 : { *(.debug) } AT>romstore
    162   .line           0 : { *(.line) } AT>romstore
     160  .debug          0 : { *(.debug) }
     161  .line           0 : { *(.line) }
    163162
    164163  /* GNU DWARF 1 extensions */
    165   .debug_srcinfo  0 : { *(.debug_srcinfo) } AT>romstore
    166   .debug_sfnames  0 : { *(.debug_sfnames) } AT>romstore
     164  .debug_srcinfo  0 : { *(.debug_srcinfo) }
     165  .debug_sfnames  0 : { *(.debug_sfnames) }
    167166
    168167  /* DWARF 1.1 and DWARF 2 */
    169   .debug_aranges  0 : { *(.debug_aranges) } AT>romstore
    170   .debug_pubnames 0 : { *(.debug_pubnames) } AT>romstore
     168  .debug_aranges  0 : { *(.debug_aranges) }
     169  .debug_pubnames 0 : { *(.debug_pubnames) }
    171170
    172171  /* DWARF 2 */
    173   .debug_info     0 : { *(.debug_info) }    AT>romstore
    174   .debug_abbrev   0 : { *(.debug_abbrev) }  AT>romstore
    175   .debug_line     0 : { *(.debug_line) }    AT>romstore
    176   .debug_frame    0 : { *(.debug_frame)}    AT>romstore
    177   .debug_str      0 : { *(.debug_str) }     AT>romstore
    178   .debug_loc      0 : { *(.debug_loc) }     AT>romstore
    179   .debug_macinfo  0 : { *(.debug_macinfo) } AT>romstore
     172  .debug_info     0 : { *(.debug_info) }   
     173  .debug_abbrev   0 : { *(.debug_abbrev) } 
     174  .debug_line     0 : { *(.debug_line) }   
     175  .debug_frame    0 : { *(.debug_frame)}   
     176  .debug_str      0 : { *(.debug_str) }     
     177  .debug_loc      0 : { *(.debug_loc) }     
     178  .debug_macinfo  0 : { *(.debug_macinfo) }
    180179
    181180  /* SGI/MIPS DWARF 2 extensions */
    182   .debug_weaknames 0 : { *(.debug_weaknames) } AT>romstore
    183   .debug_funcnames 0 : { *(.debug_funcnames) } AT>romstore
    184   .debug_typenames 0 : { *(.debug_typenames) } AT>romstore
    185   .debug_varnames  0 : { *(.debug_varnames) }  AT>romstore
     181  .debug_weaknames 0 : { *(.debug_weaknames) }
     182  .debug_funcnames 0 : { *(.debug_funcnames) }
     183  .debug_typenames 0 : { *(.debug_typenames) }
     184  .debug_varnames  0 : { *(.debug_varnames) } 
    186185}
Note: See TracChangeset for help on using the changeset viewer.