Changeset 0e4e9dd4 in rtems


Ignore:
Timestamp:
03/15/23 18:15:51 (11 months ago)
Author:
Karel Gardas <karel@…>
Branches:
master
Children:
fb0eb31
Parents:
1425735
git-author:
Karel Gardas <karel@…> (03/15/23 18:15:51)
git-committer:
Karel Gardas <karel@…> (07/14/23 10:38:14)
Message:

score/arm: improve printed exception information for Cortex-Mx CPUs

Sponsored-By: Precidata

Location:
cpukit/score/cpu/arm
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/arm-exception-frame-print.c

    r1425735 r0e4e9dd4  
    4242
    4343#include <rtems/score/cpu.h>
     44#if defined(ARM_MULTILIB_ARCH_V7M)
     45#include <rtems/score/armv7m.h>
     46#endif
    4447#include <rtems/bspIo.h>
    4548
    4649static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )
    4750{
    48 #ifdef ARM_MULTILIB_VFP_D32
     51#ifdef ARM_MULTILIB_VFP
    4952  if ( vfp_context != NULL ) {
    5053    const uint64_t *dx = &vfp_context->register_d0;
     
    5760    );
    5861
    59     for ( i = 0; i < 32; ++i ) {
     62#if defined(ARM_MULTILIB_VFP_D32)
     63    int regcount = 32;
     64#elif defined(ARM_MULTILIB_VFP_D16)
     65    int regcount = 16;
     66#else
     67    int regcount = 0;
     68#endif
     69    for ( i = 0; i < regcount; ++i ) {
    6070      uint32_t low = (uint32_t) dx[i];
    6171      uint32_t high = (uint32_t) (dx[i] >> 32);
     
    6777}
    6878
     79static void _ARM_Cortex_M_fault_info_print( void )
     80{
     81#if defined(ARM_MULTILIB_ARCH_V7M)
     82  /*
     83   * prints content of additional debugging registers
     84   * available on Cortex-Mx where x > 0 cores.
     85   */
     86  uint32_t cfsr = _ARMV7M_SCB->cfsr;
     87  uint8_t mmfsr = ARMV7M_SCB_CFSR_MMFSR_GET( cfsr );
     88  uint8_t bfsr = ( ARMV7M_SCB_CFSR_BFSR_GET( cfsr ) >> 8 );
     89  uint16_t ufsr = ( ARMV7M_SCB_CFSR_UFSR_GET( cfsr ) >> 16 );
     90  uint32_t hfsr = _ARMV7M_SCB->hfsr;
     91  if ( mmfsr > 0 ) {
     92    printk( "MMFSR= 0x%08" PRIx32 " (memory fault)\n", mmfsr );
     93    if ( ( mmfsr & 0x1 ) != 0 ) {
     94      printk( "  IACCVIOL   : 1  (instruction access violation)\n" );
     95    }
     96    if ( ( mmfsr & 0x2 ) != 0 ) {
     97      printk( "  DACCVIOL   : 1  (data access violation)\n" );
     98    }
     99    if ( (mmfsr & 0x8 ) != 0 ) {
     100      printk(
     101        "  MUNSTKERR  : 1  (fault on unstacking on exception return)\n"
     102      );
     103    }
     104    if ( ( mmfsr & 0x10 ) != 0 ) {
     105      printk( "  MSTKERR    : 1  (fault on stacking on exception entry)\n" );
     106    }
     107    if ( (mmfsr & 0x20 ) != 0 ) {
     108      printk( "  MLSPERR    : 1  (fault during lazy FP stack preservation)\n" );
     109    }
     110    if ( (mmfsr & 0x80 ) != 0 ) {
     111      printk(
     112        "  MMFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",
     113        _ARMV7M_SCB->mmfar
     114      );
     115    }
     116    else {
     117      printk( "  MMFARVALID : 0  (undetermined error address)\n" );
     118    }
     119  }
     120  if ( bfsr > 0 ) {
     121    printk( "BFSR = 0x%08" PRIx32 " (bus fault)\n", bfsr );
     122    if ( ( bfsr & 0x1 ) != 0 ) {
     123      printk( "  IBUSERR    : 1  (instruction fetch error)\n" );
     124    }
     125    if ( (bfsr & 0x2 ) != 0 ) {
     126      printk(
     127        "  PRECISERR  : 1  (data bus error with known exact location)\n"
     128      );
     129    }
     130    if ( ( bfsr & 0x4) != 0 ) {
     131      printk(
     132        "  IMPRECISERR: 1  (data bus error without known exact location)\n"
     133      );
     134    }
     135    if ( (bfsr & 0x8 ) != 0 ) {
     136      printk(
     137        "  UNSTKERR   : 1  (fault on unstacking on exception return)\n"
     138      );
     139    }
     140    if ( ( bfsr & 0x10 ) != 0 ) {
     141      printk( "  STKERR     : 1  (fault on stacking on exception entry)\n" );
     142    }
     143    if ( ( bfsr & 0x20 ) != 0 ) {
     144      printk( "  LSPERR     : 1  (fault during lazy FP stack preservation)\n" );
     145    }
     146    if ( (bfsr & 0x80 ) != 0 ) {
     147      printk(
     148        "  BFARVALID  : 1 -> 0x%08" PRIx32 "  (error address)\n",
     149        _ARMV7M_SCB->bfar
     150      );
     151    }
     152    else {
     153      printk( "  BFARVALID  : 0  (undetermined error address)\n" );
     154    }
     155  }
     156  if ( ufsr > 0 ) {
     157    printk( "UFSR = 0x%08" PRIx32 " (usage fault)\n", ufsr);
     158    if ( (ufsr & 0x1 ) != 0 ) {
     159      printk( "  UNDEFINSTR : 1  (undefined instruction issued)\n");
     160    }
     161    if ( (ufsr & 0x2 ) != 0 ) {
     162      printk(
     163        "  INVSTATE   : 1"
     164        "  (invalid instruction state"
     165        " (Thumb not set in EPSR or invalid IT state in EPSR))\n"
     166      );
     167    }
     168    if ( (ufsr & 0x4 ) != 0 ) {
     169      printk( "  INVPC      : 1  (integrity check failure on EXC_RETURN)\n" );
     170    }
     171    if ( (ufsr & 0x8 ) != 0 ) {
     172      printk(
     173        "  NOCP       : 1"
     174        "  (coprocessor instruction issued"
     175        " but coprocessor disabled or non existent)\n"
     176      );
     177    }
     178    if ( ( ufsr & 0x100) != 0 ) {
     179      printk( "  UNALIGNED  : 1  (unaligned access operation occurred)\n" );
     180    }
     181    if ( ( ufsr & 0x200) != 0 ) {
     182      printk( "  DIVBYZERO  : 1  (division by zero)" );
     183    }
     184  }
     185  if ( (hfsr & (
     186    ARMV7M_SCB_HFSR_VECTTBL_MASK
     187    | ARMV7M_SCB_HFSR_DEBUGEVT_MASK
     188    | ARMV7M_SCB_HFSR_FORCED_MASK
     189    ) ) != 0 ) {
     190    printk( "HFSR = 0x%08" PRIx32 " (hard fault)\n", hfsr );
     191    if ( (hfsr & ARMV7M_SCB_HFSR_VECTTBL_MASK ) != 0 ) {
     192      printk(
     193        "  VECTTBL    : 1  (error in address located in vector table)\n"
     194      );
     195    }
     196    if ( (hfsr & ARMV7M_SCB_HFSR_FORCED_MASK ) != 0 ) {
     197      printk(
     198        "  FORCED     : 1  (configurable fault escalated to hard fault)\n"
     199      );
     200    }
     201    if ( (hfsr & ARMV7M_SCB_HFSR_DEBUGEVT_MASK ) != 0 ) {
     202      printk(
     203        "  DEBUGEVT   : 1  (debug event occurred with debug system disabled)\n"
     204      );
     205    }
     206  }
     207#endif
     208}
    69209void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
    70210{
     
    110250
    111251  _ARM_VFP_context_print( frame->vfp_context );
     252  _ARM_Cortex_M_fault_info_print();
    112253}
  • cpukit/score/cpu/arm/include/rtems/score/armv7m.h

    r1425735 r0e4e9dd4  
    160160  uint32_t shcsr;
    161161
     162#define ARMV7M_SCB_CFSR_MMFSR_MASK 0xff
     163#define ARMV7M_SCB_CFSR_MMFSR_GET(n) (n & ARMV7M_SCB_CFSR_MMFSR_MASK)
     164#define ARMV7M_SCB_CFSR_BFSR_MASK 0xff00
     165#define ARMV7M_SCB_CFSR_BFSR_GET(n) (n & ARMV7M_SCB_CFSR_BFSR_MASK)
     166#define ARMV7M_SCB_CFSR_UFSR_MASK 0xffff0000
     167#define ARMV7M_SCB_CFSR_UFSR_GET(n) (n & ARMV7M_SCB_CFSR_UFSR_MASK)
    162168  uint32_t cfsr;
     169
     170#define ARMV7M_SCB_HFSR_VECTTBL_MASK 0x2
     171#define ARMV7M_SCB_HFSR_FORCED_MASK (1U << 30)
     172#define ARMV7M_SCB_HFSR_DEBUGEVT_MASK (1U << 31)
    163173  uint32_t hfsr;
     174
    164175  uint32_t dfsr;
    165176  uint32_t mmfar;
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