Changeset 0df8d7f2 in rtems


Ignore:
Timestamp:
Feb 10, 2014, 11:21:24 AM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
62c5c4a5
Parents:
069e10c3
git-author:
Sebastian Huber <sebastian.huber@…> (02/10/14 11:21:24)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/10/14 15:58:03)
Message:

bsps/arm: Use Global Timer for Cortex-A9 MPCore

Use the Global Timer for the Cortex-A9 MPCore clock driver instead of
the Private Timer. This enables a consistent nanoseconds since last
context switch value across all processors.

Location:
c/src/lib/libbsp/arm
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h

    r069e10c3 r0df8d7f2  
    4646#define BSP_ARM_GIC_CPUIF_BASE 0x1f000100
    4747
     48#define BSP_ARM_A9MPCORE_GT_BASE 0x1f000200
     49
    4850#define BSP_ARM_A9MPCORE_PT_BASE 0x1f000600
    4951
  • c/src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c

    r069e10c3 r0df8d7f2  
    11/*
    2  * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    1818#include <bsp/arm-a9mpcore-clock.h>
    1919
    20 #define A9MPCORE_PT ((volatile a9mpcore_pt *) BSP_ARM_A9MPCORE_PT_BASE)
     20#define A9MPCORE_GT ((volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE)
    2121
    2222static uint64_t a9mpcore_clock_last_tick_k;
     
    3333static void a9mpcore_clock_at_tick(void)
    3434{
    35   volatile a9mpcore_pt *pt = A9MPCORE_PT;
     35  volatile a9mpcore_gt *gt = A9MPCORE_GT;
    3636
    37   pt->irqst = A9MPCORE_PT_IRQST_EFLG;
     37  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
    3838}
    3939
     
    4343
    4444  sc = rtems_interrupt_handler_install(
    45     A9MPCORE_IRQ_PT,
     45    A9MPCORE_IRQ_GT,
    4646    "Clock",
    4747    RTEMS_INTERRUPT_UNIQUE,
     
    5757}
    5858
     59static uint64_t a9mpcore_clock_get_counter(volatile a9mpcore_gt *gt)
     60{
     61  uint32_t cl;
     62  uint32_t cu1;
     63  uint32_t cu2;
     64
     65  do {
     66    cu1 = gt->cntrupper;
     67    cl = gt->cntrlower;
     68    cu2 = gt->cntrupper;
     69  } while (cu1 != cu2);
     70
     71  return ((uint64_t) cu2 << 32) | cl;
     72}
     73
    5974static void a9mpcore_clock_initialize(void)
    6075{
    61   volatile a9mpcore_pt *pt = A9MPCORE_PT;
    62   uint64_t periphclk = (uint64_t) a9mpcore_clock_periphclk();
    63   uint64_t interval = (periphclk
    64     * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000;
     76  volatile a9mpcore_gt *gt = A9MPCORE_GT;
     77  uint64_t periphclk = a9mpcore_clock_periphclk();
     78  uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
     79  uint32_t interval = (uint32_t) ((periphclk * us_per_tick) / 1000000);
     80  uint64_t cmpval;
    6581
    66   a9mpcore_clock_last_tick_k = (1000000000ULL << 32) / periphclk;
     82  a9mpcore_clock_last_tick_k = (UINT64_C(1000000000) << 32) / periphclk;
    6783
    68   pt->load = (uint32_t) interval - 1;
    69   pt->ctrl = A9MPCORE_PT_CTRL_AUTO_RLD
    70     | A9MPCORE_PT_CTRL_IRQ_EN
    71     | A9MPCORE_PT_CTRL_TMR_EN;
     84  gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
     85  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
     86
     87  cmpval = a9mpcore_clock_get_counter(gt);
     88  cmpval += interval;
     89
     90  gt->cmpvallower = (uint32_t) cmpval;
     91  gt->cmpvalupper = (uint32_t) (cmpval >> 32);
     92  gt->autoinc = interval;
     93  gt->ctrl = A9MPCORE_GT_CTRL_AUTOINC_EN
     94    | A9MPCORE_GT_CTRL_IRQ_EN
     95    | A9MPCORE_GT_CTRL_COMP_EN
     96    | A9MPCORE_GT_CTRL_TMR_EN;
    7297}
    7398
    7499static void a9mpcore_clock_cleanup(void)
    75100{
    76   volatile a9mpcore_pt *pt = A9MPCORE_PT;
     101  volatile a9mpcore_gt *gt = A9MPCORE_GT;
    77102  rtems_status_code sc;
    78103
    79   pt->ctrl = 0;
    80   pt->irqst = A9MPCORE_PT_IRQST_EFLG;
     104  gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
     105  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
    81106
    82107  sc = rtems_interrupt_handler_remove(
    83     A9MPCORE_IRQ_PT,
     108    A9MPCORE_IRQ_GT,
    84109    (rtems_interrupt_handler) Clock_isr,
    85110    NULL
     
    95120static uint32_t a9mpcore_clock_nanoseconds_since_last_tick(void)
    96121{
    97   volatile a9mpcore_pt *pt = A9MPCORE_PT;
     122  volatile a9mpcore_gt *gt = A9MPCORE_GT;
    98123  uint64_t k = a9mpcore_clock_last_tick_k;
    99   uint32_t c = pt->cntr;
    100   uint32_t p = pt->load + 1;
     124  uint32_t c = gt->cntrlower;
     125  uint32_t n = gt->cmpvallower;
     126  uint32_t i = gt->autoinc;
    101127
    102   if ((pt->irqst & A9MPCORE_PT_IRQST_EFLG) != 0) {
    103     c = pt->cntr - p;
     128  if ((gt->irqst & A9MPCORE_GT_IRQST_EFLG) != 0) {
     129    n = gt->cmpvallower - i;
    104130  }
    105131
    106   return (uint32_t) (((p - c) * k) >> 32);
     132  return (uint32_t) (((c - n - i) * k) >> 32);
    107133}
    108134
  • c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h

    r069e10c3 r0df8d7f2  
    5959
    6060typedef struct {
    61   uint32_t cntr;
    62   uint32_t reserved_04;
     61  uint32_t cntrlower;
     62  uint32_t cntrupper;
     63#define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
     64#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
     65#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
     66#define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3)
     67#define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2)
     68#define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1)
     69#define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0)
    6370  uint32_t ctrl;
     71#define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0)
    6472  uint32_t irqst;
    65   uint32_t cmpval;
    66   uint32_t reserved_14;
     73  uint32_t cmpvallower;
     74  uint32_t cmpvalupper;
    6775  uint32_t autoinc;
    6876} a9mpcore_gt;
  • c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h

    r069e10c3 r0df8d7f2  
    121121}
    122122
     123BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_global_timer(void)
     124{
     125  volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE;
     126
     127  gt->ctrl = 0;
     128  gt->cntrlower = 0;
     129  gt->cntrupper = 0;
     130  gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN;
     131}
     132
    123133BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_1(void)
    124134{
     135  arm_a9mpcore_start_global_timer();
    125136  arm_a9mpcore_start_set_vector_base();
    126137}
  • c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h

    r069e10c3 r0df8d7f2  
    5050#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100
    5151
     52#define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200
     53
    5254#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600
    5355
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