Changeset 0dd1d44 in rtems for c/src/lib/libcpu/sh/sh7045/clock


Ignore:
Timestamp:
Jan 11, 2000, 5:34:20 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
76c2b35
Parents:
bdb2899
Message:

Removed old hack of using Configuration Table entry ticks_per_timeslice
being set to 0 to indicate that there should be no Clock Tick. This
was used by the Timing Tests to avoid clock tick overhead perturbing
execution times. Now the Timing Tests simply leave the Clock Tick
Driver out of the Device Driver Table.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/sh/sh7045/clock/ckinit.c

    rbdb2899 r0dd1d44  
    162162  Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
    163163
    164   /*
    165    *  If ticks_per_timeslice is configured as non-zero, then the user
    166    *  wants a clock tick.
    167    */
    168 
    169   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    170     rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
    171     /*
    172      *  Hardware specific initialize goes here
    173      */
     164  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
     165
     166  /*
     167   *  Hardware specific initialize goes here
     168   */
    174169   
    175     /* stop Timer 0 */
    176     temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
    177     write8( temp8, MTU_TSTR);
    178 
    179     /* set initial counter value to 0 */
    180     write16( 0, MTU_TCNT0);
    181 
    182     /* Timer 0 runs independent */
    183     temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
    184     write8( temp8, MTU_TSYR);
    185 
    186     /* Timer 0 normal mode */
    187     temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
    188     write8( temp8, MTU_TMDR0);
    189 
    190     /* TCNT is cleared by GRA ; internal clock /4 */
    191     write8( MTU0_TCRMASK , MTU_TCR0);
    192 
    193     /* use GRA without I/O - pins  */
    194     write8( MTU0_TIORVAL, MTU_TIORL0);
     170  /* stop Timer 0 */
     171  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
     172  write8( temp8, MTU_TSTR);
     173
     174  /* set initial counter value to 0 */
     175  write16( 0, MTU_TCNT0);
     176
     177  /* Timer 0 runs independent */
     178  temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
     179  write8( temp8, MTU_TSYR);
     180
     181  /* Timer 0 normal mode */
     182  temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
     183  write8( temp8, MTU_TMDR0);
     184
     185  /* TCNT is cleared by GRA ; internal clock /4 */
     186  write8( MTU0_TCRMASK , MTU_TCR0);
     187
     188  /* use GRA without I/O - pins  */
     189  write8( MTU0_TIORVAL, MTU_TIORL0);
    195190   
    196     /* reset flags of the status register */
    197     temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
    198     write8( temp8, MTU_TSR0);
    199 
    200     /* Irq if is equal GRA */
    201     temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
    202     write8( temp8, MTU_TIER0);
    203 
    204     /* set interrupt priority */
    205     if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
    206       rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
    207 
    208     /* set counter limits */
    209     write16( _MTU_COUNTER0_MICROSECOND *
    210       rtems_configuration_get_microseconds_per_tick(),
    211 
    212              MTU_GR0A);
     191  /* reset flags of the status register */
     192  temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
     193  write8( temp8, MTU_TSR0);
     194
     195  /* Irq if is equal GRA */
     196  temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
     197  write8( temp8, MTU_TIER0);
     198
     199  /* set interrupt priority */
     200  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
     201    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
     202
     203  /* set counter limits */
     204  write16( _MTU_COUNTER0_MICROSECOND *
     205    rtems_configuration_get_microseconds_per_tick(), MTU_GR0A);
    213206   
    214     /* start counter */
    215     temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
    216     write8( temp8, MTU_TSTR);
    217    
    218   }
     207  /* start counter */
     208  temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
     209  write8( temp8, MTU_TSTR);
    219210
    220211  /*
     
    232223{
    233224  unsigned8 temp8 = 0;
    234   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    235 
    236     /* turn off the timer interrupts */
    237     /* set interrupt priority to 0 */
    238     if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
    239       rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
     225
     226  /* turn off the timer interrupts */
     227  /* set interrupt priority to 0 */
     228  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
     229    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
    240230
    241231/*
     
    244234 */
    245235
    246     /* stop counter */
    247     temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
    248     write8( temp8, MTU_TSTR);
    249 
    250     /* old vector shall not be installed */
    251   }
     236  /* stop counter */
     237  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
     238  write8( temp8, MTU_TSTR);
     239
     240  /* old vector shall not be installed */
    252241}
    253242
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