Changeset 0dd1d44 in rtems for c/src/lib/libcpu


Ignore:
Timestamp:
Jan 11, 2000, 5:34:20 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
76c2b35
Parents:
bdb2899
Message:

Removed old hack of using Configuration Table entry ticks_per_timeslice
being set to 0 to indicate that there should be no Clock Tick. This
was used by the Timing Tests to avoid clock tick overhead perturbing
execution times. Now the Timing Tests simply leave the Clock Tick
Driver out of the Device Driver Table.

Location:
c/src/lib/libcpu
Files:
9 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/hppa1.1/clock/clock.c

    rbdb2899 r0dd1d44  
    102102    Clock_isrs = rtems_configuration_get_milliseconds_per_tick();
    103103
    104     if ( rtems_configuration_get_ticks_per_timeslice() ) {
    105         /*
    106          * initialize the interval here
    107          * First tick is set to right amount of time in the future
    108          * Future ticks will be incremented over last value set
    109          * in order to provide consistent clicks in the face of
    110          * interrupt overhead
    111          */
    112 
    113         Clock_clicks_interrupt = Clock_read_itimer() + CPU_HPPA_CLICKS_PER_TICK;
    114         set_itimer((rtems_unsigned32) Clock_clicks_interrupt);
    115 
    116         (void) set_vector(clock_isr, HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER, 1);
    117     }
     104    /*
     105     * initialize the interval here
     106     * First tick is set to right amount of time in the future
     107     * Future ticks will be incremented over last value set
     108     * in order to provide consistent clicks in the face of
     109     * interrupt overhead
     110     */
     111
     112    Clock_clicks_interrupt = Clock_read_itimer() + CPU_HPPA_CLICKS_PER_TICK;
     113    set_itimer((rtems_unsigned32) Clock_clicks_interrupt);
     114
     115    (void) set_vector(clock_isr, HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER, 1);
    118116    atexit(Clock_exit);
    119117}
     
    187185Clock_exit(void)
    188186{
    189     if ( rtems_configuration_get_ticks_per_timeslice() ) {
    190         (void) set_vector(0, HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER, 1);
    191     }
     187  (void) set_vector(0, HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER, 1);
    192188}
    193189
  • c/src/lib/libcpu/mips/clock/ckinit.c

    rbdb2899 r0dd1d44  
    161161  Clock_isrs = rtems_configuration_get_milliseconds_per_tick();
    162162
    163   /*
    164    *  If ticks_per_timeslice is configured as non-zero, then the user
    165    *  wants a clock tick.
    166    */
    167 
    168   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    169     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    170     /*
    171      *  Hardware specific initialize goes here
    172      */
    173 
    174     mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
    175     mips_set_timer( mips_timer_rate );
    176     enable_int(CLOCK_VECTOR_MASK);
    177   }
     163  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     164  /*
     165   *  Hardware specific initialize goes here
     166   */
     167
     168  mips_timer_rate =
     169     rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
     170  mips_set_timer( mips_timer_rate );
     171  enable_int(CLOCK_VECTOR_MASK);
    178172
    179173  /*
     
    190184void Clock_exit( void )
    191185{
    192   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    193     /* mips: turn off the timer interrupts */
    194     disable_int(~CLOCK_VECTOR_MASK);
    195   }
     186  /* mips: turn off the timer interrupts */
     187  disable_int(~CLOCK_VECTOR_MASK);
    196188}
    197189
  • c/src/lib/libcpu/mips64orion/clock/ckinit.c

    rbdb2899 r0dd1d44  
    161161  Clock_isrs = rtems_configuration_get_milliseconds_per_tick();
    162162
    163   /*
    164    *  If ticks_per_timeslice is configured as non-zero, then the user
    165    *  wants a clock tick.
    166    */
    167 
    168   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    169     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    170     /*
    171      *  Hardware specific initialize goes here
    172      */
    173 
    174     mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
    175     mips_set_timer( mips_timer_rate );
    176     enable_int(CLOCK_VECTOR_MASK);
    177   }
     163  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     164  /*
     165   *  Hardware specific initialize goes here
     166   */
     167
     168  mips_timer_rate =
     169     rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
     170  mips_set_timer( mips_timer_rate );
     171  enable_int(CLOCK_VECTOR_MASK);
    178172
    179173  /*
     
    190184void Clock_exit( void )
    191185{
    192   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    193     /* mips: turn off the timer interrupts */
    194     disable_int(~CLOCK_VECTOR_MASK);
    195   }
     186  /* mips: turn off the timer interrupts */
     187  disable_int(~CLOCK_VECTOR_MASK);
    196188}
    197189
  • c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c

    rbdb2899 r0dd1d44  
    4949void clockOff(void* unused)
    5050{
    51   if (BSP_Configuration.ticks_per_timeslice)    {
    52     /*
    53      * Nothing to do as we cannot disable all interrupts and
    54      * the decrementer interrupt enable is MSR_EE
    55      */
    56   }
     51  /*
     52   * Nothing to do as we cannot disable all interrupts and
     53   * the decrementer interrupt enable is MSR_EE
     54   */
    5755}
    5856void clockOn(void* unused)
     
    117115void Clock_exit( void )
    118116{
    119   if ( BSP_Configuration.ticks_per_timeslice ) {
    120    (void) BSP_disconnect_clock_handler ();
    121   }
     117  (void) BSP_disconnect_clock_handler ();
    122118}
    123119 
  • c/src/lib/libcpu/powerpc/mpc821/clock/clock.c

    rbdb2899 r0dd1d44  
    8282    rtems_fatal_error_occurred(-1);
    8383  } 
    84   if ( rtems_configuration_get_ticks_per_timeslice() ) {
     84
     85  /*
     86   * initialize the interval here
     87   * First tick is set to right amount of time in the future
     88   * Future ticks will be incremented over last value set
     89   * in order to provide consistent clicks in the face of
     90   * interrupt overhead
     91   */
     92 
     93  rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
    8594   
    86     /*
    87      * initialize the interval here
    88      * First tick is set to right amount of time in the future
    89      * Future ticks will be incremented over last value set
    90      * in order to provide consistent clicks in the face of
    91      * interrupt overhead
    92      */
     95  m821.sccr &= ~(1<<24);
     96  m821.pitc = pit_value;
    9397   
    94     rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
     98  /* set PIT irq level, enable PIT, PIT interrupts */
     99  /*  and clear int. status */
     100  m821.piscr = M821_PISCR_PIRQ(0) |
     101    M821_PISCR_PTE | M821_PISCR_PS | M821_PISCR_PIE;
    95102   
    96     m821.sccr &= ~(1<<24);
    97     m821.pitc = pit_value;
    98    
    99     /* set PIT irq level, enable PIT, PIT interrupts */
    100     /*  and clear int. status */
    101     m821.piscr = M821_PISCR_PIRQ(0) |
    102       M821_PISCR_PTE | M821_PISCR_PS | M821_PISCR_PIE;
    103    
    104     m821.simask |= M821_SIMASK_LVM0;
    105   }
     103  m821.simask |= M821_SIMASK_LVM0;
    106104  atexit(Clock_exit);
    107105}
     
    128126Clock_exit(void)
    129127{
    130   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    131     /* disable PIT and PIT interrupts */
    132     m821.piscr &= ~(M821_PISCR_PTE | M821_PISCR_PIE);
    133    
    134     (void) set_vector(0, PPC_IRQ_LVL0, 1);
    135   }
     128  /* disable PIT and PIT interrupts */
     129  m821.piscr &= ~(M821_PISCR_PTE | M821_PISCR_PIE);
     130 
     131  (void) set_vector(0, PPC_IRQ_LVL0, 1);
    136132}
    137133
  • c/src/lib/libcpu/powerpc/mpc860/clock/clock.c

    rbdb2899 r0dd1d44  
    8383    rtems_fatal_error_occurred(-1);
    8484  } 
    85   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    8685   
    87     /*
    88      * initialize the interval here
    89      * First tick is set to right amount of time in the future
    90      * Future ticks will be incremented over last value set
    91      * in order to provide consistent clicks in the face of
    92      * interrupt overhead
    93      */
     86  /*
     87   * initialize the interval here
     88   * First tick is set to right amount of time in the future
     89   * Future ticks will be incremented over last value set
     90   * in order to provide consistent clicks in the face of
     91   * interrupt overhead
     92   */
     93 
     94  rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
    9495   
    95     rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
     96  m860.sccr &= ~(1<<24);
     97  m860.pitc = pit_value;
    9698   
    97     m860.sccr &= ~(1<<24);
    98     m860.pitc = pit_value;
     99  /* set PIT irq level, enable PIT, PIT interrupts */
     100  /*  and clear int. status */
     101  m860.piscr = M860_PISCR_PIRQ(0) |
     102    M860_PISCR_PTE | M860_PISCR_PS | M860_PISCR_PIE;
    99103   
    100     /* set PIT irq level, enable PIT, PIT interrupts */
    101     /*  and clear int. status */
    102     m860.piscr = M860_PISCR_PIRQ(0) |
    103       M860_PISCR_PTE | M860_PISCR_PS | M860_PISCR_PIE;
    104    
    105     m860.simask |= M860_SIMASK_LVM0;
    106   }
     104  m860.simask |= M860_SIMASK_LVM0;
    107105  atexit(Clock_exit);
    108106}
     
    129127Clock_exit(void)
    130128{
    131   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    132     /* disable PIT and PIT interrupts */
    133     m860.piscr &= ~(M860_PISCR_PTE | M860_PISCR_PIE);
     129  /* disable PIT and PIT interrupts */
     130  m860.piscr &= ~(M860_PISCR_PTE | M860_PISCR_PIE);
    134131   
    135     (void) set_vector(0, PPC_IRQ_LVL0, 1);
    136   }
     132  (void) set_vector(0, PPC_IRQ_LVL0, 1);
    137133}
    138134
  • c/src/lib/libcpu/powerpc/ppc403/clock/clock.c

    rbdb2899 r0dd1d44  
    133133    rtems_isr_entry previous_isr;
    134134    rtems_unsigned32 pvr, iocr;
     135    register rtems_unsigned32 tcr;
    135136 
    136137    Clock_driver_ticks = 0;
     
    165166      rtems_cpu_configuration_get_clicks_per_usec();
    166167 
    167     if ( rtems_configuration_get_ticks_per_timeslice() ) {
    168       register rtems_unsigned32 tcr;
    169 
    170         /*
    171          * initialize the interval here
    172          * First tick is set to right amount of time in the future
    173          * Future ticks will be incremented over last value set
    174          * in order to provide consistent clicks in the face of
    175          * interrupt overhead
    176          */
    177  
    178       rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr);
    179  
    180       asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
    181  
    182       asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    183  
    184       tcr &= ~ 0x04400000;
    185  
    186       tcr |= (auto_restart ? 0x04400000 : 0x04000000);
    187  
    188       tick_time = get_itimer() + pit_value;
    189  
    190       asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    191     }
     168
     169    /*
     170     * initialize the interval here
     171     * First tick is set to right amount of time in the future
     172     * Future ticks will be incremented over last value set
     173     * in order to provide consistent clicks in the face of
     174     * interrupt overhead
     175     */
     176
     177    rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr);
     178
     179    asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
     180 
     181    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     182 
     183    tcr &= ~ 0x04400000;
     184 
     185    tcr |= (auto_restart ? 0x04400000 : 0x04000000);
     186 
     187    tick_time = get_itimer() + pit_value;
     188 
     189    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     190
    192191    atexit(Clock_exit);
    193192}
     
    215214Clock_exit(void)
    216215{
    217     if ( rtems_configuration_get_ticks_per_timeslice() ) {
    218       register rtems_unsigned32 tcr;
    219  
    220       asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    221  
    222       tcr &= ~ 0x04400000;
    223  
    224       asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    225  
    226       (void) set_vector(0, PPC_IRQ_PIT, 1);
    227     }
    228 
     216    register rtems_unsigned32 tcr;
     217 
     218    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     219 
     220    tcr &= ~ 0x04400000;
     221 
     222    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     223 
     224    (void) set_vector(0, PPC_IRQ_PIT, 1);
    229225}
    230226
  • c/src/lib/libcpu/sh/sh7032/clock/ckinit.c

    rbdb2899 r0dd1d44  
    224224  Clock_isrs = Clock_isrs_const;
    225225
    226   /*
    227    *  If ticks_per_timeslice is configured as non-zero, then the user
    228    *  wants a clock tick.
    229    */
    230 
    231   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    232     rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
    233     /*
    234      *  Hardware specific initialize goes here
    235      */
     226  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
     227  /*
     228   *  Hardware specific initialize goes here
     229   */
     230 
     231  /* stop Timer 0 */
     232  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
     233  write8( temp8, ITU_TSTR);
     234
     235  /* set initial counter value to 0 */
     236  write16( 0, ITU_TCNT0);
     237
     238  /* Timer 0 runs independent */
     239  temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK;
     240  write8( temp8, ITU_TSNC);
     241
     242  /* Timer 0 normal mode */
     243  temp8 = read8( ITU_TMDR) & ITU0_MODEMASK;
     244  write8( temp8, ITU_TMDR);
     245
     246  /* TCNT is cleared by GRA ; internal clock /4 */
     247  write8( ITU0_TCRMASK , ITU_TCR0);
     248
     249  /* use GRA without I/O - pins  */
     250  write8( ITU0_TIORVAL, ITU_TIOR0);
    236251   
    237     /* stop Timer 0 */
    238     temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
    239     write8( temp8, ITU_TSTR);
    240 
    241     /* set initial counter value to 0 */
    242     write16( 0, ITU_TCNT0);
    243 
    244     /* Timer 0 runs independent */
    245     temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK;
    246     write8( temp8, ITU_TSNC);
    247 
    248     /* Timer 0 normal mode */
    249     temp8 = read8( ITU_TMDR) & ITU0_MODEMASK;
    250     write8( temp8, ITU_TMDR);
    251 
    252     /* TCNT is cleared by GRA ; internal clock /4 */
    253     write8( ITU0_TCRMASK , ITU_TCR0);
    254 
    255     /* use GRA without I/O - pins  */
    256     write8( ITU0_TIORVAL, ITU_TIOR0);
    257    
    258     /* reset flags of the status register */
    259     temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
    260     write8( temp8, ITU_TSR0);
    261 
    262     /* Irq if is equal GRA */
    263     temp8 = read8( ITU_TIER0) | ITU0_TIERMASK;
    264     write8( temp8, ITU_TIER0);
    265 
    266     /* set interrupt priority */
    267     if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
    268       rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
    269 
    270     /* set counter limits */
    271     write16( Clock_limit, ITU_GRA0);
     252  /* reset flags of the status register */
     253  temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
     254  write8( temp8, ITU_TSR0);
     255
     256  /* Irq if is equal GRA */
     257  temp8 = read8( ITU_TIER0) | ITU0_TIERMASK;
     258  write8( temp8, ITU_TIER0);
     259
     260  /* set interrupt priority */
     261  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
     262    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
     263
     264  /* set counter limits */
     265  write16( Clock_limit, ITU_GRA0);
    272266   
    273     /* start counter */
    274     temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
    275     write8( temp8, ITU_TSTR);
    276    
    277   }
     267  /* start counter */
     268  temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
     269  write8( temp8, ITU_TSTR);
    278270
    279271  /*
     
    291283{
    292284  unsigned8 temp8 = 0;
    293   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    294 
    295     /* turn off the timer interrupts */
    296     /* set interrupt priority to 0 */
    297     if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
    298       rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
     285
     286  /* turn off the timer interrupts */
     287  /* set interrupt priority to 0 */
     288  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
     289    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
    299290
    300291/*
     
    303294 */
    304295
    305     /* stop counter */
    306     temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
    307     write8( temp8, ITU_TSTR);
    308 
    309     /* old vector shall not be installed */
    310   }
     296  /* stop counter */
     297  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
     298  write8( temp8, ITU_TSTR);
     299
     300  /* old vector shall not be installed */
    311301}
    312302
  • c/src/lib/libcpu/sh/sh7045/clock/ckinit.c

    rbdb2899 r0dd1d44  
    162162  Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
    163163
    164   /*
    165    *  If ticks_per_timeslice is configured as non-zero, then the user
    166    *  wants a clock tick.
    167    */
    168 
    169   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    170     rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
    171     /*
    172      *  Hardware specific initialize goes here
    173      */
     164  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
     165
     166  /*
     167   *  Hardware specific initialize goes here
     168   */
    174169   
    175     /* stop Timer 0 */
    176     temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
    177     write8( temp8, MTU_TSTR);
    178 
    179     /* set initial counter value to 0 */
    180     write16( 0, MTU_TCNT0);
    181 
    182     /* Timer 0 runs independent */
    183     temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
    184     write8( temp8, MTU_TSYR);
    185 
    186     /* Timer 0 normal mode */
    187     temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
    188     write8( temp8, MTU_TMDR0);
    189 
    190     /* TCNT is cleared by GRA ; internal clock /4 */
    191     write8( MTU0_TCRMASK , MTU_TCR0);
    192 
    193     /* use GRA without I/O - pins  */
    194     write8( MTU0_TIORVAL, MTU_TIORL0);
     170  /* stop Timer 0 */
     171  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
     172  write8( temp8, MTU_TSTR);
     173
     174  /* set initial counter value to 0 */
     175  write16( 0, MTU_TCNT0);
     176
     177  /* Timer 0 runs independent */
     178  temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
     179  write8( temp8, MTU_TSYR);
     180
     181  /* Timer 0 normal mode */
     182  temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
     183  write8( temp8, MTU_TMDR0);
     184
     185  /* TCNT is cleared by GRA ; internal clock /4 */
     186  write8( MTU0_TCRMASK , MTU_TCR0);
     187
     188  /* use GRA without I/O - pins  */
     189  write8( MTU0_TIORVAL, MTU_TIORL0);
    195190   
    196     /* reset flags of the status register */
    197     temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
    198     write8( temp8, MTU_TSR0);
    199 
    200     /* Irq if is equal GRA */
    201     temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
    202     write8( temp8, MTU_TIER0);
    203 
    204     /* set interrupt priority */
    205     if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
    206       rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
    207 
    208     /* set counter limits */
    209     write16( _MTU_COUNTER0_MICROSECOND *
    210       rtems_configuration_get_microseconds_per_tick(),
    211 
    212              MTU_GR0A);
     191  /* reset flags of the status register */
     192  temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
     193  write8( temp8, MTU_TSR0);
     194
     195  /* Irq if is equal GRA */
     196  temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
     197  write8( temp8, MTU_TIER0);
     198
     199  /* set interrupt priority */
     200  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
     201    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
     202
     203  /* set counter limits */
     204  write16( _MTU_COUNTER0_MICROSECOND *
     205    rtems_configuration_get_microseconds_per_tick(), MTU_GR0A);
    213206   
    214     /* start counter */
    215     temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
    216     write8( temp8, MTU_TSTR);
    217    
    218   }
     207  /* start counter */
     208  temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
     209  write8( temp8, MTU_TSTR);
    219210
    220211  /*
     
    232223{
    233224  unsigned8 temp8 = 0;
    234   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    235 
    236     /* turn off the timer interrupts */
    237     /* set interrupt priority to 0 */
    238     if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
    239       rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
     225
     226  /* turn off the timer interrupts */
     227  /* set interrupt priority to 0 */
     228  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
     229    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
    240230
    241231/*
     
    244234 */
    245235
    246     /* stop counter */
    247     temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
    248     write8( temp8, MTU_TSTR);
    249 
    250     /* old vector shall not be installed */
    251   }
     236  /* stop counter */
     237  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
     238  write8( temp8, MTU_TSTR);
     239
     240  /* old vector shall not be installed */
    252241}
    253242
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