Changeset 0dd1d44 in rtems for c/src/lib


Ignore:
Timestamp:
Jan 11, 2000, 5:34:20 PM (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
76c2b35
Parents:
bdb2899
Message:

Removed old hack of using Configuration Table entry ticks_per_timeslice
being set to 0 to indicate that there should be no Clock Tick. This
was used by the Timing Tests to avoid clock tick overhead perturbing
execution times. Now the Timing Tests simply leave the Clock Tick
Driver out of the Device Driver Table.

Location:
c/src/lib
Files:
30 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/i386/pc386/clock/ckinit.c

    rbdb2899 r0dd1d44  
    104104void clockOff(const rtems_irq_connect_data* unused)
    105105{
    106   if (BSP_Configuration.ticks_per_timeslice)
    107   {
    108     /* reset timer mode to standard (BIOS) value */
    109     outport_byte(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN);
    110     outport_byte(TIMER_CNTR0, 0);
    111     outport_byte(TIMER_CNTR0, 0);
    112   }
     106  /* reset timer mode to standard (BIOS) value */
     107  outport_byte(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN);
     108  outport_byte(TIMER_CNTR0, 0);
     109  outport_byte(TIMER_CNTR0, 0);
    113110} /* Clock_exit */
    114111
     
    159156  Clock_isrs = Clock_isrs_per_tick; /* Initialize Clock_isrs */
    160157
    161   if (BSP_Configuration.ticks_per_timeslice)
    162158  {
    163159    /* 105/88 approximates TIMER_TICK * 1e-6 */
  • c/src/lib/libbsp/i960/cvme961/clock/ckinit.c

    rbdb2899 r0dd1d44  
    5252  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    5353
    54   if ( BSP_Configuration.ticks_per_timeslice ) {
    55     Old_ticker = set_vector( clock_isr, CLOCK_VECTOR, 1 );
    56     victimer = (volatile unsigned char *) 0xa00000c3;
    57     *victimer = 0x12;
    58     *victimer = 0x92;      /* 1000 HZ */
    59   }
     54  Old_ticker = set_vector( clock_isr, CLOCK_VECTOR, 1 );
     55  victimer = (volatile unsigned char *) 0xa00000c3;
     56  *victimer = 0x12;
     57  *victimer = 0x92;      /* 1000 HZ */
    6058}
    6159
     
    6462  unsigned char *victimer;
    6563
    66   if ( BSP_Configuration.ticks_per_timeslice ) {
    67     victimer = (unsigned char *) 0xa00000c3;
    68     *victimer = 0x12;
    69     i960_mask_intr( 5 );
    70     /* do not restore old vector */
    71   }
     64  victimer = (unsigned char *) 0xa00000c3;
     65  *victimer = 0x12;
     66  i960_mask_intr( 5 );
     67  /* do not restore old vector */
    7268}
    7369
  • c/src/lib/libbsp/i960/rxgen960/clock/ckinit.c

    rbdb2899 r0dd1d44  
    6666  Clock_isrs = Reload_Clock_isrs;
    6767
    68 /* Not for our case
    69   if ( BSP_Configuration.ticks_per_timeslice ) {
    70      *icon = 0x6000;
    71 
    72     Old_ticker = set_vector( (((unsigned int) clock_isr) | 0x2), CLOCK_VECTOR, 1 );
    73 */
    7468    #define BUS_CLOCK_1 0
    7569    #define TMR_WRITE_CNTL 8
     
    7973
    8074    Old_ticker = set_vector( (((unsigned int) clock_isr) | 0x2), CLOCK_VECTOR, 1 );
    81 /*
    82     *(unsigned int *)(CLOCK_VECTOR >>2) = (unsigned int )clockHandler;
    83 */
    8475
    8576    /* initialize the i960RP timer 0 here */
     
    10394  volatile unsigned int *tmr0 = (unsigned int *) TMR0_ADDR;
    10495
    105   if ( BSP_Configuration.ticks_per_timeslice ) {
    106     /* shut down the timer */
    107     *tmr0 = *tmr0 & ~TMR_ENABLE;
     96  /* shut down the timer */
     97  *tmr0 = *tmr0 & ~TMR_ENABLE;
    10898
    109     i960_mask_intr( 12 );
    110     /* do not restore old vector */
    111   }
     99  i960_mask_intr( 12 );
     100  /* do not restore old vector */
    112101}
    113102
  • c/src/lib/libbsp/m68k/dmv152/clock/ckinit.c

    rbdb2899 r0dd1d44  
    7070  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    7171
    72   if ( BSP_Configuration.ticks_per_timeslice ) {
    73     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     72  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    7473
    75     Z8x36_WRITE( TIMER, MASTER_CFG, 0xd4 );
    76     Z8x36_READ ( TIMER, MASTER_INTR, data );
    77     Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0x7E) );
    78     Z8x36_WRITE( TIMER, CT1_TIME_CONST_MSB, 0x04 );
    79     Z8x36_WRITE( TIMER, CT1_TIME_CONST_LSB, 0xCE );
    80     Z8x36_WRITE( TIMER, CT1_MODE_SPEC, 0x83 );
    81     Z8x36_WRITE( TIMER, CNT_TMR_VECTOR, CLOCK_VECTOR );
    82     Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0x20 );
    83     Z8x36_READ ( TIMER, MASTER_INTR, data );
    84     Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0xDA) | 0x80 );
     74  Z8x36_WRITE( TIMER, MASTER_CFG, 0xd4 );
     75  Z8x36_READ ( TIMER, MASTER_INTR, data );
     76  Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0x7E) );
     77  Z8x36_WRITE( TIMER, CT1_TIME_CONST_MSB, 0x04 );
     78  Z8x36_WRITE( TIMER, CT1_TIME_CONST_LSB, 0xCE );
     79  Z8x36_WRITE( TIMER, CT1_MODE_SPEC, 0x83 );
     80  Z8x36_WRITE( TIMER, CNT_TMR_VECTOR, CLOCK_VECTOR );
     81  Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0x20 );
     82  Z8x36_READ ( TIMER, MASTER_INTR, data );
     83  Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0xDA) | 0x80 );
    8584
    86     /*
    87      * ACC_IC54 - interrupt 5 will be vectored and mapped to level 6
    88      */
     85  /*
     86   * ACC_IC54 - interrupt 5 will be vectored and mapped to level 6
     87   */
    8988
    90     data = (*(rtems_unsigned8 *)0x0D00000B);
    91     (*(rtems_unsigned8 *)0x0D00000B) = (data & 0x7F) | 0x60;
     89  data = (*(rtems_unsigned8 *)0x0D00000B);
     90  (*(rtems_unsigned8 *)0x0D00000B) = (data & 0x7F) | 0x60;
    9291
    93     Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xC6 );
     92  Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xC6 );
    9493
    95     atexit( Clock_exit );
    96   }
     94  atexit( Clock_exit );
    9795}
    9896
     
    10199  rtems_unsigned8 data;
    102100
    103   if ( BSP_Configuration.ticks_per_timeslice ) {
    104 
    105     Z8x36_READ ( TIMER, MASTER_INTR, data );
    106     Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0x01) );
    107     /* do not restore old vector */
    108 
    109   }
     101  Z8x36_READ ( TIMER, MASTER_INTR, data );
     102  Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0x01) );
     103  /* do not restore old vector */
    110104}
    111105
  • c/src/lib/libbsp/m68k/efi332/clock/ckinit.c

    rbdb2899 r0dd1d44  
    5858  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    5959
    60   if ( BSP_Configuration.ticks_per_timeslice ) {
    61     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     60  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    6261
    63     /* enable 1mS interrupts */
    64     *PITR = (unsigned short int)( SAM(0x09,0,PITM) );/* load counter */
    65     *PICR = (unsigned short int)                     /* enable interrupt */
    66       ( SAM(ISRL_PIT,8,PIRQL) | SAM(CLOCK_VECTOR,0,PIV) );
    67    
    68     atexit( Clock_exit );
    69   }
     62  /* enable 1mS interrupts */
     63  *PITR = (unsigned short int)( SAM(0x09,0,PITM) );/* load counter */
     64  *PICR = (unsigned short int)                     /* enable interrupt */
     65    ( SAM(ISRL_PIT,8,PIRQL) | SAM(CLOCK_VECTOR,0,PIV) );
     66 
     67  atexit( Clock_exit );
    7068}
    7169
    7270void Clock_exit( void )
    7371{
     72  /* shutdown the periodic interrupt */
     73  *PICR = (unsigned short int)
     74    ( SAM(0,8,PIRQL) | SAM(CLOCK_VECTOR,0,PIV) );
     75  /*     ^^ zero disables interrupt */
    7476
    75   if ( BSP_Configuration.ticks_per_timeslice ) {
    76 
    77     /* shutdown the periodic interrupt */
    78     *PICR = (unsigned short int)
    79       ( SAM(0,8,PIRQL) | SAM(CLOCK_VECTOR,0,PIV) );
    80     /*     ^^ zero disables interrupt */
    81 
    82     /* do not restore old vector */
    83 
    84   }
     77  /* do not restore old vector */
    8578}
    8679
  • c/src/lib/libbsp/m68k/efi68k/clock/ckinit.c

    rbdb2899 r0dd1d44  
    8383  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    8484
    85   if ( BSP_Configuration.ticks_per_timeslice ) {
    86     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     85  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    8786
    88     *MSR = RS;                  /* enable 1mS interrupts */
    89     *ICR0 |= OME;
     87  *MSR = RS;                    /* enable 1mS interrupts */
     88  *ICR0 |= OME;
    9089
    91     atexit( Clock_exit );
    92   }
     90  atexit( Clock_exit );
    9391}
    9492
    9593void Clock_exit( void )
    9694{
    97 
    98   if ( BSP_Configuration.ticks_per_timeslice ) {
    99 
    100     /* shutdown periodic interrupt */
    101     *MSR = RS;
    102     *ICR0 &= 0xc0;
    103     /* do not restore old vector */
    104 
    105   }
     95  /* shutdown periodic interrupt */
     96  *MSR = RS;
     97  *ICR0 &= 0xc0;
     98  /* do not restore old vector */
    10699}
    107100
  • c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c

    rbdb2899 r0dd1d44  
    8484)
    8585{
    86 
    8786  Clock_driver_ticks = 0;
    8887  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    8988
    90   if ( BSP_Configuration.ticks_per_timeslice ) {
    91    set_vector( clock_isr, CLOCK_VECTOR, 1 );
     89  set_vector( clock_isr, CLOCK_VECTOR, 1 );
    9290
    93     m302.reg.trr1 = TRR1_VAL;           /* set timer reference register */
    94     m302.reg.tmr1 = TMR1_VAL;           /* set timer mode register & enable */
    95     /*
    96      * Enable TIMER1 interrupts only.
    97      */
    98     m302.reg.imr  = RBIT_IMR_TIMER1;    /* set 68302 int-mask to allow ints */
     91  m302.reg.trr1 = TRR1_VAL;             /* set timer reference register */
     92  m302.reg.tmr1 = TMR1_VAL;             /* set timer mode register & enable */
     93  /*
     94   * Enable TIMER1 interrupts only.
     95   */
     96  m302.reg.imr  = RBIT_IMR_TIMER1;      /* set 68302 int-mask to allow ints */
    9997
    100     atexit( Clock_exit );
    101   }
     98  atexit( Clock_exit );
    10299}
    103100
    104101void Clock_exit( void )
    105102{
    106   if ( BSP_Configuration.ticks_per_timeslice ) {
    107     /* TODO: figure out what to do here */
    108     /* do not restore old vector */
    109   }
     103  /* TODO: figure out what to do here */
     104  /* do not restore old vector */
    110105}
    111106
  • c/src/lib/libbsp/m68k/gen68340/clock/ckinit.c

    rbdb2899 r0dd1d44  
    7878Clock_exit (void)
    7979{
    80         if (BSP_Configuration.ticks_per_timeslice ) {
    81                 /*
    82                  * Turn off periodic interval timer
    83                  */             
    84                 SIMPITR = 0;
    85         }
     80        /*
     81         * Turn off periodic interval timer
     82         */             
     83        SIMPITR = 0;
    8684}
    8785
     
    9795{
    9896        unsigned32 pitr_tmp;
     97        unsigned32 usecs_per_tick;
    9998
    10099        Clock_driver_ticks = 0;
    101         if ( BSP_Configuration.ticks_per_timeslice ) {
    102100
    103                 set_vector (clock_isr, CLOCK_VECTOR, 1);
     101        set_vector (clock_isr, CLOCK_VECTOR, 1);
    104102               
    105                 /* sets the Periodic Interrupt Control Register PICR */
    106                 /* voir a quoi correspond exactement le Clock Vector */
     103        /* sets the Periodic Interrupt Control Register PICR */
     104        /* voir a quoi correspond exactement le Clock Vector */
    107105
    108                 SIMPICR = ( CLOCK_IRQ_LEVEL << 8 ) | ( CLOCK_VECTOR );         
    109                                  
    110                 /* sets the PITR count value */
    111                 /* this assumes a 32.765 kHz crystal */
     106        SIMPICR = ( CLOCK_IRQ_LEVEL << 8 ) | ( CLOCK_VECTOR );         
     107                         
     108        /* sets the PITR count value */
     109        /* this assumes a 32.765 kHz crystal */
    112110               
    113                 /* find out whether prescaler should be enabled or not */
    114                 if ( BSP_Configuration.microseconds_per_tick <= 31128 ) {
    115                    pitr_tmp = ( BSP_Configuration.microseconds_per_tick * 8192 ) / 1000000 ;
    116                 }
    117                 else {
    118                    pitr_tmp = ( BSP_Configuration.microseconds_per_tick / 1000000 ) * 16;
    119                    /* enable it */                 
    120                    pitr_tmp |= 0x100;             
    121                 }
     111        usecs_per_tick = BSP_Configuration.microseconds_per_tick;
     112        /* find out whether prescaler should be enabled or not */
     113        if ( usecs_per_tick <= 31128 ) {
     114           pitr_tmp = ( usecs_per_tick * 8192 ) / 1000000 ;
     115        } else {
     116           pitr_tmp = ( usecs_per_tick / 1000000 ) * 16;
     117           /* enable it */                 
     118           pitr_tmp |= 0x100;             
     119        }
    122120
    123                 SIMPITR = (unsigned char) pitr_tmp;
     121        SIMPITR = (unsigned char) pitr_tmp;
    124122
    125                 atexit (Clock_exit);
    126         }
     123        atexit (Clock_exit);
    127124}
    128125
  • c/src/lib/libbsp/m68k/gen68360/clock/ckinit.c

    rbdb2899 r0dd1d44  
    102102Clock_exit (void)
    103103{
    104         if (BSP_Configuration.ticks_per_timeslice ) {
    105                 /*
    106                  * Turn off periodic interval timer
    107                  */
    108                 m360.pitr &= ~0xFF;
    109         }
     104        /*
     105         * Turn off periodic interval timer
     106         */
     107        m360.pitr &= ~0xFF;
    110108}
    111109
     
    113111Install_clock (rtems_isr_entry clock_isr)
    114112{
     113        int divisor;
     114        extern int m360_clock_rate; /* This should be somewhere in a config file */
     115        unsigned long nsec_per_chip_tick = 1000000000 / m360_clock_rate;
     116        unsigned long nsec_per_pit_tick = 512 * nsec_per_chip_tick;
     117
    115118        Clock_driver_ticks = 0;
    116         if ( BSP_Configuration.ticks_per_timeslice ) {
    117                 /*
    118                  * Choose periodic interval timer register value
    119                  * The rate at which the periodic interval timer
    120                  * can generate interrupts is almost certainly not
    121                  * the same as desired by the BSP configuration.
    122                  * Handle the difference by choosing the largest PIT
    123                  * interval which is less than or equal to the RTEMS
    124                  * interval and skipping some hardware interrupts.
    125                  * To reduce the jitter in the calls to RTEMS the
    126                  * hardware interrupt interval is never less than
    127                  * the maximum non-prescaled value from the PIT.
    128                  *
    129                  * For a 25 MHz external clock the basic clock rate is
    130                  *      40 nsec * 128 * 4 = 20.48 usec/tick
    131                  */
    132                 int divisor;
    133                 extern int m360_clock_rate; /* This should be somewhere in a config file */
    134                 unsigned long nsec_per_chip_tick = 1000000000 / m360_clock_rate;
    135                 unsigned long nsec_per_pit_tick = 512 * nsec_per_chip_tick;
     119        /*
     120         * Choose periodic interval timer register value
     121         * The rate at which the periodic interval timer
     122         * can generate interrupts is almost certainly not
     123         * the same as desired by the BSP configuration.
     124         * Handle the difference by choosing the largest PIT
     125         * interval which is less than or equal to the RTEMS
     126         * interval and skipping some hardware interrupts.
     127         * To reduce the jitter in the calls to RTEMS the
     128         * hardware interrupt interval is never less than
     129         * the maximum non-prescaled value from the PIT.
     130         *
     131         * For a 25 MHz external clock the basic clock rate is
     132         *      40 nsec * 128 * 4 = 20.48 usec/tick
     133         */
    136134
    137                 rtems_nsec_per_tick = BSP_Configuration.microseconds_per_tick * 1000;
    138                 divisor = rtems_nsec_per_tick / nsec_per_pit_tick;
    139                 if (divisor >= 256) {
    140                         divisor = 255;
    141                 }
    142                 else if (divisor == 0) {
    143                         divisor = 1;
    144                 }
    145                 pit_nsec_per_tick = nsec_per_pit_tick * divisor;
    146                 m360.pitr &= ~0x1FF;
    147                 m360.picr = (CLOCK_IRQ_LEVEL << 8) | CLOCK_VECTOR;
    148                 set_vector (clock_isr, CLOCK_VECTOR, 1);
    149                 m360.pitr |= divisor;
    150                 atexit (Clock_exit);
     135        rtems_nsec_per_tick = BSP_Configuration.microseconds_per_tick * 1000;
     136        divisor = rtems_nsec_per_tick / nsec_per_pit_tick;
     137        if (divisor >= 256) {
     138                divisor = 255;
     139        } else if (divisor == 0) {
     140                divisor = 1;
    151141        }
     142        pit_nsec_per_tick = nsec_per_pit_tick * divisor;
     143        m360.pitr &= ~0x1FF;
     144        m360.picr = (CLOCK_IRQ_LEVEL << 8) | CLOCK_VECTOR;
     145        set_vector (clock_isr, CLOCK_VECTOR, 1);
     146        m360.pitr |= divisor;
     147        atexit (Clock_exit);
    152148}
    153149
  • c/src/lib/libbsp/m68k/idp/clock/ckinit.c

    rbdb2899 r0dd1d44  
    9797  Clock_isrs = (int)(Configuration.microseconds_per_tick / 1000);
    9898
    99   if ( Configuration.ticks_per_timeslice ) {
    10099/*    led_putnum('c'); * for debugging purposes */
    101100    Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    102101
    103         /* Disable timer for initialization */
    104         MC68230_WRITE (TCR, 0x00);
     102  /* Disable timer for initialization */
     103  MC68230_WRITE (TCR, 0x00);
    105104
    106         /* some PI/T initialization stuff here -- see comment in the ckisr.c
    107            file in this directory to understand why I use the values that I do */
    108         /* Set up the interrupt vector on the MC68230 chip:
    109                 TIVR = CLOCK_VECTOR; */
    110         MC68230_WRITE (TIVR, CLOCK_VECTOR);
     105  /* some PI/T initialization stuff here -- see comment in the ckisr.c
     106     file in this directory to understand why I use the values that I do */
     107  /* Set up the interrupt vector on the MC68230 chip:
     108  TIVR = CLOCK_VECTOR; */
     109  MC68230_WRITE (TIVR, CLOCK_VECTOR);
    111110
    112         /* Set CPRH through CPRL to 193 (not 203) decimal for countdown--see ckisr.c
    113                 CPRH = 0x00;
    114                 CPRM = 0x00;
    115                 CPRL = 0xC1; */
    116         MC68230_WRITE (CPRH, 0x00);
    117         MC68230_WRITE (CPRM, 0x00);
    118         MC68230_WRITE (CPRL, 0xC1);
     111  /* Set CPRH through CPRL to 193 (not 203) decimal for countdown--see ckisr.c
     112        CPRH = 0x00;
     113        CPRM = 0x00;
     114        CPRL = 0xC1; */
     115  MC68230_WRITE (CPRH, 0x00);
     116  MC68230_WRITE (CPRM, 0x00);
     117  MC68230_WRITE (CPRL, 0xC1);
    119118
    120         /* Enable timer and use it as an external periodic interrupt generator
    121                 TCR = 0xA1; */
     119  /* Enable timer and use it as an external periodic interrupt generator
     120        TCR = 0xA1; */
    122121/*    led_putnum('a'); * for debugging purposes */
    123         MC68230_WRITE (TCR, 0xA1);
     122  MC68230_WRITE (TCR, 0xA1);
    124123
    125         /*
    126          *  Schedule the clock cleanup routine to execute if the application exits.
    127          */
    128     atexit( Clock_exit );
    129   }
     124  /*
     125   *  Schedule the clock cleanup routine to execute if the application exits.
     126   */
     127  atexit( Clock_exit );
    130128}
    131129
     
    135133  rtems_unsigned8 data;
    136134
    137   if ( Configuration.ticks_per_timeslice ) {
     135  /* disable timer
     136        data = TCR;
     137        TCR = (data & 0xFE); */
     138  MC68230_READ (TCR, data);
     139  MC68230_WRITE (TCR, (data & 0xFE));
    138140
    139         /* disable timer
    140                 data = TCR;
    141                 TCR = (data & 0xFE); */
    142         MC68230_READ (TCR, data);
    143         MC68230_WRITE (TCR, (data & 0xFE));
    144 
    145     /* do not restore old vector */
    146   }
     141  /* do not restore old vector */
    147142}
    148143
  • c/src/lib/libbsp/m68k/mvme136/clock/ckinit.c

    rbdb2899 r0dd1d44  
    8282  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    8383
    84   if ( BSP_Configuration.ticks_per_timeslice ) {
    85     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    86     timer = (struct z8036_map *) 0xfffb0000;
    87     timer->MASTER_INTR        = MICRVAL;
    88     timer->CT1_MODE_SPEC      = T1MSRVAL;
     84  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     85  timer = (struct z8036_map *) 0xfffb0000;
     86  timer->MASTER_INTR        = MICRVAL;
     87  timer->CT1_MODE_SPEC      = T1MSRVAL;
    8988
    90     *((rtems_unsigned16 *)0xfffb0016) = MS_COUNT;  /* write countdown value */
     89  *((rtems_unsigned16 *)0xfffb0016) = MS_COUNT;  /* write countdown value */
    9190
    92     /*
    93      *  timer->CT1_TIME_CONST_MSB = (MS_COUNT >> 8);
    94      *  timer->CT1_TIME_CONST_LSB = (MS_COUNT &  0xff);
    95      */
     91  /*
     92   *  timer->CT1_TIME_CONST_MSB = (MS_COUNT >> 8);
     93   *  timer->CT1_TIME_CONST_LSB = (MS_COUNT &  0xff);
     94   */
    9695
    97     timer->MASTER_CFG         = MCCRVAL;
    98     timer->CT1_CMD_STATUS     = T1CSRVAL;
     96  timer->MASTER_CFG         = MCCRVAL;
     97  timer->CT1_CMD_STATUS     = T1CSRVAL;
    9998
    100     /*
    101      * Enable interrupt via VME interrupt mask register
    102      */
    103     (*(rtems_unsigned8 *)0xfffb0038) &= 0xfd;
     99  /*
     100   * Enable interrupt via VME interrupt mask register
     101   */
     102  (*(rtems_unsigned8 *)0xfffb0038) &= 0xfd;
    104103
    105     atexit( Clock_exit );
    106   }
    107 
     104  atexit( Clock_exit );
    108105}
    109106
     
    112109  volatile struct z8036_map *timer;
    113110
    114   if ( BSP_Configuration.ticks_per_timeslice ) {
    115     timer = (struct z8036_map *) 0xfffb0000;
    116     timer->MASTER_INTR        = 0x62;
    117     timer->CT1_MODE_SPEC      = 0x00;
    118     timer->MASTER_CFG         = 0xf4;
    119     timer->CT1_CMD_STATUS     = 0x00;
    120     /* do not restore old vector */
    121   }
     111  timer = (struct z8036_map *) 0xfffb0000;
     112  timer->MASTER_INTR        = 0x62;
     113  timer->CT1_MODE_SPEC      = 0x00;
     114  timer->MASTER_CFG         = 0xf4;
     115  timer->CT1_CMD_STATUS     = 0x00;
     116  /* do not restore old vector */
    122117}
    123118
  • c/src/lib/libbsp/m68k/mvme147/clock/ckinit.c

    rbdb2899 r0dd1d44  
    6868  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    6969
    70   if ( BSP_Configuration.ticks_per_timeslice ) {
    71     Old_ticker =
    72       (rtems_isr_entry) set_vector( clock_isr, TIMER_2_VECTOR, 1 );
     70  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, TIMER_2_VECTOR, 1 );
    7371
    74     pcc->timer2_int_control = 0x00; /* Disable T2 Interr. */
    75     pcc->timer2_preload = MS_COUNT;
    76     /* write preload value */
    77     pcc->timer2_control = 0x07; /* clear T2 overflow counter, enable counter */
    78     pcc->timer2_int_control = CLOCK_INT_LEVEL|0x08;
    79     /* Enable Timer 2 and set its int. level */
     72  pcc->timer2_int_control = 0x00; /* Disable T2 Interr. */
     73  pcc->timer2_preload = MS_COUNT;
     74  /* write preload value */
     75  pcc->timer2_control = 0x07; /* clear T2 overflow counter, enable counter */
     76  pcc->timer2_int_control = CLOCK_INT_LEVEL|0x08;
     77  /* Enable Timer 2 and set its int. level */
    8078   
    81     atexit( Clock_exit );
    82   }
     79  atexit( Clock_exit );
    8380}
    8481
    8582void Clock_exit( void )
    8683{
    87   if ( BSP_Configuration.ticks_per_timeslice ) {
    88     pcc->timer2_int_control = 0x00; /* Disable T2 Interr. */
    89   }
     84  pcc->timer2_int_control = 0x00; /* Disable T2 Interr. */
    9085}
    9186
  • c/src/lib/libbsp/m68k/mvme162/clock/ckinit.c

    rbdb2899 r0dd1d44  
    7272  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    7373
    74   if ( BSP_Configuration.ticks_per_timeslice ) {
    75     Old_ticker =
    76       (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    77     lcsr->vector_base |= MASK_INT;   /* unmask VMEchip2 interrupts */
    78     lcsr->to_ctl = 0xE7;             /* prescaler to 1 MHz (see Appendix A1) */
    79     lcsr->timer_cmp_2 = MS_COUNT;
    80     lcsr->timer_cnt_2 = 0;           /* clear counter */
    81     lcsr->board_ctl |= 0x700;        /* increment, reset-on-compare, and */
    82                                      /*   clear-overflow-cnt */
     74  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     75  lcsr->vector_base |= MASK_INT;   /* unmask VMEchip2 interrupts */
     76  lcsr->to_ctl = 0xE7;             /* prescaler to 1 MHz (see Appendix A1) */
     77  lcsr->timer_cmp_2 = MS_COUNT;
     78  lcsr->timer_cnt_2 = 0;           /* clear counter */
     79  lcsr->board_ctl |= 0x700;        /* increment, reset-on-compare, and */
     80                                   /*   clear-overflow-cnt */
    8381
    84     lcsr->intr_level[0] |= CLOCK_INT_LEVEL * 0x10;      /* set int level */
    85     lcsr->intr_ena |= 0x02000000;       /* enable tick timer 2 interrupt */
     82  lcsr->intr_level[0] |= CLOCK_INT_LEVEL * 0x10;      /* set int level */
     83  lcsr->intr_ena |= 0x02000000;       /* enable tick timer 2 interrupt */
    8684
    87     atexit( Clock_exit );
    88   }
     85  atexit( Clock_exit );
    8986}
    9087
  • c/src/lib/libbsp/m68k/mvme167/clock/ckinit.c

    rbdb2899 r0dd1d44  
    157157  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    158158
    159   if ( BSP_Configuration.ticks_per_timeslice ) {
    160     lcsr->intr_ena &= 0xFDFFFFFF;   /* Disable tick timer 2 interrupt */
    161     lcsr->intr_clear = 0x02000000;  /* Clear tick timer 2 interrupt */
    162     lcsr->intr_level[0] =           /* Set tick timer 2 interrupt level */
    163         (lcsr->intr_level[0] & 0xFFFFFF0F ) | (CLOCK_INT_LEVEL << 4);
    164     lcsr->timer_cmp_2 = MS_COUNT;   /* Period in compare register */
    165     lcsr->timer_cnt_2 = 0;          /* Clear tick timer 2 counter */
    166     Old_ticker =                    /* Install C ISR */
    167         (rtems_isr_entry) set_vector( VMEchip2_T2_isr, CLOCK_VECTOR, 1 );
    168     lcsr->board_ctl |= 0x700;       /* Start tick timer 2, reset-on-compare, */
    169                                     /*  and clear tick timer 2 overflow counter */
    170     lcsr->intr_ena |= 0x02000000;   /* Enable tick timer 2 interrupt */
    171     lcsr->vector_base |= 0x00800000;/* Unmask VMEchip2 interrupts */
    172     atexit( clock_exit );           /* Turn off T2 interrupts when we exit */
    173   }
     159  lcsr->intr_ena &= 0xFDFFFFFF;   /* Disable tick timer 2 interrupt */
     160  lcsr->intr_clear = 0x02000000;  /* Clear tick timer 2 interrupt */
     161  lcsr->intr_level[0] =           /* Set tick timer 2 interrupt level */
     162      (lcsr->intr_level[0] & 0xFFFFFF0F ) | (CLOCK_INT_LEVEL << 4);
     163  lcsr->timer_cmp_2 = MS_COUNT;   /* Period in compare register */
     164  lcsr->timer_cnt_2 = 0;          /* Clear tick timer 2 counter */
     165  Old_ticker =                    /* Install C ISR */
     166      (rtems_isr_entry) set_vector( VMEchip2_T2_isr, CLOCK_VECTOR, 1 );
     167  lcsr->board_ctl |= 0x700;       /* Start tick timer 2, reset-on-compare, */
     168                                  /*  and clear tick timer 2 overflow counter */
     169  lcsr->intr_ena |= 0x02000000;   /* Enable tick timer 2 interrupt */
     170  lcsr->vector_base |= 0x00800000;/* Unmask VMEchip2 interrupts */
     171  atexit( clock_exit );           /* Turn off T2 interrupts when we exit */
    174172}
    175173
     
    190188void clock_exit( void )
    191189{
    192   if ( BSP_Configuration.ticks_per_timeslice ) {
    193     lcsr->board_ctl &= 0xFFFFFEFF;  /* Stop tick timer 2 */
    194     lcsr->intr_ena &= 0xFDFFFFFF;   /* Disable tick timer 2 interrupt */
    195     lcsr->intr_clear = 0x02000000;  /* Clear tick timer 2 interrupt */
    196 
    197     set_vector( Old_ticker, CLOCK_VECTOR, 1 );
    198   }
     190  lcsr->board_ctl &= 0xFFFFFEFF;  /* Stop tick timer 2 */
     191  lcsr->intr_ena &= 0xFDFFFFFF;   /* Disable tick timer 2 interrupt */
     192  lcsr->intr_clear = 0x02000000;  /* Clear tick timer 2 interrupt */
     193
     194  set_vector( Old_ticker, CLOCK_VECTOR, 1 );
    199195}
    200196
  • c/src/lib/libbsp/m68k/ods68302/clock/ckinit.c

    rbdb2899 r0dd1d44  
    8888  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    8989
    90   if ( BSP_Configuration.ticks_per_timeslice ) {
    91    set_vector( clock_isr, CLOCK_VECTOR, 1 );
     90  set_vector( clock_isr, CLOCK_VECTOR, 1 );
    9291
    93     m302.reg.trr1 = TRR1_VAL;           /* set timer reference register */
    94     m302.reg.tmr1 = TMR1_VAL;           /* set timer mode register & enable */
    95     /*
    96      * Enable TIMER1 interrupts only.
    97      */
    98     m302.reg.imr  = RBIT_IMR_TIMER1;    /* set 68302 int-mask to allow ints */
     92  m302.reg.trr1 = TRR1_VAL;             /* set timer reference register */
     93  m302.reg.tmr1 = TMR1_VAL;             /* set timer mode register & enable */
     94  /*
     95   * Enable TIMER1 interrupts only.
     96   */
     97  m302.reg.imr  = RBIT_IMR_TIMER1;      /* set 68302 int-mask to allow ints */
    9998
    100     atexit( Clock_exit );
    101   }
     99  atexit( Clock_exit );
    102100}
    103101
    104102void Clock_exit( void )
    105103{
    106   if ( BSP_Configuration.ticks_per_timeslice ) {
    107     /* TODO: figure out what to do here */
    108     /* do not restore old vector */
    109   }
     104  /* TODO: figure out what to do here */
     105  /* do not restore old vector */
    110106}
    111107
  • c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c

    rbdb2899 r0dd1d44  
    9999  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
    100100
     101  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    101102  /*
    102    *  If ticks_per_timeslice is configured as non-zero, then the user
    103    *  wants a clock tick.
     103   *  Hardware specific initialize goes here
    104104   */
    105105
    106   if ( BSP_Configuration.ticks_per_timeslice ) {
    107     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    108     /*
    109      *  Hardware specific initialize goes here
    110      */
    111 
    112     /* XXX */
    113   }
     106  /* XXX */
    114107
    115108  /*
     
    126119void Clock_exit( void )
    127120{
    128   if ( BSP_Configuration.ticks_per_timeslice ) {
     121  /* XXX: turn off the timer interrupts */
    129122
    130     /* XXX: turn off the timer interrupts */
    131 
    132     /* XXX: If necessary, restore the old vector */
    133   }
     123  /* XXX: If necessary, restore the old vector */
    134124}
    135125
  • c/src/lib/libbsp/powerpc/dmv177/clock/clock.c

    rbdb2899 r0dd1d44  
    120120  Clock_driver_ticks = 0;
    121121
    122   if ( BSP_Configuration.ticks_per_timeslice ) {
    123     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    124 
    125     PPC_Set_decrementer( Clock_Decrementer_value );
    126 
    127     atexit( Clock_exit );
    128   }
     122  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     123
     124  PPC_Set_decrementer( Clock_Decrementer_value );
     125
     126  atexit( Clock_exit );
    129127}
    130128
     
    146144void Clock_exit( void )
    147145{
    148   if ( BSP_Configuration.ticks_per_timeslice ) {
    149 
    150     /* nothing to do */;
    151 
    152     /* do not restore old vector */
    153   }
     146  /* nothing to do */;
     147
     148  /* do not restore old vector */
    154149}
    155150 
  • c/src/lib/libbsp/powerpc/ppcn_60x/clock/clock.c

    rbdb2899 r0dd1d44  
    118118  Clock_driver_ticks = 0;
    119119
    120   if ( BSP_Configuration.ticks_per_timeslice ) {
    121     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    122 
    123     PPC_Set_decrementer( Clock_Decrementer_value );
    124 
    125     atexit( Clock_exit );
    126   }
     120  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     121
     122  PPC_Set_decrementer( Clock_Decrementer_value );
     123
     124  atexit( Clock_exit );
    127125}
    128126
     
    143141void Clock_exit( void )
    144142{
    145   if ( BSP_Configuration.ticks_per_timeslice ) {
    146 
    147     /* nothing to do */;
    148 
    149     /* do not restore old vector */
    150   }
     143  /* nothing to do */;
     144
     145  /* do not restore old vector */
    151146}
    152147 
  • c/src/lib/libbsp/powerpc/psim/clock/clock.c

    rbdb2899 r0dd1d44  
    123123  Clock_driver_ticks = 0;
    124124
    125   if ( BSP_Configuration.ticks_per_timeslice ) {
    126     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    127 
    128     PPC_Set_decrementer( CPU_PPC_CLICKS_PER_TICK );
    129 
    130     atexit( Clock_exit );
    131   }
    132 
     125  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     126
     127  PPC_Set_decrementer( CPU_PPC_CLICKS_PER_TICK );
     128
     129  atexit( Clock_exit );
    133130}
    134131
     
    149146void Clock_exit( void )
    150147{
    151   if ( BSP_Configuration.ticks_per_timeslice ) {
    152 
    153     /* nothing to do */;
    154 
    155     /* do not restore old vector */
    156   }
     148  /* nothing to do */;
     149
     150  /* do not restore old vector */
    157151}
    158152 
  • c/src/lib/libbsp/powerpc/score603e/clock/clock.c

    rbdb2899 r0dd1d44  
    118118  Clock_driver_ticks = 0;
    119119
    120   if ( BSP_Configuration.ticks_per_timeslice ) {
    121     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    122 
    123     PPC_Set_decrementer( Clock_Decrementer_value );
    124 
    125     atexit( Clock_exit );
    126   }
     120  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     121
     122  PPC_Set_decrementer( Clock_Decrementer_value );
     123
     124  atexit( Clock_exit );
    127125}
    128126
     
    143141void Clock_exit( void )
    144142{
    145   if ( BSP_Configuration.ticks_per_timeslice ) {
    146 
    147     /* nothing to do */;
    148 
    149     /* do not restore old vector */
    150   }
     143  /* nothing to do */;
     144
     145  /* do not restore old vector */
    151146}
    152147 
  • c/src/lib/libbsp/sparc/erc32/clock/ckinit.c

    rbdb2899 r0dd1d44  
    129129  Clock_driver_ticks = 0;
    130130
    131   if ( BSP_Configuration.ticks_per_timeslice ) {
    132     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    133 
    134     /* approximately 1 us per countdown */
    135     ERC32_MEC.Real_Time_Clock_Scalar  = CLOCK_SPEED - 1;
    136     ERC32_MEC.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
    137 
    138     ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
    139       ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
    140         ERC32_MEC_TIMER_COUNTER_LOAD_SCALER |
    141         ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
    142     );
    143  
    144     ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
    145       ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
    146         ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO
    147     );
    148 
    149     atexit( Clock_exit );
    150   }
    151 
     131  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     132
     133  /* approximately 1 us per countdown */
     134  ERC32_MEC.Real_Time_Clock_Scalar  = CLOCK_SPEED - 1;
     135  ERC32_MEC.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
     136
     137  ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
     138    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
     139      ERC32_MEC_TIMER_COUNTER_LOAD_SCALER |
     140      ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
     141  );
     142 
     143  ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
     144    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
     145      ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO
     146  );
     147
     148  atexit( Clock_exit );
    152149}
    153150
     
    168165void Clock_exit( void )
    169166{
    170   if ( BSP_Configuration.ticks_per_timeslice ) {
    171     ERC32_Mask_interrupt( ERC32_INTERRUPT_REAL_TIME_CLOCK );
    172 
    173     ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
    174       ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING
    175     );
    176 
    177     /* do not restore old vector */
    178   }
     167  ERC32_Mask_interrupt( ERC32_INTERRUPT_REAL_TIME_CLOCK );
     168
     169  ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
     170    ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING
     171  );
     172
     173  /* do not restore old vector */
    179174}
    180175 
  • c/src/lib/libcpu/hppa1.1/clock/clock.c

    rbdb2899 r0dd1d44  
    102102    Clock_isrs = rtems_configuration_get_milliseconds_per_tick();
    103103
    104     if ( rtems_configuration_get_ticks_per_timeslice() ) {
    105         /*
    106          * initialize the interval here
    107          * First tick is set to right amount of time in the future
    108          * Future ticks will be incremented over last value set
    109          * in order to provide consistent clicks in the face of
    110          * interrupt overhead
    111          */
    112 
    113         Clock_clicks_interrupt = Clock_read_itimer() + CPU_HPPA_CLICKS_PER_TICK;
    114         set_itimer((rtems_unsigned32) Clock_clicks_interrupt);
    115 
    116         (void) set_vector(clock_isr, HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER, 1);
    117     }
     104    /*
     105     * initialize the interval here
     106     * First tick is set to right amount of time in the future
     107     * Future ticks will be incremented over last value set
     108     * in order to provide consistent clicks in the face of
     109     * interrupt overhead
     110     */
     111
     112    Clock_clicks_interrupt = Clock_read_itimer() + CPU_HPPA_CLICKS_PER_TICK;
     113    set_itimer((rtems_unsigned32) Clock_clicks_interrupt);
     114
     115    (void) set_vector(clock_isr, HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER, 1);
    118116    atexit(Clock_exit);
    119117}
     
    187185Clock_exit(void)
    188186{
    189     if ( rtems_configuration_get_ticks_per_timeslice() ) {
    190         (void) set_vector(0, HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER, 1);
    191     }
     187  (void) set_vector(0, HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER, 1);
    192188}
    193189
  • c/src/lib/libcpu/mips/clock/ckinit.c

    rbdb2899 r0dd1d44  
    161161  Clock_isrs = rtems_configuration_get_milliseconds_per_tick();
    162162
    163   /*
    164    *  If ticks_per_timeslice is configured as non-zero, then the user
    165    *  wants a clock tick.
    166    */
    167 
    168   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    169     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    170     /*
    171      *  Hardware specific initialize goes here
    172      */
    173 
    174     mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
    175     mips_set_timer( mips_timer_rate );
    176     enable_int(CLOCK_VECTOR_MASK);
    177   }
     163  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     164  /*
     165   *  Hardware specific initialize goes here
     166   */
     167
     168  mips_timer_rate =
     169     rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
     170  mips_set_timer( mips_timer_rate );
     171  enable_int(CLOCK_VECTOR_MASK);
    178172
    179173  /*
     
    190184void Clock_exit( void )
    191185{
    192   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    193     /* mips: turn off the timer interrupts */
    194     disable_int(~CLOCK_VECTOR_MASK);
    195   }
     186  /* mips: turn off the timer interrupts */
     187  disable_int(~CLOCK_VECTOR_MASK);
    196188}
    197189
  • c/src/lib/libcpu/mips64orion/clock/ckinit.c

    rbdb2899 r0dd1d44  
    161161  Clock_isrs = rtems_configuration_get_milliseconds_per_tick();
    162162
    163   /*
    164    *  If ticks_per_timeslice is configured as non-zero, then the user
    165    *  wants a clock tick.
    166    */
    167 
    168   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    169     Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
    170     /*
    171      *  Hardware specific initialize goes here
    172      */
    173 
    174     mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
    175     mips_set_timer( mips_timer_rate );
    176     enable_int(CLOCK_VECTOR_MASK);
    177   }
     163  Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
     164  /*
     165   *  Hardware specific initialize goes here
     166   */
     167
     168  mips_timer_rate =
     169     rtems_configuration_get_microseconds_per_tick() * CLOCKS_PER_MICROSECOND;
     170  mips_set_timer( mips_timer_rate );
     171  enable_int(CLOCK_VECTOR_MASK);
    178172
    179173  /*
     
    190184void Clock_exit( void )
    191185{
    192   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    193     /* mips: turn off the timer interrupts */
    194     disable_int(~CLOCK_VECTOR_MASK);
    195   }
     186  /* mips: turn off the timer interrupts */
     187  disable_int(~CLOCK_VECTOR_MASK);
    196188}
    197189
  • c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c

    rbdb2899 r0dd1d44  
    4949void clockOff(void* unused)
    5050{
    51   if (BSP_Configuration.ticks_per_timeslice)    {
    52     /*
    53      * Nothing to do as we cannot disable all interrupts and
    54      * the decrementer interrupt enable is MSR_EE
    55      */
    56   }
     51  /*
     52   * Nothing to do as we cannot disable all interrupts and
     53   * the decrementer interrupt enable is MSR_EE
     54   */
    5755}
    5856void clockOn(void* unused)
     
    117115void Clock_exit( void )
    118116{
    119   if ( BSP_Configuration.ticks_per_timeslice ) {
    120    (void) BSP_disconnect_clock_handler ();
    121   }
     117  (void) BSP_disconnect_clock_handler ();
    122118}
    123119 
  • c/src/lib/libcpu/powerpc/mpc821/clock/clock.c

    rbdb2899 r0dd1d44  
    8282    rtems_fatal_error_occurred(-1);
    8383  } 
    84   if ( rtems_configuration_get_ticks_per_timeslice() ) {
     84
     85  /*
     86   * initialize the interval here
     87   * First tick is set to right amount of time in the future
     88   * Future ticks will be incremented over last value set
     89   * in order to provide consistent clicks in the face of
     90   * interrupt overhead
     91   */
     92 
     93  rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
    8594   
    86     /*
    87      * initialize the interval here
    88      * First tick is set to right amount of time in the future
    89      * Future ticks will be incremented over last value set
    90      * in order to provide consistent clicks in the face of
    91      * interrupt overhead
    92      */
     95  m821.sccr &= ~(1<<24);
     96  m821.pitc = pit_value;
    9397   
    94     rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
     98  /* set PIT irq level, enable PIT, PIT interrupts */
     99  /*  and clear int. status */
     100  m821.piscr = M821_PISCR_PIRQ(0) |
     101    M821_PISCR_PTE | M821_PISCR_PS | M821_PISCR_PIE;
    95102   
    96     m821.sccr &= ~(1<<24);
    97     m821.pitc = pit_value;
    98    
    99     /* set PIT irq level, enable PIT, PIT interrupts */
    100     /*  and clear int. status */
    101     m821.piscr = M821_PISCR_PIRQ(0) |
    102       M821_PISCR_PTE | M821_PISCR_PS | M821_PISCR_PIE;
    103    
    104     m821.simask |= M821_SIMASK_LVM0;
    105   }
     103  m821.simask |= M821_SIMASK_LVM0;
    106104  atexit(Clock_exit);
    107105}
     
    128126Clock_exit(void)
    129127{
    130   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    131     /* disable PIT and PIT interrupts */
    132     m821.piscr &= ~(M821_PISCR_PTE | M821_PISCR_PIE);
    133    
    134     (void) set_vector(0, PPC_IRQ_LVL0, 1);
    135   }
     128  /* disable PIT and PIT interrupts */
     129  m821.piscr &= ~(M821_PISCR_PTE | M821_PISCR_PIE);
     130 
     131  (void) set_vector(0, PPC_IRQ_LVL0, 1);
    136132}
    137133
  • c/src/lib/libcpu/powerpc/mpc860/clock/clock.c

    rbdb2899 r0dd1d44  
    8383    rtems_fatal_error_occurred(-1);
    8484  } 
    85   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    8685   
    87     /*
    88      * initialize the interval here
    89      * First tick is set to right amount of time in the future
    90      * Future ticks will be incremented over last value set
    91      * in order to provide consistent clicks in the face of
    92      * interrupt overhead
    93      */
     86  /*
     87   * initialize the interval here
     88   * First tick is set to right amount of time in the future
     89   * Future ticks will be incremented over last value set
     90   * in order to provide consistent clicks in the face of
     91   * interrupt overhead
     92   */
     93 
     94  rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
    9495   
    95     rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
     96  m860.sccr &= ~(1<<24);
     97  m860.pitc = pit_value;
    9698   
    97     m860.sccr &= ~(1<<24);
    98     m860.pitc = pit_value;
     99  /* set PIT irq level, enable PIT, PIT interrupts */
     100  /*  and clear int. status */
     101  m860.piscr = M860_PISCR_PIRQ(0) |
     102    M860_PISCR_PTE | M860_PISCR_PS | M860_PISCR_PIE;
    99103   
    100     /* set PIT irq level, enable PIT, PIT interrupts */
    101     /*  and clear int. status */
    102     m860.piscr = M860_PISCR_PIRQ(0) |
    103       M860_PISCR_PTE | M860_PISCR_PS | M860_PISCR_PIE;
    104    
    105     m860.simask |= M860_SIMASK_LVM0;
    106   }
     104  m860.simask |= M860_SIMASK_LVM0;
    107105  atexit(Clock_exit);
    108106}
     
    129127Clock_exit(void)
    130128{
    131   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    132     /* disable PIT and PIT interrupts */
    133     m860.piscr &= ~(M860_PISCR_PTE | M860_PISCR_PIE);
     129  /* disable PIT and PIT interrupts */
     130  m860.piscr &= ~(M860_PISCR_PTE | M860_PISCR_PIE);
    134131   
    135     (void) set_vector(0, PPC_IRQ_LVL0, 1);
    136   }
     132  (void) set_vector(0, PPC_IRQ_LVL0, 1);
    137133}
    138134
  • c/src/lib/libcpu/powerpc/ppc403/clock/clock.c

    rbdb2899 r0dd1d44  
    133133    rtems_isr_entry previous_isr;
    134134    rtems_unsigned32 pvr, iocr;
     135    register rtems_unsigned32 tcr;
    135136 
    136137    Clock_driver_ticks = 0;
     
    165166      rtems_cpu_configuration_get_clicks_per_usec();
    166167 
    167     if ( rtems_configuration_get_ticks_per_timeslice() ) {
    168       register rtems_unsigned32 tcr;
    169 
    170         /*
    171          * initialize the interval here
    172          * First tick is set to right amount of time in the future
    173          * Future ticks will be incremented over last value set
    174          * in order to provide consistent clicks in the face of
    175          * interrupt overhead
    176          */
    177  
    178       rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr);
    179  
    180       asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
    181  
    182       asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    183  
    184       tcr &= ~ 0x04400000;
    185  
    186       tcr |= (auto_restart ? 0x04400000 : 0x04000000);
    187  
    188       tick_time = get_itimer() + pit_value;
    189  
    190       asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    191     }
     168
     169    /*
     170     * initialize the interval here
     171     * First tick is set to right amount of time in the future
     172     * Future ticks will be incremented over last value set
     173     * in order to provide consistent clicks in the face of
     174     * interrupt overhead
     175     */
     176
     177    rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr);
     178
     179    asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
     180 
     181    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     182 
     183    tcr &= ~ 0x04400000;
     184 
     185    tcr |= (auto_restart ? 0x04400000 : 0x04000000);
     186 
     187    tick_time = get_itimer() + pit_value;
     188 
     189    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     190
    192191    atexit(Clock_exit);
    193192}
     
    215214Clock_exit(void)
    216215{
    217     if ( rtems_configuration_get_ticks_per_timeslice() ) {
    218       register rtems_unsigned32 tcr;
    219  
    220       asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    221  
    222       tcr &= ~ 0x04400000;
    223  
    224       asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    225  
    226       (void) set_vector(0, PPC_IRQ_PIT, 1);
    227     }
    228 
     216    register rtems_unsigned32 tcr;
     217 
     218    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     219 
     220    tcr &= ~ 0x04400000;
     221 
     222    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     223 
     224    (void) set_vector(0, PPC_IRQ_PIT, 1);
    229225}
    230226
  • c/src/lib/libcpu/sh/sh7032/clock/ckinit.c

    rbdb2899 r0dd1d44  
    224224  Clock_isrs = Clock_isrs_const;
    225225
    226   /*
    227    *  If ticks_per_timeslice is configured as non-zero, then the user
    228    *  wants a clock tick.
    229    */
    230 
    231   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    232     rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
    233     /*
    234      *  Hardware specific initialize goes here
    235      */
     226  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
     227  /*
     228   *  Hardware specific initialize goes here
     229   */
     230 
     231  /* stop Timer 0 */
     232  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
     233  write8( temp8, ITU_TSTR);
     234
     235  /* set initial counter value to 0 */
     236  write16( 0, ITU_TCNT0);
     237
     238  /* Timer 0 runs independent */
     239  temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK;
     240  write8( temp8, ITU_TSNC);
     241
     242  /* Timer 0 normal mode */
     243  temp8 = read8( ITU_TMDR) & ITU0_MODEMASK;
     244  write8( temp8, ITU_TMDR);
     245
     246  /* TCNT is cleared by GRA ; internal clock /4 */
     247  write8( ITU0_TCRMASK , ITU_TCR0);
     248
     249  /* use GRA without I/O - pins  */
     250  write8( ITU0_TIORVAL, ITU_TIOR0);
    236251   
    237     /* stop Timer 0 */
    238     temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
    239     write8( temp8, ITU_TSTR);
    240 
    241     /* set initial counter value to 0 */
    242     write16( 0, ITU_TCNT0);
    243 
    244     /* Timer 0 runs independent */
    245     temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK;
    246     write8( temp8, ITU_TSNC);
    247 
    248     /* Timer 0 normal mode */
    249     temp8 = read8( ITU_TMDR) & ITU0_MODEMASK;
    250     write8( temp8, ITU_TMDR);
    251 
    252     /* TCNT is cleared by GRA ; internal clock /4 */
    253     write8( ITU0_TCRMASK , ITU_TCR0);
    254 
    255     /* use GRA without I/O - pins  */
    256     write8( ITU0_TIORVAL, ITU_TIOR0);
    257    
    258     /* reset flags of the status register */
    259     temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
    260     write8( temp8, ITU_TSR0);
    261 
    262     /* Irq if is equal GRA */
    263     temp8 = read8( ITU_TIER0) | ITU0_TIERMASK;
    264     write8( temp8, ITU_TIER0);
    265 
    266     /* set interrupt priority */
    267     if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
    268       rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
    269 
    270     /* set counter limits */
    271     write16( Clock_limit, ITU_GRA0);
     252  /* reset flags of the status register */
     253  temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
     254  write8( temp8, ITU_TSR0);
     255
     256  /* Irq if is equal GRA */
     257  temp8 = read8( ITU_TIER0) | ITU0_TIERMASK;
     258  write8( temp8, ITU_TIER0);
     259
     260  /* set interrupt priority */
     261  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
     262    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
     263
     264  /* set counter limits */
     265  write16( Clock_limit, ITU_GRA0);
    272266   
    273     /* start counter */
    274     temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
    275     write8( temp8, ITU_TSTR);
    276    
    277   }
     267  /* start counter */
     268  temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
     269  write8( temp8, ITU_TSTR);
    278270
    279271  /*
     
    291283{
    292284  unsigned8 temp8 = 0;
    293   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    294 
    295     /* turn off the timer interrupts */
    296     /* set interrupt priority to 0 */
    297     if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
    298       rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
     285
     286  /* turn off the timer interrupts */
     287  /* set interrupt priority to 0 */
     288  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
     289    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
    299290
    300291/*
     
    303294 */
    304295
    305     /* stop counter */
    306     temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
    307     write8( temp8, ITU_TSTR);
    308 
    309     /* old vector shall not be installed */
    310   }
     296  /* stop counter */
     297  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
     298  write8( temp8, ITU_TSTR);
     299
     300  /* old vector shall not be installed */
    311301}
    312302
  • c/src/lib/libcpu/sh/sh7045/clock/ckinit.c

    rbdb2899 r0dd1d44  
    162162  Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
    163163
    164   /*
    165    *  If ticks_per_timeslice is configured as non-zero, then the user
    166    *  wants a clock tick.
    167    */
    168 
    169   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    170     rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
    171     /*
    172      *  Hardware specific initialize goes here
    173      */
     164  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
     165
     166  /*
     167   *  Hardware specific initialize goes here
     168   */
    174169   
    175     /* stop Timer 0 */
    176     temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
    177     write8( temp8, MTU_TSTR);
    178 
    179     /* set initial counter value to 0 */
    180     write16( 0, MTU_TCNT0);
    181 
    182     /* Timer 0 runs independent */
    183     temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
    184     write8( temp8, MTU_TSYR);
    185 
    186     /* Timer 0 normal mode */
    187     temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
    188     write8( temp8, MTU_TMDR0);
    189 
    190     /* TCNT is cleared by GRA ; internal clock /4 */
    191     write8( MTU0_TCRMASK , MTU_TCR0);
    192 
    193     /* use GRA without I/O - pins  */
    194     write8( MTU0_TIORVAL, MTU_TIORL0);
     170  /* stop Timer 0 */
     171  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
     172  write8( temp8, MTU_TSTR);
     173
     174  /* set initial counter value to 0 */
     175  write16( 0, MTU_TCNT0);
     176
     177  /* Timer 0 runs independent */
     178  temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
     179  write8( temp8, MTU_TSYR);
     180
     181  /* Timer 0 normal mode */
     182  temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
     183  write8( temp8, MTU_TMDR0);
     184
     185  /* TCNT is cleared by GRA ; internal clock /4 */
     186  write8( MTU0_TCRMASK , MTU_TCR0);
     187
     188  /* use GRA without I/O - pins  */
     189  write8( MTU0_TIORVAL, MTU_TIORL0);
    195190   
    196     /* reset flags of the status register */
    197     temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
    198     write8( temp8, MTU_TSR0);
    199 
    200     /* Irq if is equal GRA */
    201     temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
    202     write8( temp8, MTU_TIER0);
    203 
    204     /* set interrupt priority */
    205     if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
    206       rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
    207 
    208     /* set counter limits */
    209     write16( _MTU_COUNTER0_MICROSECOND *
    210       rtems_configuration_get_microseconds_per_tick(),
    211 
    212              MTU_GR0A);
     191  /* reset flags of the status register */
     192  temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
     193  write8( temp8, MTU_TSR0);
     194
     195  /* Irq if is equal GRA */
     196  temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
     197  write8( temp8, MTU_TIER0);
     198
     199  /* set interrupt priority */
     200  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
     201    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
     202
     203  /* set counter limits */
     204  write16( _MTU_COUNTER0_MICROSECOND *
     205    rtems_configuration_get_microseconds_per_tick(), MTU_GR0A);
    213206   
    214     /* start counter */
    215     temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
    216     write8( temp8, MTU_TSTR);
    217    
    218   }
     207  /* start counter */
     208  temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
     209  write8( temp8, MTU_TSTR);
    219210
    220211  /*
     
    232223{
    233224  unsigned8 temp8 = 0;
    234   if ( rtems_configuration_get_ticks_per_timeslice() ) {
    235 
    236     /* turn off the timer interrupts */
    237     /* set interrupt priority to 0 */
    238     if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
    239       rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
     225
     226  /* turn off the timer interrupts */
     227  /* set interrupt priority to 0 */
     228  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
     229    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
    240230
    241231/*
     
    244234 */
    245235
    246     /* stop counter */
    247     temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
    248     write8( temp8, MTU_TSTR);
    249 
    250     /* old vector shall not be installed */
    251   }
     236  /* stop counter */
     237  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
     238  write8( temp8, MTU_TSTR);
     239
     240  /* old vector shall not be installed */
    252241}
    253242
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