Ignore:
Timestamp:
May 14, 2002, 4:56:44 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
6fae458
Parents:
78f8c91
Message:

2001-05-14 Till Straumann <strauman@…>

  • rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add the following:
    • support for the MPC74000 (AKA G4); there is no AltiVec? support yet, however.
    • the cache flushing assembly code uses hardware-flush on the G4. Also, a couple of hardcoded numerical values were replaced by more readable symbolic constants.
    • extended interrupt-disabled code section so enclose the entire cache flush/invalidate procedure (as recommended by the book). This is not (latency) critical as it is only used by init code but prevents possible corruption.
    • Trivial page table support as been added. (1:1 effective-virtual-physical address mapping which is only useful only on CPUs which feature hardware TLB replacement, e.g. >604. This allows for write-protecting memory regions, e.g. text/ro-data which makes catching corruptors a lot easier. It also frees one DBAT/IBAT and gives more flexibility for setting up address maps :-)
    • setdbat() allows changing BAT0 also (since the BSP may use a page table, BAT0 could be available...).
    • asm_setdbatX() violated the SVR ABI by using r20 as a scratch register; changed for r0
    • according to the book, a context synchronizing instruction is necessary prior to and after changing a DBAT -> isync added
File:
1 edited

Legend:

Unmodified
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  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h

    r78f8c91 r0d776cd2  
    2828  PPC_604e = 0x9,
    2929  PPC_604r = 0xA,
     30  PPC_7400 = 0xA,
    3031  PPC_620 = 0x16,
    3132  PPC_860 = 0x50,
     
    3940extern ppc_cpu_id_t get_ppc_cpu_type ();
    4041extern ppc_cpu_id_t current_ppc_cpu;
     42extern char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu);
    4143extern ppc_cpu_revision_t get_ppc_cpu_revision ();
    4244extern ppc_cpu_revision_t current_ppc_revision;
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