Changeset 0d776cd2 in rtems


Ignore:
Timestamp:
05/14/02 16:56:44 (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
6fae458
Parents:
78f8c91
Message:

2001-05-14 Till Straumann <strauman@…>

  • rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add the following:
    • support for the MPC74000 (AKA G4); there is no AltiVec? support yet, however.
    • the cache flushing assembly code uses hardware-flush on the G4. Also, a couple of hardcoded numerical values were replaced by more readable symbolic constants.
    • extended interrupt-disabled code section so enclose the entire cache flush/invalidate procedure (as recommended by the book). This is not (latency) critical as it is only used by init code but prevents possible corruption.
    • Trivial page table support as been added. (1:1 effective-virtual-physical address mapping which is only useful only on CPUs which feature hardware TLB replacement, e.g. >604. This allows for write-protecting memory regions, e.g. text/ro-data which makes catching corruptors a lot easier. It also frees one DBAT/IBAT and gives more flexibility for setting up address maps :-)
    • setdbat() allows changing BAT0 also (since the BSP may use a page table, BAT0 could be available...).
    • asm_setdbatX() violated the SVR ABI by using r20 as a scratch register; changed for r0
    • according to the book, a context synchronizing instruction is necessary prior to and after changing a DBAT -> isync added
Location:
c/src/lib/libcpu/powerpc
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    r78f8c91 r0d776cd2  
     12001-05-14      Till Straumann <strauman@slac.stanford.edu>
     2
     3        * rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add
     4        the following:
     5            - support for the MPC74000 (AKA G4); there is no
     6              AltiVec support yet, however.
     7            - the cache flushing assembly code uses hardware-flush on the G4.
     8              Also, a couple of hardcoded numerical values were replaced
     9              by more readable symbolic constants.
     10            - extended interrupt-disabled code section so enclose the entire
     11              cache flush/invalidate procedure (as recommended by the book).
     12              This is not (latency) critical as it is only used by
     13              init code but prevents possible corruption.
     14            - Trivial page table support as been added.
     15              (1:1 effective-virtual-physical address mapping which is only
     16              useful only on CPUs which feature hardware TLB replacement,
     17              e.g. >604.  This allows for write-protecting memory regions,
     18              e.g. text/ro-data which makes catching corruptors a lot easier.
     19              It also frees one DBAT/IBAT and gives more flexibility
     20              for setting up address maps :-)
     21            - setdbat() allows changing BAT0 also (since the BSP may use
     22              a page table, BAT0 could be available...).
     23            - asm_setdbatX() violated the SVR ABI by using
     24              r20 as a scratch register; changed for r0
     25            - according to the book, a context synchronizing instruction is
     26              necessary prior to and after changing a DBAT -> isync added
     27
    1282002-04-30      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    229
  • c/src/lib/libcpu/powerpc/configure.ac

    r78f8c91 r0d776cd2  
    2929
    3030AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "mpc750" \
     31|| test "$RTEMS_CPU_MODEL" = "mpc7400" \
    3132|| test "$RTEMS_CPU_MODEL" = "ppc603e" \
    3233|| test "$RTEMS_CPU_MODEL" = "mpc604" \
     
    4142AM_CONDITIONAL(mpc6xx, test "$RTEMS_CPU_MODEL" = "mpc6xx" \
    4243|| test "$RTEMS_CPU_MODEL" = "mpc604" \
     44|| test "$RTEMS_CPU_MODEL" = "mpc7400" \
    4345|| test "$RTEMS_CPU_MODEL" = "mpc750" )
    4446AM_CONDITIONAL(mpc8xx, test "$RTEMS_CPU_MODEL" = "mpc8xx" \
  • c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c

    r78f8c91 r0d776cd2  
    114114{
    115115     switch (current_ppc_cpu) {
     116        case PPC_7400:
    116117        case PPC_750:
    117118            if (!mpc750_vector_is_valid(vector)) {
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/Makefile.am

    r78f8c91 r0d776cd2  
    66PGM = $(ARCH)/mmu.rel
    77
    8 C_FILES = bat.c
     8C_FILES = bat.c pte121.c
    99
    1010S_FILES = mmuAsm.S
     
    1212include_libcpudir = $(includedir)/libcpu
    1313
    14 include_libcpu_HEADERS = bat.h
     14include_libcpu_HEADERS = bat.h pte121.h
    1515
    1616mmu_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
     
    3939.PRECIOUS: $(PGM)
    4040
    41 EXTRA_DIST = bat.c bat.h mmuAsm.S
     41EXTRA_DIST = bat.c bat.h mmuAsm.S pte121.c pte121.h
    4242
    4343include $(top_srcdir)/../../../../../automake/local.am
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c

    r78f8c91 r0d776cd2  
    5656  bat_addrs[bat_index].phys = phys;
    5757  switch (bat_index) {
     58  case 0 : asm_setdbat1(bat.word[0], bat.word[1]); break;
    5859  case 1 : asm_setdbat1(bat.word[0], bat.word[1]); break;
    5960  case 2 : asm_setdbat2(bat.word[0], bat.word[1]); break;
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S

    r78f8c91 r0d776cd2  
    1313 *  http://www.OARcorp.com/rtems/license.html.
    1414 *     
     15 *  T. Straumann - 11/2001: added support for 7400 (no AltiVec yet)
    1516 */
    1617
     
    1819#include <rtems/score/cpu.h>
    1920#include <libcpu/io.h>
     21
     22/* Unfortunately, the CPU types defined in cpu.h are
     23 * an 'enum' type and hence not available :-(
     24 */
     25#define PPC_601   0x1
     26#define PPC_603   0x3
     27#define PPC_604   0x4
     28#define PPC_603e  0x6
     29#define PPC_603ev 0x7
     30#define PPC_750   0x8
     31#define PPC_604e  0x9
     32#define PPC_604r  0xA
     33#define PPC_7400  0xC
     34#define PPC_620   0x16
     35#define PPC_860   0x50
     36#define PPC_821   PPC_860
     37#define PPC_8260  0x81
     38
     39/* ALTIVEC instructions (not recognized by off-the shelf gcc yet) */
     40#define DSSALL  .long   0x7e00066c              /* DSSALL altivec instruction opcode */
     41
     42/* A couple of defines to make the code more readable */
     43#define CACHE_LINE_SIZE 32
     44
     45#ifndef MSSCR0
     46#define MSSCR0   1014
     47#else
     48#warning MSSCR0 seems to be known, update __FILE__
     49#endif
     50
     51#define DL1HWF  (1<<(31-8))
     52#define L2HWF   (1<<(31-20))
     53
     54
    2055
    2156/*
     
    2560 */
    2661
     62        .globl  asm_setdbat0
     63        .type   asm_setdbat0,@function
     64asm_setdbat0:
     65        li      r0,0
     66        sync
     67        isync
     68        mtspr   DBAT0U,r0
     69        mtspr   DBAT0L,r0
     70        sync
     71        isync
     72        mtspr DBAT0L, r4
     73        mtspr DBAT0U, r3
     74        sync
     75        isync
     76        blr
     77
    2778        .globl  asm_setdbat1
    2879        .type   asm_setdbat1,@function
    2980asm_setdbat1:
    30         li      r20,0
    31         SYNC
    32         mtspr   DBAT1U,r20
    33         mtspr   DBAT1L,r20
    34         SYNC
     81        li      r0,0
     82        sync
     83        isync
     84        mtspr   DBAT1U,r0
     85        mtspr   DBAT1L,r0
     86        sync
     87        isync
    3588        mtspr DBAT1L, r4
    3689        mtspr DBAT1U, r3
    37         SYNC
     90        sync
     91        isync
    3892        blr
    3993
     
    4195        .type   asm_setdbat2,@function
    4296asm_setdbat2:   
    43         li      r20,0
    44         SYNC
    45         mtspr   DBAT2U,r20
    46         mtspr   DBAT2L,r20
    47         SYNC
     97        li      r0,0
     98        sync
     99        isync
     100        mtspr   DBAT2U,r0
     101        mtspr   DBAT2L,r0
     102        sync
     103        isync
    48104        mtspr DBAT2L, r4
    49105        mtspr DBAT2U, r3
    50         SYNC
     106        sync
     107        isync
    51108        blr
    52109
     
    54111        .type   asm_setdbat3,@function
    55112asm_setdbat3:   
    56         li      r20,0
    57         SYNC
    58         mtspr   DBAT3U,r20
    59         mtspr   DBAT3L,r20
    60         SYNC
     113        li      r0,0
     114        sync
     115        isync
     116        mtspr   DBAT3U,r0
     117        mtspr   DBAT3L,r0
     118        sync
     119        isync
    61120        mtspr DBAT3L, r4
    62121        mtspr DBAT3U, r3
    63         SYNC
     122        sync
     123        isync
    64124        blr
    65125               
     
    73133        mfspr   r9,PVR
    74134        rlwinm  r9,r9,16,16,31
    75         cmpi    0,r9,1
     135        cmpi    0,r9,PPC_601
    76136        beq     4f                      /* not needed for 601 */
    77137        mfspr   r11,HID0
     
    88148        sync
    89149        isync
    90         cmpi    0,r9,4                  /* check for 604 */
    91         cmpi    1,r9,9                  /* or 604e */
    92         cmpi    2,r9,10                 /* or mach5 */
     150        cmpi    0,r9,PPC_604    /* check for 604 */
     151        cmpi    1,r9,PPC_604e   /* or 604e */
     152        cmpi    2,r9,PPC_604r   /* or mach5 */
    93153        cror    2,2,6
    94154        cror    2,2,10
     155        cmpi    1,r9,PPC_750    /* or 750 */
     156        cror    2,2,6
     157        cmpi    1,r9,PPC_7400   /* or 7400 */
     158        bne     3f
     159        ori     r11,r11,HID0_BTIC       /* enable branch tgt cache on 7400 */
     1603:      cror    2,2,6
    95161        bne     4f
     162        /* on 7400 SIED is actually SGE (store gathering enable) */
    96163        ori     r11,r11,HID0_SIED|HID0_BHTE /* for 604[e], enable */
    97164        bne     2,5f
     
    104171        .type  get_L2CR, @function     
    105172get_L2CR:       
    106         /* Make sure this is a 750 chip */
     173        /* Make sure this is a > 750 chip */
    107174        mfspr   r3,PVR
    108175        rlwinm  r3,r3,16,16,31
    109         cmplwi  r3,0x0008
     176        cmplwi  r3,PPC_750      /* it's a 750 */
     177        beq     1f
     178        cmplwi  r3,PPC_7400     /* it's a 7400 */
     179        beq     1f
    110180        li      r3,0
    111         bnelr
    112        
     181        blr
     182       
     1831:
    113184        /* Return the L2CR contents */
    114185        mfspr   r3,L2CR
     
    147218         */
    148219       
    149         /* Make sure this is a 750 chip */
    150         mfspr   r4,PVR
    151         rlwinm  r4,r4,16,16,31
    152         cmplwi  r4,0x0008
     220        /* Make sure this is a > 750 chip */
     221        mfspr   r0,PVR
     222        rlwinm  r0,r0,16,16,31
     223        cmplwi  r0,PPC_750
     224        beq     thisIs750
     225        cmplwi  r0,PPC_7400
    153226        beq     thisIs750
    154227        li      r3,-1
     
    162235        /* See if we want to perform a global inval this time. */
    163236        rlwinm  r6,r3,0,10,10           /* r6 contains the new invalidate bit */
    164         rlwinm. r5,r3,0,0,0             /* r5 contains the new enable bit */
     237        rlwinm. r5,r3,0,0,0                     /* r5 contains the new enable bit */
    165238        rlwinm  r3,r3,0,11,9            /* Turn off the invalidate bit */
    166239        rlwinm  r3,r3,0,1,31            /* Turn off the enable bit */
    167         or      r3,r3,r4                /* Keep the enable bit the same as it was for now. */
    168         bne     dontDisableCache        /* Only disable the cache if L2CRApply has the enable bit off */
     240        or              r3,r3,r4                        /* Keep the enable bit the same as it was for now. */
     241        mfmsr   r7                                      /* shut off interrupts around critical flush/invalidate sections */
     242        rlwinm  r4,r7,0,17,15           /* Turn off EE bit - an external exception while we are flushing
     243                                                                   the cache is fatal (comment this line and see!) */
     244        mtmsr   r4
     245        bne             dontDisableCache        /* Only disable the cache if L2CRApply has the enable bit off */
     246
     247        cmplwi  r0,PPC_7400                     /* > 7400 ? */
     248        bne             disableCache            /* use traditional method */
     249
     250        /* On the 7400, they recommend using the hardware flush feature */
     251        DSSALL                                          /* stop all data streams */
     252        sync
     253        /* we wouldn't have to flush L1, but for sake of consistency with the other code we do it anyway */
     254        mfspr   r4, MSSCR0
     255        oris    r4, r4, DL1HWF@h
     256        mtspr   MSSCR0, r4
     257        sync
     258        /* L1 flushed */
     259        mfspr   r4, L2CR
     260        ori             r4, r4, L2HWF
     261        mtspr   L2CR, r4
     262        sync
     263        /* L2 flushed */
     264        b               flushDone
    169265
    170266disableCache:
    171267        /* Disable the cache.  First, we turn off data relocation. */
    172         mfmsr   r7
    173         rlwinm  r4,r7,0,28,26           /* Turn off DR bit */
    174         rlwinm  r4,r4,0,17,15           /* Turn off EE bit - an external exception while we are flushing
    175                                            the cache is fatal (comment this line and see!) */
    176         sync
     268        rlwinm  r4,r4,0,28,26           /* Turn off DR bit */
    177269        mtmsr   r4
    178         sync
     270        isync                                           /* make sure memory accesses have completed */
    179271       
    180272        /*
     
    183275                the size of the L1 cache, but 2MB will cover everything just to be safe).
    184276        */
    185         lis     r4,0x0001
     277        lis             r4,0x0001
    186278        mtctr   r4
    187         li      r4,0
     279        li              r4,0
    188280loadLoop:
    189281        lwzx    r0,r0,r4
    190         addi    r4,r4,0x0020            /* Go to start of next cache line */
     282        addi    r4,r4,CACHE_LINE_SIZE   /* Go to start of next cache line */
    191283        bdnz    loadLoop
    192284       
    193285        /* Now, flush the first 2MB of memory */
    194         lis     r4,0x0001
     286        lis             r4,0x0001
    195287        mtctr   r4
    196         li      r4,0
     288        li              r4,0
    197289        sync
    198290flushLoop:
    199291        dcbf    r0,r4
    200         addi    r4,r4,0x0020    /* Go to start of next cache line */
     292        addi    r4,r4,CACHE_LINE_SIZE   /* Go to start of next cache line */
    201293        bdnz    flushLoop
     294        sync
     295
     296        rlwinm  r4,r7,0,17,15           /* still mask EE but reenable data relocation */
     297        mtmsr   r4
     298        isync
     299
     300flushDone:
    202301       
    203302        /* Turn off the L2CR enable bit. */
    204303        rlwinm  r3,r3,0,1,31
    205304       
    206         /* Reenable data relocation. */
    207         sync
    208         mtmsr   r7
    209         sync
    210        
    211305dontDisableCache:
    212306        /* Set up the L2CR configuration bits */
     
    220314        oris    r3,r3,0x0020
    221315        sync
    222         mtspr   1017,r3
    223         sync
    224 invalCompleteLoop:                      /* Wait for the invalidation to complete */
    225         mfspr   r3,1017
     316        mtspr   L2CR,r3
     317        sync
     318invalCompleteLoop:                              /* Wait for the invalidation to complete */
     319        mfspr   r3,L2CR
    226320        rlwinm. r4,r3,0,31,31
    227321        bne     invalCompleteLoop
     
    233327       
    234328noInval:
     329        /* re-enable interrupts, i.e. restore original MSR */
     330        mtmsr   r7                                      /* (no sync needed) */
    235331        /* See if we need to enable the cache */
    236332        cmplwi  r5,0
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c

    r78f8c91 r0d776cd2  
    2727ppc_cpu_revision_t current_ppc_revision = 0xff;
    2828
     29char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu)
     30{
     31  switch (cpu) {
     32    case PPC_601:               return "MPC601";
     33    case PPC_603:               return "MPC603";
     34    case PPC_603ev:             return "MPC603ev";
     35    case PPC_604:               return "MPC604";
     36    case PPC_750:               return "MPC750";
     37    case PPC_7400:              return "MPC7400";
     38    case PPC_604e:              return "MPC604e";
     39    case PPC_604r:              return "MPC604r";
     40    case PPC_620:               return "MPC620";
     41    case PPC_860:               return "MPC860";
     42    case PPC_8260:              return "MPC8260";
     43    default:
     44      printk("Unknown CPU value of 0x%x. Please add it to <libcpu/powerpc/shared/cpu.h>\n", cpu );
     45  }
     46  return "UNKNOWN";
     47}
     48
    2949ppc_cpu_id_t get_ppc_cpu_type()
    3050{
    3151  unsigned int pvr = (_read_PVR() >> 16);
    32 
    3352  current_ppc_cpu = (ppc_cpu_id_t) pvr;
    3453  switch (pvr) {
     
    3857    case PPC_604:
    3958    case PPC_750:
     59    case PPC_7400:
    4060    case PPC_604e:
    4161    case PPC_604r:
     
    4363    case PPC_860:
    4464    case PPC_8260:
    45       current_ppc_cpu = (ppc_cpu_id_t) pvr;
    4665      return current_ppc_cpu;
    4766    default:
     
    4968    return PPC_UNKNOWN;
    5069  }
    51  
    5270}
     71
    5372ppc_cpu_revision_t get_ppc_cpu_revision()
    5473{
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h

    r78f8c91 r0d776cd2  
    2828  PPC_604e = 0x9,
    2929  PPC_604r = 0xA,
     30  PPC_7400 = 0xA,
    3031  PPC_620 = 0x16,
    3132  PPC_860 = 0x50,
     
    3940extern ppc_cpu_id_t get_ppc_cpu_type ();
    4041extern ppc_cpu_id_t current_ppc_cpu;
     42extern char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu);
    4143extern ppc_cpu_revision_t get_ppc_cpu_revision ();
    4244extern ppc_cpu_revision_t current_ppc_revision;
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