Changeset 0cb50ab in rtems


Ignore:
Timestamp:
Jul 2, 2016, 12:33:11 PM (3 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
master
Children:
2d5902d6
Parents:
fe106ad5
git-author:
Pavel Pisa <pisa@…> (07/02/16 12:33:11)
git-committer:
Pavel Pisa <pisa@…> (07/04/16 13:55:57)
Message:

score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.

Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.

Location:
cpukit/score/cpu/arm/rtems/score
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/rtems/score/arm.h

    rfe106ad5 r0cb50ab  
    5555#endif
    5656
     57#if defined(__ARM_ARCH_7A__)
     58  #define ARM_MULTILIB_CACHE_LINE_MAX_64
     59#endif
     60
    5761#if !defined(__SOFTFP__)
    5862  #if defined(__ARM_NEON__)
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    rfe106ad5 r0cb50ab  
    146146#define CPU_STACK_GROWS_UP FALSE
    147147
    148 /* FIXME: Is this the right value? */
    149 #define CPU_CACHE_LINE_BYTES 32
     148#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64)
     149  #define CPU_CACHE_LINE_BYTES 32
     150#else
     151  #define CPU_CACHE_LINE_BYTES 64
     152#endif
    150153
    151154#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
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