Changeset 0c97890 in rtems-docs for cpu_supplement/sparc64.rst

Timestamp:

Oct 28, 2016, 6:07:04 PM (4 years ago)

Author:

Joel Sherrill <joel@…>

Branches:

4.11, 5, am, master

Children:

6941506

Parents:

23a5ce4

git-author:

Joel Sherrill <joel@…> (10/28/16 18:07:04)

git-committer:

Joel Sherrill <joel@…> (10/28/16 18:10:22)

Message:

powerpc, sparc, sparc64: Correct tables

File:

• cpu_supplement/sparc64.rst (modified) (3 diffs)

cpu_supplement/sparc64.rst

@@ -144 +144 @@
 registers and the register sets:
 
-    +-----------------+----------------+------------------+
-    | Register Number | Register Names |   Description    |
-    +-----------------+----------------+------------------+
-    |     0 - 7       |    g0 - g7     | Global Registers |
-    +-----------------+----------------+------------------+
-    |     8 - 15      |    o0 - o7     | Output Registers |
-    +-----------------+----------------+------------------+
-    |    16 - 23      |    l0 - l7     | Local Registers  |
-    +-----------------+----------------+------------------+
-    |    24 - 31      |    i0 - i7     | Input Registers  |
-    +-----------------+----------------+------------------+
+================ ================ ===================
+Register Number  Register Names   Description
+================ ================ ===================
+0 - 7            g0 - g7          Global Registers
+8 - 15           o0 - o7          Output Registers
+16 - 23          l0 - l7          Local Registers
+24 - 31          i0 - i7          Input Registers
+================ ================ ===================
 
 As mentioned above, some of the registers serve defined roles in the
@@ -160 +157 @@
 registers:
 
-    +---------------+----------------+----------------------+
-    | Register Name | Alternate Name |      Description     |
-    +---------------+----------------+----------------------+
-    |     g0        |      na        |    reads return 0    |
-    |               |                |  writes are ignored  |
-    +---------------+----------------+----------------------+
-    |     o6        |      sp        |     stack pointer    |
-    +---------------+----------------+----------------------+
-    |     i6        |      fp        |     frame pointer    |
-    +---------------+----------------+----------------------+
-    |     i7        |      na        |    return address    |
-    +---------------+----------------+----------------------+
+============== ================ ==================================
+Register Name  Alternate Name   Description
+============== ================ ==================================
+g0             na               reads return 0, writes are ignored
+o6             sp               stack pointer
+i6             fp               frame pointer
+i7             na               return address
+============== ================ ==================================
 
 Floating Point Registers
@@ -385 +378 @@
 the alignment requirements for a variety of data accesses:
 
-.. table::
-
-    +--------------+-----------------------+
-    |   Data Type  | Alignment Requirement |
-    +--------------+-----------------------+
-    |     byte     |          1            |
-    |   half-word  |          2            |
-    |     word     |          4            |
-    |  doubleword  |          8            |
-    |   quadword   |          16           |
-    +--------------+-----------------------+
+==============  ======================
+Data Type       Alignment Requirement
+==============  ======================
+byte            1
+half-word       2
+word            4
+doubleword      8
+quadword        16
+==============  ======================
 
 RTEMS currently does not support any SPARC Memory Management Units, therefore,